From: Walker Chen <walker.chen@starfivetech.com> To: <linux-riscv@lists.infradead.org>, <linux-pm@vger.kernel.org>, <devicetree@vger.kernel.org> Cc: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor.dooley@microchip.com>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, "Rafael J . Wysocki" <rafael@kernel.org>, Walker Chen <walker.chen@starfivetech.com>, <linux-kernel@vger.kernel.org> Subject: [RESEND PATCH v2 1/3] dt-bindings: power: Add starfive,jh71xx-pmu Date: Thu, 8 Dec 2022 16:45:21 +0800 [thread overview] Message-ID: <20221208084523.9733-2-walker.chen@starfivetech.com> (raw) In-Reply-To: <20221208084523.9733-1-walker.chen@starfivetech.com> Add bindings for Power Management Unit (PMU) on the StarFive JH71XX SoC. Signed-off-by: Walker Chen <walker.chen@starfivetech.com> --- .../bindings/power/starfive,jh71xx-pmu.yaml | 45 +++++++++++++++++++ .../dt-bindings/power/starfive,jh7110-pmu.h | 17 +++++++ 2 files changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/starfive,jh71xx-pmu.yaml create mode 100644 include/dt-bindings/power/starfive,jh7110-pmu.h diff --git a/Documentation/devicetree/bindings/power/starfive,jh71xx-pmu.yaml b/Documentation/devicetree/bindings/power/starfive,jh71xx-pmu.yaml new file mode 100644 index 000000000000..f308ae136a57 --- /dev/null +++ b/Documentation/devicetree/bindings/power/starfive,jh71xx-pmu.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/starfive,jh71xx-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH71xx Power Management Unit + +maintainers: + - Walker Chen <walker.chen@starfivetech.com> + +description: | + StarFive JH71xx SoCs include support for multiple power domains which can be + powered on/off by software based on different application scenes to save power. + +properties: + compatible: + - enum: + - starfive,jh7110-pmu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#power-domain-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - "#power-domain-cells" + +additionalProperties: false + +examples: + - | + pwrc: power-controller@17030000 { + compatible = "starfive,jh7110-pmu"; + reg = <0x17030000 0x10000>; + interrupts = <111>; + #power-domain-cells = <1>; + }; diff --git a/include/dt-bindings/power/starfive,jh7110-pmu.h b/include/dt-bindings/power/starfive,jh7110-pmu.h new file mode 100644 index 000000000000..73c6a79a2181 --- /dev/null +++ b/include/dt-bindings/power/starfive,jh7110-pmu.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Walker Chen <walker.chen@starfivetech.com> + */ +#ifndef __DT_BINDINGS_POWER_JH7110_POWER_H__ +#define __DT_BINDINGS_POWER_JH7110_POWER_H__ + +#define JH7110_PD_SYSTOP 0 +#define JH7110_PD_CPU 1 +#define JH7110_PD_GPUA 2 +#define JH7110_PD_VDEC 3 +#define JH7110_PD_VOUT 4 +#define JH7110_PD_ISP 5 +#define JH7110_PD_VENC 6 + +#endif -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Walker Chen <walker.chen@starfivetech.com> To: <linux-riscv@lists.infradead.org>, <linux-pm@vger.kernel.org>, <devicetree@vger.kernel.org> Cc: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor.dooley@microchip.com>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, "Rafael J . Wysocki" <rafael@kernel.org>, Walker Chen <walker.chen@starfivetech.com>, <linux-kernel@vger.kernel.org> Subject: [RESEND PATCH v2 1/3] dt-bindings: power: Add starfive,jh71xx-pmu Date: Thu, 8 Dec 2022 16:45:21 +0800 [thread overview] Message-ID: <20221208084523.9733-2-walker.chen@starfivetech.com> (raw) In-Reply-To: <20221208084523.9733-1-walker.chen@starfivetech.com> Add bindings for Power Management Unit (PMU) on the StarFive JH71XX SoC. Signed-off-by: Walker Chen <walker.chen@starfivetech.com> --- .../bindings/power/starfive,jh71xx-pmu.yaml | 45 +++++++++++++++++++ .../dt-bindings/power/starfive,jh7110-pmu.h | 17 +++++++ 2 files changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/starfive,jh71xx-pmu.yaml create mode 100644 include/dt-bindings/power/starfive,jh7110-pmu.h diff --git a/Documentation/devicetree/bindings/power/starfive,jh71xx-pmu.yaml b/Documentation/devicetree/bindings/power/starfive,jh71xx-pmu.yaml new file mode 100644 index 000000000000..f308ae136a57 --- /dev/null +++ b/Documentation/devicetree/bindings/power/starfive,jh71xx-pmu.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/starfive,jh71xx-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH71xx Power Management Unit + +maintainers: + - Walker Chen <walker.chen@starfivetech.com> + +description: | + StarFive JH71xx SoCs include support for multiple power domains which can be + powered on/off by software based on different application scenes to save power. + +properties: + compatible: + - enum: + - starfive,jh7110-pmu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#power-domain-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - "#power-domain-cells" + +additionalProperties: false + +examples: + - | + pwrc: power-controller@17030000 { + compatible = "starfive,jh7110-pmu"; + reg = <0x17030000 0x10000>; + interrupts = <111>; + #power-domain-cells = <1>; + }; diff --git a/include/dt-bindings/power/starfive,jh7110-pmu.h b/include/dt-bindings/power/starfive,jh7110-pmu.h new file mode 100644 index 000000000000..73c6a79a2181 --- /dev/null +++ b/include/dt-bindings/power/starfive,jh7110-pmu.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Walker Chen <walker.chen@starfivetech.com> + */ +#ifndef __DT_BINDINGS_POWER_JH7110_POWER_H__ +#define __DT_BINDINGS_POWER_JH7110_POWER_H__ + +#define JH7110_PD_SYSTOP 0 +#define JH7110_PD_CPU 1 +#define JH7110_PD_GPUA 2 +#define JH7110_PD_VDEC 3 +#define JH7110_PD_VOUT 4 +#define JH7110_PD_ISP 5 +#define JH7110_PD_VENC 6 + +#endif -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-12-08 8:46 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-08 8:45 [RESEND PATCH v2 0/3] JH7110 PMU Support Walker Chen 2022-12-08 8:45 ` Walker Chen 2022-12-08 8:45 ` Walker Chen [this message] 2022-12-08 8:45 ` [RESEND PATCH v2 1/3] dt-bindings: power: Add starfive,jh71xx-pmu Walker Chen 2022-12-08 8:59 ` Krzysztof Kozlowski 2022-12-08 8:59 ` Krzysztof Kozlowski 2022-12-12 2:46 ` Walker Chen 2022-12-12 2:46 ` Walker Chen 2022-12-08 9:03 ` Krzysztof Kozlowski 2022-12-08 9:03 ` Krzysztof Kozlowski 2022-12-12 3:19 ` Walker Chen 2022-12-12 3:19 ` Walker Chen 2022-12-08 13:31 ` Rob Herring 2022-12-08 13:31 ` Rob Herring 2022-12-12 6:33 ` Walker Chen 2022-12-12 6:33 ` Walker Chen 2022-12-08 8:45 ` [RESEND PATCH v2 2/3] soc: starfive: Add StarFive JH71XX pmu driver Walker Chen 2022-12-08 8:45 ` Walker Chen 2022-12-19 20:40 ` Conor Dooley 2022-12-19 20:40 ` Conor Dooley 2022-12-28 2:08 ` Walker Chen 2022-12-28 2:08 ` Walker Chen 2022-12-28 19:50 ` Conor Dooley 2022-12-28 19:50 ` Conor Dooley 2023-01-09 6:32 ` Walker Chen 2023-01-09 6:32 ` Walker Chen 2022-12-08 8:45 ` [RESEND PATCH v2 3/3] riscv: dts: starfive: add pmu controller node Walker Chen 2022-12-08 8:45 ` Walker Chen
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