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From: Samuel Holland <samuel@sholland.org>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Alexandre Ghiti <alexghiti@rivosinc.com>,
	linux-riscv@lists.infradead.org
Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org,
	Samuel Holland <samuel@sholland.org>
Subject: [PATCH 7/7] riscv: mm: Combine the SMP and non-SMP TLB flushing code
Date: Sat,  9 Sep 2023 15:16:35 -0500	[thread overview]
Message-ID: <20230909201727.10909-8-samuel@sholland.org> (raw)
In-Reply-To: <20230909201727.10909-1-samuel@sholland.org>

This allows non-SMP configurations to take advantage of improvements
to the code in tlbflush.c, such as support for huge pages and flushing
multiple-page ranges.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 arch/riscv/include/asm/tlbflush.h | 31 ++++++++-----------------------
 arch/riscv/mm/Makefile            |  5 +----
 arch/riscv/mm/tlbflush.c          |  7 ++++++-
 3 files changed, 15 insertions(+), 28 deletions(-)

diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h
index ba27cf68b170..a947ae3afd28 100644
--- a/arch/riscv/include/asm/tlbflush.h
+++ b/arch/riscv/include/asm/tlbflush.h
@@ -33,13 +33,12 @@ static inline void local_flush_tlb_page_asid(unsigned long addr,
 {
 	ALT_SFENCE_VMA_ADDR_ASID(addr, asid);
 }
-#else /* CONFIG_MMU */
-#define local_flush_tlb_all()			do { } while (0)
-#define local_flush_tlb_page(addr)		do { } while (0)
-#endif /* CONFIG_MMU */
 
-#if defined(CONFIG_SMP) && defined(CONFIG_MMU)
+#ifdef CONFIG_SMP
 void flush_tlb_all(void);
+#else
+#define flush_tlb_all() local_flush_tlb_all()
+#endif
 void flush_tlb_mm(struct mm_struct *mm);
 void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr);
 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
@@ -49,24 +48,10 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
 			unsigned long end);
 #endif
-#else /* CONFIG_SMP && CONFIG_MMU */
-
-#define flush_tlb_all() local_flush_tlb_all()
-#define flush_tlb_page(vma, addr) local_flush_tlb_page(addr)
-
-static inline void flush_tlb_mm(struct mm_struct *mm)
-{
-	unsigned long asid = cntx2asid(atomic_long_read(&mm->context.id));
-
-	local_flush_tlb_all_asid(asid);
-}
-
-static inline void flush_tlb_range(struct vm_area_struct *vma,
-		unsigned long start, unsigned long end)
-{
-	flush_tlb_mm(vma->vm_mm);
-}
-#endif /* !CONFIG_SMP || !CONFIG_MMU */
+#else /* CONFIG_MMU */
+#define local_flush_tlb_all()			do { } while (0)
+#define local_flush_tlb_page(addr)		do { } while (0)
+#endif /* CONFIG_MMU */
 
 /* Flush a range of kernel pages */
 static inline void flush_tlb_kernel_range(unsigned long start,
diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
index 9c454f90fd3d..64f901674e35 100644
--- a/arch/riscv/mm/Makefile
+++ b/arch/riscv/mm/Makefile
@@ -13,15 +13,12 @@ endif
 KCOV_INSTRUMENT_init.o := n
 
 obj-y += init.o
-obj-$(CONFIG_MMU) += extable.o fault.o pageattr.o
+obj-$(CONFIG_MMU) += extable.o fault.o pageattr.o tlbflush.o
 obj-y += cacheflush.o
 obj-y += context.o
 obj-y += pgtable.o
 obj-y += pmem.o
 
-ifeq ($(CONFIG_MMU),y)
-obj-$(CONFIG_SMP) += tlbflush.o
-endif
 obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
 obj-$(CONFIG_PTDUMP_CORE) += ptdump.o
 obj-$(CONFIG_KASAN)   += kasan_init.o
diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index 56c2d40681a2..587b3bb084b2 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -15,6 +15,7 @@ static inline void local_flush_tlb_range_asid(unsigned long start,
 		local_flush_tlb_all_asid(asid);
 }
 
+#ifdef CONFIG_SMP
 static void __ipi_flush_tlb_all(void *info)
 {
 	local_flush_tlb_all();
@@ -41,12 +42,12 @@ static void __ipi_flush_tlb_range_asid(void *info)
 
 	local_flush_tlb_range_asid(d->start, d->size, d->stride, d->asid);
 }
+#endif
 
 static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
 			      unsigned long size, unsigned long stride)
 {
 	unsigned long asid = cntx2asid(atomic_long_read(&mm->context.id));
-	struct flush_tlb_range_data ftd;
 	struct cpumask *cmask = mm_cpumask(mm);
 	unsigned int cpuid;
 
@@ -54,9 +55,12 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
 		return;
 
 	cpuid = get_cpu();
+#ifdef CONFIG_SMP
 	/* check if the tlbflush needs to be sent to other CPUs */
 	if (cpumask_any_but(cmask, cpuid) < nr_cpu_ids) {
 		if (riscv_use_ipi_for_rfence()) {
+			struct flush_tlb_range_data ftd;
+
 			ftd.asid = asid;
 			ftd.start = start;
 			ftd.size = size;
@@ -68,6 +72,7 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
 			sbi_remote_sfence_vma_asid(cmask,
 						   start, size, asid);
 	} else
+#endif
 		local_flush_tlb_range_asid(start, size, stride, asid);
 	put_cpu();
 }
-- 
2.41.0


WARNING: multiple messages have this Message-ID (diff)
From: Samuel Holland <samuel@sholland.org>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Alexandre Ghiti <alexghiti@rivosinc.com>,
	linux-riscv@lists.infradead.org
Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org,
	Samuel Holland <samuel@sholland.org>
Subject: [PATCH 7/7] riscv: mm: Combine the SMP and non-SMP TLB flushing code
Date: Sat,  9 Sep 2023 15:16:35 -0500	[thread overview]
Message-ID: <20230909201727.10909-8-samuel@sholland.org> (raw)
In-Reply-To: <20230909201727.10909-1-samuel@sholland.org>

This allows non-SMP configurations to take advantage of improvements
to the code in tlbflush.c, such as support for huge pages and flushing
multiple-page ranges.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 arch/riscv/include/asm/tlbflush.h | 31 ++++++++-----------------------
 arch/riscv/mm/Makefile            |  5 +----
 arch/riscv/mm/tlbflush.c          |  7 ++++++-
 3 files changed, 15 insertions(+), 28 deletions(-)

diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h
index ba27cf68b170..a947ae3afd28 100644
--- a/arch/riscv/include/asm/tlbflush.h
+++ b/arch/riscv/include/asm/tlbflush.h
@@ -33,13 +33,12 @@ static inline void local_flush_tlb_page_asid(unsigned long addr,
 {
 	ALT_SFENCE_VMA_ADDR_ASID(addr, asid);
 }
-#else /* CONFIG_MMU */
-#define local_flush_tlb_all()			do { } while (0)
-#define local_flush_tlb_page(addr)		do { } while (0)
-#endif /* CONFIG_MMU */
 
-#if defined(CONFIG_SMP) && defined(CONFIG_MMU)
+#ifdef CONFIG_SMP
 void flush_tlb_all(void);
+#else
+#define flush_tlb_all() local_flush_tlb_all()
+#endif
 void flush_tlb_mm(struct mm_struct *mm);
 void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr);
 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
@@ -49,24 +48,10 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
 			unsigned long end);
 #endif
-#else /* CONFIG_SMP && CONFIG_MMU */
-
-#define flush_tlb_all() local_flush_tlb_all()
-#define flush_tlb_page(vma, addr) local_flush_tlb_page(addr)
-
-static inline void flush_tlb_mm(struct mm_struct *mm)
-{
-	unsigned long asid = cntx2asid(atomic_long_read(&mm->context.id));
-
-	local_flush_tlb_all_asid(asid);
-}
-
-static inline void flush_tlb_range(struct vm_area_struct *vma,
-		unsigned long start, unsigned long end)
-{
-	flush_tlb_mm(vma->vm_mm);
-}
-#endif /* !CONFIG_SMP || !CONFIG_MMU */
+#else /* CONFIG_MMU */
+#define local_flush_tlb_all()			do { } while (0)
+#define local_flush_tlb_page(addr)		do { } while (0)
+#endif /* CONFIG_MMU */
 
 /* Flush a range of kernel pages */
 static inline void flush_tlb_kernel_range(unsigned long start,
diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
index 9c454f90fd3d..64f901674e35 100644
--- a/arch/riscv/mm/Makefile
+++ b/arch/riscv/mm/Makefile
@@ -13,15 +13,12 @@ endif
 KCOV_INSTRUMENT_init.o := n
 
 obj-y += init.o
-obj-$(CONFIG_MMU) += extable.o fault.o pageattr.o
+obj-$(CONFIG_MMU) += extable.o fault.o pageattr.o tlbflush.o
 obj-y += cacheflush.o
 obj-y += context.o
 obj-y += pgtable.o
 obj-y += pmem.o
 
-ifeq ($(CONFIG_MMU),y)
-obj-$(CONFIG_SMP) += tlbflush.o
-endif
 obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
 obj-$(CONFIG_PTDUMP_CORE) += ptdump.o
 obj-$(CONFIG_KASAN)   += kasan_init.o
diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index 56c2d40681a2..587b3bb084b2 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -15,6 +15,7 @@ static inline void local_flush_tlb_range_asid(unsigned long start,
 		local_flush_tlb_all_asid(asid);
 }
 
+#ifdef CONFIG_SMP
 static void __ipi_flush_tlb_all(void *info)
 {
 	local_flush_tlb_all();
@@ -41,12 +42,12 @@ static void __ipi_flush_tlb_range_asid(void *info)
 
 	local_flush_tlb_range_asid(d->start, d->size, d->stride, d->asid);
 }
+#endif
 
 static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
 			      unsigned long size, unsigned long stride)
 {
 	unsigned long asid = cntx2asid(atomic_long_read(&mm->context.id));
-	struct flush_tlb_range_data ftd;
 	struct cpumask *cmask = mm_cpumask(mm);
 	unsigned int cpuid;
 
@@ -54,9 +55,12 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
 		return;
 
 	cpuid = get_cpu();
+#ifdef CONFIG_SMP
 	/* check if the tlbflush needs to be sent to other CPUs */
 	if (cpumask_any_but(cmask, cpuid) < nr_cpu_ids) {
 		if (riscv_use_ipi_for_rfence()) {
+			struct flush_tlb_range_data ftd;
+
 			ftd.asid = asid;
 			ftd.start = start;
 			ftd.size = size;
@@ -68,6 +72,7 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
 			sbi_remote_sfence_vma_asid(cmask,
 						   start, size, asid);
 	} else
+#endif
 		local_flush_tlb_range_asid(start, size, stride, asid);
 	put_cpu();
 }
-- 
2.41.0


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  parent reply	other threads:[~2023-09-09 20:18 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-09 20:16 [PATCH 0/7] riscv: ASID-related and UP-related TLB flush enhancements Samuel Holland
2023-09-09 20:16 ` Samuel Holland
2023-09-09 20:16 ` [PATCH 1/7] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma Samuel Holland
2023-09-09 20:16   ` Samuel Holland
2023-09-09 20:16 ` [PATCH 2/7] riscv: mm: Introduce cntx2asid/cntx2version helper macros Samuel Holland
2023-09-09 20:16   ` Samuel Holland
2023-09-09 20:16 ` [PATCH 3/7] riscv: mm: Use a fixed layout for the MM context ID Samuel Holland
2023-09-09 20:16   ` Samuel Holland
2023-09-09 20:16 ` [PATCH 4/7] riscv: mm: Make asid_bits a local variable Samuel Holland
2023-09-09 20:16   ` Samuel Holland
2023-09-09 20:16 ` [PATCH 5/7] riscv: mm: Preserve global TLB entries when switching contexts Samuel Holland
2023-09-09 20:16   ` Samuel Holland
2023-09-09 20:16 ` [PATCH 6/7] riscv: mm: Always flush a single MM context by ASID Samuel Holland
2023-09-09 20:16   ` Samuel Holland
2023-09-10 19:46   ` Conor Dooley
2023-09-10 19:46     ` Conor Dooley
2023-10-26 15:53     ` Palmer Dabbelt
2023-10-26 15:53       ` Palmer Dabbelt
2023-09-09 20:16 ` Samuel Holland [this message]
2023-09-09 20:16   ` [PATCH 7/7] riscv: mm: Combine the SMP and non-SMP TLB flushing code Samuel Holland
2023-09-09 23:02   ` kernel test robot
2023-09-09 23:02     ` kernel test robot
2023-09-11 22:08   ` kernel test robot
2023-09-11 22:08     ` kernel test robot
2023-09-12  2:03   ` kernel test robot
2023-09-12  2:03     ` kernel test robot

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