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From: Claudiu <claudiu.beznea@tuxon.dev>
To: geert+renesas@glider.be, magnus.damm@gmail.com,
	robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org
Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: [PATCH 3/6] arm64: dts: renesas: r9a08g045: Add nodes for SDHI1 and SDHI2
Date: Tue, 10 Oct 2023 16:26:58 +0300	[thread overview]
Message-ID: <20231010132701.1658737-4-claudiu.beznea.uj@bp.renesas.com> (raw)
In-Reply-To: <20231010132701.1658737-1-claudiu.beznea.uj@bp.renesas.com>

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Add DT nodes for SDHI1 and SDHI2 available on RZ/G3S (R9A08G045).

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 7971e44a5a0a..534b728a8e14 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -118,6 +118,36 @@ sdhi0: mmc@11c00000  {
 			status = "disabled";
 		};
 
+		sdhi1: mmc@11c10000 {
+			compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
+			reg = <0x0 0x11c10000 0 0x10000>;
+			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>,
+				 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>,
+				 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>,
+				 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
+			clock-names = "core", "clkh", "cd", "aclk";
+			resets = <&cpg R9A08G045_SDHI1_IXRST>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		sdhi2: mmc@11c20000 {
+			compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
+			reg = <0x0 0x11c20000 0 0x10000>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>,
+				 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>,
+				 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>,
+				 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
+			clock-names = "core", "clkh", "cd", "aclk";
+			resets = <&cpg R9A08G045_SDHI2_IXRST>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@12400000 {
 			compatible = "arm,gic-v3";
 			#interrupt-cells = <3>;
-- 
2.39.2


  parent reply	other threads:[~2023-10-10 13:27 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-10 13:26 [PATCH 0/6] arm64: dts: renesas: Add SDHI1 and SDHI2 for RZ/G3S Claudiu
2023-10-10 13:26 ` [PATCH 1/6] clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R() Claudiu
2023-10-10 14:52   ` Sergei Shtylyov
2023-10-11  7:36     ` claudiu beznea
2023-10-11  7:43       ` Geert Uytterhoeven
2023-10-11 15:55         ` claudiu beznea
2023-10-12 12:37   ` Geert Uytterhoeven
2023-10-10 13:26 ` [PATCH 2/6] clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2 Claudiu
2023-10-12 13:22   ` Geert Uytterhoeven
2023-10-10 13:26 ` Claudiu [this message]
2023-10-12 13:35   ` [PATCH 3/6] arm64: dts: renesas: r9a08g045: Add nodes " Geert Uytterhoeven
2023-10-10 13:26 ` [PATCH 4/6] arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2 Claudiu
2023-10-12 14:36   ` Geert Uytterhoeven
2023-10-13  5:45     ` claudiu beznea
2023-10-10 13:27 ` [PATCH 5/6] arm64: dts: renesas: rzg3s-smarc: Enable SDHI1 Claudiu
2023-10-12 14:44   ` Geert Uytterhoeven
2023-10-13  5:51     ` claudiu beznea
2023-10-10 13:27 ` [PATCH 6/6] arm64: dts: renesas: rzg3s: Fix dtbs_check Claudiu
2023-10-12 14:49   ` Geert Uytterhoeven
2023-10-13  5:55     ` claudiu beznea

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