From: Atish Patra <atishp@rivosinc.com>
Cc: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Atish Patra <atishp@rivosinc.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
Weiwei Li <liwei1518@gmail.com>,
kaiwenxue1@gmail.com
Subject: [PATCH v5 3/5] target/riscv: Add cycle & instret privilege mode filtering definitions
Date: Wed, 28 Feb 2024 10:51:14 -0800 [thread overview]
Message-ID: <20240228185116.1321730-4-atishp@rivosinc.com> (raw)
In-Reply-To: <20240228185116.1321730-1-atishp@rivosinc.com>
From: Kaiwen Xue <kaiwenx@rivosinc.com>
This adds the definitions for ISA extension smcntrpmf.
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/cpu.h | 6 ++++++
target/riscv/cpu_bits.h | 29 +++++++++++++++++++++++++++++
2 files changed, 35 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f52dce78baa0..174e8ba8e847 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -338,6 +338,12 @@ struct CPUArchState {
target_ulong mcountinhibit;
+ /* PMU cycle & instret privilege mode filtering */
+ target_ulong mcyclecfg;
+ target_ulong mcyclecfgh;
+ target_ulong minstretcfg;
+ target_ulong minstretcfgh;
+
/* PMU counter state */
PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index fc2068ee4dcf..e866c60a400c 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -394,6 +394,10 @@
/* Machine counter-inhibit register */
#define CSR_MCOUNTINHIBIT 0x320
+/* Machine counter configuration registers */
+#define CSR_MCYCLECFG 0x321
+#define CSR_MINSTRETCFG 0x322
+
#define CSR_MHPMEVENT3 0x323
#define CSR_MHPMEVENT4 0x324
#define CSR_MHPMEVENT5 0x325
@@ -424,6 +428,9 @@
#define CSR_MHPMEVENT30 0x33e
#define CSR_MHPMEVENT31 0x33f
+#define CSR_MCYCLECFGH 0x721
+#define CSR_MINSTRETCFGH 0x722
+
#define CSR_MHPMEVENT3H 0x723
#define CSR_MHPMEVENT4H 0x724
#define CSR_MHPMEVENT5H 0x725
@@ -878,6 +885,28 @@ typedef enum RISCVException {
/* PMU related bits */
#define MIE_LCOFIE (1 << IRQ_PMU_OVF)
+#define MCYCLECFG_BIT_MINH BIT_ULL(62)
+#define MCYCLECFGH_BIT_MINH BIT(30)
+#define MCYCLECFG_BIT_SINH BIT_ULL(61)
+#define MCYCLECFGH_BIT_SINH BIT(29)
+#define MCYCLECFG_BIT_UINH BIT_ULL(60)
+#define MCYCLECFGH_BIT_UINH BIT(28)
+#define MCYCLECFG_BIT_VSINH BIT_ULL(59)
+#define MCYCLECFGH_BIT_VSINH BIT(27)
+#define MCYCLECFG_BIT_VUINH BIT_ULL(58)
+#define MCYCLECFGH_BIT_VUINH BIT(26)
+
+#define MINSTRETCFG_BIT_MINH BIT_ULL(62)
+#define MINSTRETCFGH_BIT_MINH BIT(30)
+#define MINSTRETCFG_BIT_SINH BIT_ULL(61)
+#define MINSTRETCFGH_BIT_SINH BIT(29)
+#define MINSTRETCFG_BIT_UINH BIT_ULL(60)
+#define MINSTRETCFGH_BIT_UINH BIT(28)
+#define MINSTRETCFG_BIT_VSINH BIT_ULL(59)
+#define MINSTRETCFGH_BIT_VSINH BIT(27)
+#define MINSTRETCFG_BIT_VUINH BIT_ULL(58)
+#define MINSTRETCFGH_BIT_VUINH BIT(26)
+
#define MHPMEVENT_BIT_OF BIT_ULL(63)
#define MHPMEVENTH_BIT_OF BIT(31)
#define MHPMEVENT_BIT_MINH BIT_ULL(62)
--
2.34.1
next prev parent reply other threads:[~2024-02-28 18:53 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-28 18:51 [PATCH v5 0/5] Add ISA extension smcntrpmf support Atish Patra
2024-02-28 18:51 ` [PATCH v5 1/5] target/riscv: Fix the predicate functions for mhpmeventhX CSRs Atish Patra
2024-03-05 7:03 ` LIU Zhiwei
2024-02-28 18:51 ` [PATCH v5 2/5] target/riscv: Add cycle & instret privilege mode filtering properties Atish Patra
2024-03-04 17:24 ` Daniel Henrique Barboza
2024-03-05 7:01 ` LIU Zhiwei
2024-03-07 9:27 ` Atish Patra
2024-02-28 18:51 ` Atish Patra [this message]
2024-02-28 18:51 ` [PATCH v5 4/5] target/riscv: Add cycle & instret privilege mode filtering support Atish Patra
2024-02-28 18:51 ` [PATCH v5 5/5] target/riscv: Implement privilege mode filtering for cycle/instret Atish Patra
2024-03-05 6:47 ` LIU Zhiwei
2024-03-07 9:25 ` Atish Patra
2024-03-20 4:54 ` Alistair Francis
2024-03-20 7:21 ` Atish Patra
2024-03-20 8:06 ` Alistair Francis
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