From: Zong Li <zong.li@sifive.com> To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, mhiramat@kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Zong Li <zong.li@sifive.com>, Palmer Dabbelt <palmerdabbelt@google.com> Subject: [PATCH v5 5/9] riscv: add ARCH_HAS_SET_DIRECT_MAP support Date: Wed, 8 Apr 2020 15:57:00 +0800 [thread overview] Message-ID: <357ebe77f7f676dcc7e828436275ec096fd61a96.1586332296.git.zong.li@sifive.com> (raw) In-Reply-To: <cover.1586332296.git.zong.li@sifive.com> Add set_direct_map_*() functions for setting the direct map alias for the page to its default permissions and to an invalid state that cannot be cached in a TLB. (See d253ca0c ("x86/mm/cpa: Add set_direct_map_*() functions")) Add a similar implementation for RISC-V. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/set_memory.h | 3 +++ arch/riscv/mm/pageattr.c | 24 ++++++++++++++++++++++++ 3 files changed, 28 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 9044e0dd95ea..a94d0f064d9c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -59,6 +59,7 @@ config RISCV select HAVE_EBPF_JIT if 64BIT select EDAC_SUPPORT select ARCH_HAS_GIGANTIC_PAGE + select ARCH_HAS_SET_DIRECT_MAP select ARCH_HAS_SET_MEMORY select ARCH_WANT_HUGE_PMD_SHARE if 64BIT select SPARSEMEM_STATIC if 32BIT diff --git a/arch/riscv/include/asm/set_memory.h b/arch/riscv/include/asm/set_memory.h index 79a810f0f38b..620d81c372d9 100644 --- a/arch/riscv/include/asm/set_memory.h +++ b/arch/riscv/include/asm/set_memory.h @@ -21,4 +21,7 @@ static inline int set_memory_x(unsigned long addr, int numpages) { return 0; } static inline int set_memory_nx(unsigned long addr, int numpages) { return 0; } #endif +int set_direct_map_invalid_noflush(struct page *page); +int set_direct_map_default_noflush(struct page *page); + #endif /* _ASM_RISCV_SET_MEMORY_H */ diff --git a/arch/riscv/mm/pageattr.c b/arch/riscv/mm/pageattr.c index fcd59ef2835b..7be6cd67e2ef 100644 --- a/arch/riscv/mm/pageattr.c +++ b/arch/riscv/mm/pageattr.c @@ -148,3 +148,27 @@ int set_memory_nx(unsigned long addr, int numpages) { return __set_memory(addr, numpages, __pgprot(0), __pgprot(_PAGE_EXEC)); } + +int set_direct_map_invalid_noflush(struct page *page) +{ + unsigned long start = (unsigned long)page_address(page); + unsigned long end = start + PAGE_SIZE; + struct pageattr_masks masks = { + .set_mask = __pgprot(0), + .clear_mask = __pgprot(_PAGE_PRESENT) + }; + + return walk_page_range(&init_mm, start, end, &pageattr_ops, &masks); +} + +int set_direct_map_default_noflush(struct page *page) +{ + unsigned long start = (unsigned long)page_address(page); + unsigned long end = start + PAGE_SIZE; + struct pageattr_masks masks = { + .set_mask = PAGE_KERNEL, + .clear_mask = __pgprot(0) + }; + + return walk_page_range(&init_mm, start, end, &pageattr_ops, &masks); +} -- 2.26.0
WARNING: multiple messages have this Message-ID (diff)
From: Zong Li <zong.li@sifive.com> To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, mhiramat@kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Palmer Dabbelt <palmerdabbelt@google.com>, Zong Li <zong.li@sifive.com> Subject: [PATCH v5 5/9] riscv: add ARCH_HAS_SET_DIRECT_MAP support Date: Wed, 8 Apr 2020 15:57:00 +0800 [thread overview] Message-ID: <357ebe77f7f676dcc7e828436275ec096fd61a96.1586332296.git.zong.li@sifive.com> (raw) In-Reply-To: <cover.1586332296.git.zong.li@sifive.com> Add set_direct_map_*() functions for setting the direct map alias for the page to its default permissions and to an invalid state that cannot be cached in a TLB. (See d253ca0c ("x86/mm/cpa: Add set_direct_map_*() functions")) Add a similar implementation for RISC-V. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/set_memory.h | 3 +++ arch/riscv/mm/pageattr.c | 24 ++++++++++++++++++++++++ 3 files changed, 28 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 9044e0dd95ea..a94d0f064d9c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -59,6 +59,7 @@ config RISCV select HAVE_EBPF_JIT if 64BIT select EDAC_SUPPORT select ARCH_HAS_GIGANTIC_PAGE + select ARCH_HAS_SET_DIRECT_MAP select ARCH_HAS_SET_MEMORY select ARCH_WANT_HUGE_PMD_SHARE if 64BIT select SPARSEMEM_STATIC if 32BIT diff --git a/arch/riscv/include/asm/set_memory.h b/arch/riscv/include/asm/set_memory.h index 79a810f0f38b..620d81c372d9 100644 --- a/arch/riscv/include/asm/set_memory.h +++ b/arch/riscv/include/asm/set_memory.h @@ -21,4 +21,7 @@ static inline int set_memory_x(unsigned long addr, int numpages) { return 0; } static inline int set_memory_nx(unsigned long addr, int numpages) { return 0; } #endif +int set_direct_map_invalid_noflush(struct page *page); +int set_direct_map_default_noflush(struct page *page); + #endif /* _ASM_RISCV_SET_MEMORY_H */ diff --git a/arch/riscv/mm/pageattr.c b/arch/riscv/mm/pageattr.c index fcd59ef2835b..7be6cd67e2ef 100644 --- a/arch/riscv/mm/pageattr.c +++ b/arch/riscv/mm/pageattr.c @@ -148,3 +148,27 @@ int set_memory_nx(unsigned long addr, int numpages) { return __set_memory(addr, numpages, __pgprot(0), __pgprot(_PAGE_EXEC)); } + +int set_direct_map_invalid_noflush(struct page *page) +{ + unsigned long start = (unsigned long)page_address(page); + unsigned long end = start + PAGE_SIZE; + struct pageattr_masks masks = { + .set_mask = __pgprot(0), + .clear_mask = __pgprot(_PAGE_PRESENT) + }; + + return walk_page_range(&init_mm, start, end, &pageattr_ops, &masks); +} + +int set_direct_map_default_noflush(struct page *page) +{ + unsigned long start = (unsigned long)page_address(page); + unsigned long end = start + PAGE_SIZE; + struct pageattr_masks masks = { + .set_mask = PAGE_KERNEL, + .clear_mask = __pgprot(0) + }; + + return walk_page_range(&init_mm, start, end, &pageattr_ops, &masks); +} -- 2.26.0
next prev parent reply other threads:[~2020-04-08 7:57 UTC|newest] Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-04-08 7:56 [PATCH v5 0/9] Support strict kernel memory permissions for security Zong Li 2020-04-08 7:56 ` [PATCH v5 1/9] riscv: add macro to get instruction length Zong Li 2020-04-18 0:22 ` Palmer Dabbelt 2020-04-18 0:22 ` Palmer Dabbelt 2020-04-08 7:56 ` [PATCH v5 2/9] riscv: introduce interfaces to patch kernel code Zong Li 2020-04-09 1:12 ` Masami Hiramatsu 2020-04-09 1:12 ` Masami Hiramatsu 2020-04-18 0:22 ` Palmer Dabbelt 2020-04-18 0:22 ` Palmer Dabbelt 2020-04-08 7:56 ` [PATCH v5 3/9] riscv: patch code by fixmap mapping Zong Li 2020-04-18 0:22 ` Palmer Dabbelt 2020-04-18 0:22 ` Palmer Dabbelt 2020-04-08 7:56 ` [PATCH v5 4/9] riscv: add ARCH_HAS_SET_MEMORY support Zong Li 2020-04-08 7:56 ` Zong Li 2020-04-08 7:57 ` Zong Li [this message] 2020-04-08 7:57 ` [PATCH v5 5/9] riscv: add ARCH_HAS_SET_DIRECT_MAP support Zong Li 2020-04-08 7:57 ` [PATCH v5 6/9] riscv: add ARCH_SUPPORTS_DEBUG_PAGEALLOC support Zong Li 2020-04-08 7:57 ` Zong Li 2020-04-08 7:57 ` [PATCH v5 7/9] riscv: move exception table immediately after RO_DATA Zong Li 2020-04-08 7:57 ` Zong Li 2020-04-08 7:57 ` [PATCH v5 8/9] riscv: add alignment for text, rodata and data sections Zong Li 2020-04-08 7:57 ` Zong Li 2020-04-08 7:57 ` [PATCH v5 9/9] riscv: add STRICT_KERNEL_RWX support Zong Li 2020-04-18 0:30 ` Palmer Dabbelt 2020-04-18 0:30 ` Palmer Dabbelt 2020-04-19 23:50 ` Damien Le Moal 2020-04-19 23:50 ` Damien Le Moal 2020-04-20 18:27 ` [PATCH v5 0/9] Support strict kernel memory permissions for security Palmer Dabbelt 2020-04-20 18:27 ` Palmer Dabbelt 2020-04-21 5:36 ` Zong Li 2020-04-21 5:36 ` Zong Li 2020-04-21 6:20 ` Anup Patel 2020-04-21 6:20 ` Anup Patel 2020-04-21 6:29 ` Zong Li 2020-04-21 6:29 ` Zong Li
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