From: BALATON Zoltan <balaton@eik.bme.hu>
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: clg@kaod.org, Daniel Henrique Barboza <danielhb413@gmail.com>,
Peter Maydell <peter.maydell@linaro.org>
Subject: [PATCH v4 13/21] ppc4xx_sdram: Rename functions to prevent name clashes
Date: Wed, 14 Sep 2022 13:34:26 +0200 (CEST) [thread overview]
Message-ID: <7997a8a82f43c124f8435b81332b9812e1ea19ce.1663154398.git.balaton@eik.bme.hu> (raw)
In-Reply-To: <cover.1663154398.git.balaton@eik.bme.hu>
Rename functions to avoid name clashes when moving the DDR2 controller
model currently called ppc440_sdram to ppc4xx_devs. This also more
clearly shows which function belongs to which model.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc440_uc.c | 69 ++++++++++++++++++++++----------------------
hw/ppc/ppc4xx_devs.c | 44 ++++++++++++++--------------
2 files changed, 57 insertions(+), 56 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index c316893944..fa313f979d 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -502,7 +502,7 @@ enum {
SDRAM_PLBADDUHB = 0x50,
};
-static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
+static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size)
{
uint32_t bcr;
@@ -547,12 +547,12 @@ static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
return bcr;
}
-static inline hwaddr sdram_base(uint32_t bcr)
+static inline hwaddr sdram_ddr2_base(uint32_t bcr)
{
return (bcr & 0xffe00000) << 2;
}
-static uint64_t sdram_size(uint32_t bcr)
+static uint64_t sdram_ddr2_size(uint32_t bcr)
{
uint64_t size;
int sh;
@@ -578,50 +578,51 @@ static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
object_unparent(OBJECT(&bank->container));
}
-static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
- uint32_t bcr, int enabled)
+static void sdram_ddr2_set_bcr(ppc440_sdram_t *sdram, int i,
+ uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 1) {
/* First unmap RAM if enabled */
- trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
- sdram_size(sdram->bank[i].bcr));
+ trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr),
+ sdram_ddr2_size(sdram->bank[i].bcr));
sdram_bank_unmap(&sdram->bank[i]);
}
sdram->bank[i].bcr = bcr & 0xffe0ffc1;
- sdram->bank[i].base = sdram_base(bcr);
- sdram->bank[i].size = sdram_size(bcr);
+ sdram->bank[i].base = sdram_ddr2_base(bcr);
+ sdram->bank[i].size = sdram_ddr2_size(bcr);
if (enabled && (bcr & 1)) {
- trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
+ trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr), sdram_ddr2_size(bcr));
sdram_bank_map(&sdram->bank[i]);
}
}
-static void sdram_map_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_map_bcr(ppc440_sdram_t *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->bank[i].size) {
- sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
+ sdram_ddr2_set_bcr(sdram, i,
+ sdram_ddr2_bcr(sdram->bank[i].base,
sdram->bank[i].size), 1);
} else {
- sdram_set_bcr(sdram, i, 0, 0);
+ sdram_ddr2_set_bcr(sdram, i, 0, 0);
}
}
}
-static void sdram_unmap_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_unmap_bcr(ppc440_sdram_t *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->bank[i].size) {
- sdram_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
+ sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
}
}
}
-static uint32_t dcr_read_sdram(void *opaque, int dcrn)
+static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
{
ppc440_sdram_t *sdram = opaque;
uint32_t ret = 0;
@@ -632,8 +633,8 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
case SDRAM_R2BAS:
case SDRAM_R3BAS:
if (sdram->bank[dcrn - SDRAM_R0BAS].size) {
- ret = sdram_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
- sdram->bank[dcrn - SDRAM_R0BAS].size);
+ ret = sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
+ sdram->bank[dcrn - SDRAM_R0BAS].size);
}
break;
case SDRAM_CONF1HB:
@@ -676,7 +677,7 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
#define SDRAM_DDR2_MCOPT2_DCEN BIT(27)
-static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
+static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
{
ppc440_sdram_t *sdram = opaque;
@@ -703,13 +704,13 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
(val & SDRAM_DDR2_MCOPT2_DCEN)) {
trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */
- sdram_map_bcr(sdram);
+ sdram_ddr2_map_bcr(sdram);
sdram->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN;
} else if ((sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
!(val & SDRAM_DDR2_MCOPT2_DCEN)) {
trace_ppc4xx_sdram_enable("disable");
/* invalidate all RAM mappings */
- sdram_unmap_bcr(sdram);
+ sdram_ddr2_unmap_bcr(sdram);
sdram->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN;
}
break;
@@ -722,7 +723,7 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
}
}
-static void sdram_reset(void *opaque)
+static void sdram_ddr2_reset(void *opaque)
{
ppc440_sdram_t *sdram = opaque;
@@ -743,30 +744,30 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
s->bank[i].base = ram_banks[i].base;
s->bank[i].size = ram_banks[i].size;
}
- qemu_register_reset(&sdram_reset, s);
+ qemu_register_reset(&sdram_ddr2_reset, s);
ppc_dcr_register(env, SDRAM0_CFGADDR,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM0_CFGDATA,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_R0BAS,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_R1BAS,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_R2BAS,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_R3BAS,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_CONF1HB,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_PLBADDULL,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_CONF1LL,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_CONFPATHB,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_PLBADDUHB,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
}
/*****************************************************************************/
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index bfe7b2d3a6..7655967351 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -81,12 +81,12 @@ static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
return bcr;
}
-static inline hwaddr sdram_base(uint32_t bcr)
+static inline hwaddr sdram_ddr_base(uint32_t bcr)
{
return bcr & 0xFF800000;
}
-static target_ulong sdram_size(uint32_t bcr)
+static target_ulong sdram_ddr_size(uint32_t bcr)
{
target_ulong size;
int sh;
@@ -101,13 +101,13 @@ static target_ulong sdram_size(uint32_t bcr)
return size;
}
-static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
- uint32_t bcr, int enabled)
+static void sdram_ddr_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
+ uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 1) {
/* Unmap RAM */
- trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
- sdram_size(sdram->bank[i].bcr));
+ trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
+ sdram_ddr_size(sdram->bank[i].bcr));
memory_region_del_subregion(get_system_memory(),
&sdram->bank[i].container);
memory_region_del_subregion(&sdram->bank[i].container,
@@ -116,38 +116,38 @@ static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
}
sdram->bank[i].bcr = bcr & 0xFFDEE001;
if (enabled && (bcr & 1)) {
- trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
+ trace_ppc4xx_sdram_map(sdram_ddr_base(bcr), sdram_ddr_size(bcr));
memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
- sdram_size(bcr));
+ sdram_ddr_size(bcr));
memory_region_add_subregion(&sdram->bank[i].container, 0,
&sdram->bank[i].ram);
memory_region_add_subregion(get_system_memory(),
- sdram_base(bcr),
+ sdram_ddr_base(bcr),
&sdram->bank[i].container);
}
}
-static void sdram_map_bcr(Ppc4xxSdramDdrState *sdram)
+static void sdram_ddr_map_bcr(Ppc4xxSdramDdrState *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->bank[i].size != 0) {
- sdram_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
- sdram->bank[i].size), 1);
+ sdram_ddr_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
+ sdram->bank[i].size), 1);
} else {
- sdram_set_bcr(sdram, i, 0, 0);
+ sdram_ddr_set_bcr(sdram, i, 0, 0);
}
}
}
-static void sdram_unmap_bcr(Ppc4xxSdramDdrState *sdram)
+static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
- trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
- sdram_size(sdram->bank[i].bcr));
+ trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
+ sdram_ddr_size(sdram->bank[i].bcr));
memory_region_del_subregion(get_system_memory(),
&sdram->bank[i].ram);
}
@@ -244,12 +244,12 @@ static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */
- sdram_map_bcr(sdram);
+ sdram_ddr_map_bcr(sdram);
sdram->status &= ~0x80000000;
} else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
trace_ppc4xx_sdram_enable("disable");
/* invalidate all RAM mappings */
- sdram_unmap_bcr(sdram);
+ sdram_ddr_unmap_bcr(sdram);
sdram->status |= 0x80000000;
}
if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) {
@@ -269,16 +269,16 @@ static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
sdram->pmit = (val & 0xF8000000) | 0x07C00000;
break;
case 0x40: /* SDRAM_B0CR */
- sdram_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000);
break;
case 0x44: /* SDRAM_B1CR */
- sdram_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000);
break;
case 0x48: /* SDRAM_B2CR */
- sdram_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000);
break;
case 0x4C: /* SDRAM_B3CR */
- sdram_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000);
break;
case 0x80: /* SDRAM_TR */
sdram->tr = val & 0x018FC01F;
--
2.30.4
next prev parent reply other threads:[~2022-09-14 12:27 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-14 11:34 [PATCH v4 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 01/21] ppc440_bamboo: Remove unnecessary memsets BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 02/21] ppc4xx: Introduce Ppc4xxSdramBank struct BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 03/21] ppc4xx_sdram: Get rid of the init RAM hack BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 04/21] ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks() BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 05/21] ppc440_bamboo: Add missing 4 MiB valid memory size BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 06/21] ppc4xx_sdram: Move size check to ppc4xx_sdram_init() BALATON Zoltan
2022-09-17 21:54 ` Philippe Mathieu-Daudé via
2022-09-14 11:34 ` [PATCH v4 07/21] ppc4xx_sdram: QOM'ify BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 08/21] ppc4xx_sdram: Drop extra zeros for readability BALATON Zoltan
2022-09-17 22:12 ` Philippe Mathieu-Daudé via
2022-09-14 11:34 ` [PATCH v4 09/21] ppc440_sdram: Split off map/unmap of sdram banks for later reuse BALATON Zoltan
2022-09-17 22:14 ` Philippe Mathieu-Daudé via
2022-09-14 11:34 ` [PATCH v4 10/21] ppc440_sdram: Implement enable bit in the DDR2 SDRAM BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 11/21] ppc440_sdram: Get rid of the init RAM hack BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 12/21] ppc440_sdram: Rename local variable for readability BALATON Zoltan
2022-09-14 11:34 ` BALATON Zoltan [this message]
2022-09-17 22:15 ` [PATCH v4 13/21] ppc4xx_sdram: Rename functions to prevent name clashes Philippe Mathieu-Daudé via
2022-09-14 11:34 ` [PATCH v4 14/21] ppc440_sdram: Move RAM size check to ppc440_sdram_init BALATON Zoltan
2022-09-17 22:16 ` Philippe Mathieu-Daudé via
2022-09-18 9:59 ` BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 15/21] ppc440_sdram: QOM'ify BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 16/21] ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models together BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 17/21] ppc4xx_sdram: Use hwaddr for memory bank size BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 18/21] ppc4xx_sdram: Rename local state variable for brevity BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 19/21] ppc4xx_sdram: Generalise bank setup BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 20/21] ppc4xx_sdram: Convert DDR SDRAM controller to new bank handling BALATON Zoltan
2022-09-14 11:34 ` [PATCH v4 21/21] ppc4xx_sdram: Add errp parameter to ppc4xx_sdram_banks() BALATON Zoltan
2022-09-17 22:18 ` Philippe Mathieu-Daudé via
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