From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com
Subject: [Qemu-devel] [PATCH v1 23/27] target/riscv: Allow specifying MMU stage
Date: Fri, 7 Jun 2019 14:56:32 -0700 [thread overview]
Message-ID: <e81fa46ccf6fc243e86046ba8fa7b6cdaf21bcd6.1559944445.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1559944445.git.alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 35 +++++++++++++++++++++++++++--------
1 file changed, 27 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b009049cc4..6cef78a2c7 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -274,10 +274,19 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
*
* Adapted from Spike's mmu_t::translate and mmu_t::walk
*
+ * @env: CPURISCVState
+ * @physical: This will be set to the calculated physical address
+ * @prot: The returned protection attributes
+ * @addr: The virtual address to be translated
+ * @access_type: The type of MMU access
+ * @mmu_idx: Indicates current privilege level
+ * @first_stage: Are we in first stage translation?
+ * Second stage is used for hypervisor guest translation
*/
static int get_physical_address(CPURISCVState *env, hwaddr *physical,
int *prot, target_ulong addr,
- int access_type, int mmu_idx)
+ int access_type, int mmu_idx,
+ bool first_stage)
{
/* NOTE: the env->pc value visible here will not be
* correct, but the value visible to the exception handler
@@ -468,12 +477,20 @@ restart:
}
static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
- MMUAccessType access_type)
+ MMUAccessType access_type, bool first_stage)
{
CPUState *cs = CPU(riscv_env_get_cpu(env));
- int page_fault_exceptions =
- (env->priv_ver >= PRIV_VERSION_1_10_0) &&
- get_field(env->satp, SATP_MODE) != VM_1_10_MBARE;
+ int page_fault_exceptions;
+ if (first_stage) {
+ page_fault_exceptions =
+ (env->priv_ver >= PRIV_VERSION_1_10_0) &&
+ get_field(env->satp, SATP_MODE) != VM_1_10_MBARE;
+ riscv_cpu_set_force_hs_excep(env, CLEAR_HS_EXCEP);
+ } else {
+ page_fault_exceptions =
+ get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE;
+ riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP);
+ }
switch (access_type) {
case MMU_INST_FETCH:
cs->exception_index = page_fault_exceptions ?
@@ -500,7 +517,8 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
int prot;
int mmu_idx = cpu_mmu_index(&cpu->env, false);
- if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx)) {
+ if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx,
+ true)) {
return -1;
}
return phys_addr;
@@ -560,7 +578,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, address, access_type, mmu_idx);
- ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx);
+ ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx,
+ true);
qemu_log_mask(CPU_LOG_MMU,
"%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
@@ -577,7 +596,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
} else if (probe) {
return false;
} else {
- raise_mmu_exception(env, address, access_type);
+ raise_mmu_exception(env, address, access_type, true);
riscv_raise_exception(env, cs->exception_index, retaddr);
}
#else
--
2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@sifive.com, alistair.francis@wdc.com, alistair23@gmail.com
Subject: [Qemu-riscv] [PATCH v1 23/27] target/riscv: Allow specifying MMU stage
Date: Fri, 7 Jun 2019 14:56:32 -0700 [thread overview]
Message-ID: <e81fa46ccf6fc243e86046ba8fa7b6cdaf21bcd6.1559944445.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1559944445.git.alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 35 +++++++++++++++++++++++++++--------
1 file changed, 27 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b009049cc4..6cef78a2c7 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -274,10 +274,19 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
*
* Adapted from Spike's mmu_t::translate and mmu_t::walk
*
+ * @env: CPURISCVState
+ * @physical: This will be set to the calculated physical address
+ * @prot: The returned protection attributes
+ * @addr: The virtual address to be translated
+ * @access_type: The type of MMU access
+ * @mmu_idx: Indicates current privilege level
+ * @first_stage: Are we in first stage translation?
+ * Second stage is used for hypervisor guest translation
*/
static int get_physical_address(CPURISCVState *env, hwaddr *physical,
int *prot, target_ulong addr,
- int access_type, int mmu_idx)
+ int access_type, int mmu_idx,
+ bool first_stage)
{
/* NOTE: the env->pc value visible here will not be
* correct, but the value visible to the exception handler
@@ -468,12 +477,20 @@ restart:
}
static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
- MMUAccessType access_type)
+ MMUAccessType access_type, bool first_stage)
{
CPUState *cs = CPU(riscv_env_get_cpu(env));
- int page_fault_exceptions =
- (env->priv_ver >= PRIV_VERSION_1_10_0) &&
- get_field(env->satp, SATP_MODE) != VM_1_10_MBARE;
+ int page_fault_exceptions;
+ if (first_stage) {
+ page_fault_exceptions =
+ (env->priv_ver >= PRIV_VERSION_1_10_0) &&
+ get_field(env->satp, SATP_MODE) != VM_1_10_MBARE;
+ riscv_cpu_set_force_hs_excep(env, CLEAR_HS_EXCEP);
+ } else {
+ page_fault_exceptions =
+ get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE;
+ riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP);
+ }
switch (access_type) {
case MMU_INST_FETCH:
cs->exception_index = page_fault_exceptions ?
@@ -500,7 +517,8 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
int prot;
int mmu_idx = cpu_mmu_index(&cpu->env, false);
- if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx)) {
+ if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx,
+ true)) {
return -1;
}
return phys_addr;
@@ -560,7 +578,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, address, access_type, mmu_idx);
- ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx);
+ ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx,
+ true);
qemu_log_mask(CPU_LOG_MMU,
"%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
@@ -577,7 +596,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
} else if (probe) {
return false;
} else {
- raise_mmu_exception(env, address, access_type);
+ raise_mmu_exception(env, address, access_type, true);
riscv_raise_exception(env, cs->exception_index, retaddr);
}
#else
--
2.21.0
next prev parent reply other threads:[~2019-06-07 22:07 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-07 21:55 [Qemu-devel] [PATCH v1 00/27] Add RISC-V Hypervisor Extension Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 01/27] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 02/27] target/riscv: Add the Hypervisor extension Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 03/27] target/riscv: Add the virtulisation mode Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 04/27] target/riscv: Add the force HS exception mode Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 05/27] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 06/27] target/riscv: Dump Hypervisor registers if enabled Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 07/27] target/riscv: Remove strict perm checking for CSR R/W Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 08/27] target/riscv: Create function to test if FP is enabled Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 09/27] target/riscv: Add support for background interrupt setting Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 10/27] target/riscv: Add Hypervisor CSR access functions Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 11/27] target/riscv: Add background CSRs accesses Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 12/27] target/riscv: Add background register swapping function Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 13/27] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 14/27] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 15/27] riscv: plic: Remove unused interrupt functions Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 16/27] riscv: plic: Always set sip.SEIP bit for HS Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 17/27] target/riscv: Add hypvervisor trap support Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 18/27] target/riscv: Add Hypervisor trap return support Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 19/27] target/riscv: Add hfence instructions Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 20/27] target/riscv: Disable guest FP support based on backgrond status Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 21/27] target/riscv: Mark both sstatus and bsstatus as dirty Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 22/27] target/riscv: Respect MPRV and SPRV for floating point ops Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` Alistair Francis [this message]
2019-06-07 21:56 ` [Qemu-riscv] [PATCH v1 23/27] target/riscv: Allow specifying MMU stage Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 24/27] target/riscv: Allow specifying number of MMU stages Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 25/27] target/riscv: Implement second stage MMU Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 26/27] target/riscv: Call the second stage MMU in virtualisation mode Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 27/27] target/riscv: Allow enabling the Hypervisor extension Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-07-15 11:50 ` [Qemu-devel] [PATCH v1 00/27] Add RISC-V Hypervisor Extension Chih-Min Chao
2019-07-15 11:50 ` [Qemu-riscv] " Chih-Min Chao
2019-07-17 0:13 ` Alistair Francis
2019-07-17 0:13 ` [Qemu-riscv] " Alistair Francis
2019-07-15 11:59 ` Peter Maydell
2019-07-15 11:59 ` [Qemu-riscv] " Peter Maydell
2019-07-17 0:14 ` Alistair Francis
2019-07-17 0:14 ` [Qemu-riscv] " Alistair Francis
2019-07-17 3:55 ` Chih-Min Chao
2019-07-17 3:55 ` [Qemu-riscv] " Chih-Min Chao
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=e81fa46ccf6fc243e86046ba8fa7b6cdaf21bcd6.1559944445.git.alistair.francis@wdc.com \
--to=alistair.francis@wdc.com \
--cc=alistair23@gmail.com \
--cc=palmer@sifive.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.