* [PATCH v3 1/3] dt-bindings: arm: qcom: Document SDX65 platform and boards
2021-10-30 0:02 [PATCH v3 0/3] Add devicetree support for SDX65 Modem and MTP quic_vamslank
@ 2021-10-30 0:02 ` quic_vamslank
2021-10-30 0:02 ` [PATCH v3 2/3] ARM: dts: qcom: Add SDX65 platform and MTP board support quic_vamslank
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: quic_vamslank @ 2021-10-30 0:02 UTC (permalink / raw)
To: agross, bjorn.andersson, olof, soc, linus.walleij, sboyd, robh+dt
Cc: linux-arm-msm, linux-kernel, devicetree, linux-gpio,
manivannan.sadhasivam, Vamsi krishna Lanka
From: Vamsi krishna Lanka <quic_vamslank@quicinc.com>
Document the SDX65 platform binding and also the boards using it.
Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 880ddaf..813a5a4 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -45,6 +45,7 @@ description: |
sdm845
sdx55
sm8150
+ sdx65
sm8250
sm8350
@@ -208,6 +209,11 @@ properties:
- items:
- enum:
+ - qcom,sdx65-mtp
+ - const: qcom,sdx65
+
+ - items:
+ - enum:
- qcom,ipq6018-cp01
- qcom,ipq6018-cp01-c1
- const: qcom,ipq6018
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v3 2/3] ARM: dts: qcom: Add SDX65 platform and MTP board support
2021-10-30 0:02 [PATCH v3 0/3] Add devicetree support for SDX65 Modem and MTP quic_vamslank
2021-10-30 0:02 ` [PATCH v3 1/3] dt-bindings: arm: qcom: Document SDX65 platform and boards quic_vamslank
@ 2021-10-30 0:02 ` quic_vamslank
2021-10-30 0:02 ` [PATCH v3 3/3] ARM: dts: qcom: sdx65: Add pincontrol node quic_vamslank
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: quic_vamslank @ 2021-10-30 0:02 UTC (permalink / raw)
To: agross, bjorn.andersson, olof, soc, linus.walleij, sboyd, robh+dt
Cc: linux-arm-msm, linux-kernel, devicetree, linux-gpio,
manivannan.sadhasivam, Vamsi krishna Lanka
From: Vamsi krishna Lanka <quic_vamslank@quicinc.com>
Add basic devicetree support for SDX65 platform and MTP board from
Qualcomm. The SDX65 platform features an ARM Cortex A7 CPU which forms
the Application Processor Sub System (APSS) along with standard Qualcomm
peripherals like GCC, TLMM, BLSP, QPIC, and BAM etc... Also, there
exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem
etc..
This commit adds basic devicetree support that includes GCC, RPMh clock, INTC
and Debug UART.
Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/qcom-sdx65-mtp.dts | 25 +++++
arch/arm/boot/dts/qcom-sdx65.dtsi | 210 +++++++++++++++++++++++++++++++++++
3 files changed, 237 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/qcom-sdx65-mtp.dts
create mode 100644 arch/arm/boot/dts/qcom-sdx65.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7e09341..a467c66 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -969,7 +969,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-mdm9615-wp8548-mangoh-green.dtb \
qcom-sdx55-mtp.dtb \
qcom-sdx55-t55.dtb \
- qcom-sdx55-telit-fn980-tlb.dtb
+ qcom-sdx55-telit-fn980-tlb.dtb \
+ qcom-sdx65-mtp.dtb
dtb-$(CONFIG_ARCH_RDA) += \
rda8810pl-orangepi-2g-iot.dtb \
rda8810pl-orangepi-i96.dtb
diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
new file mode 100644
index 0000000..59457da
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+/dts-v1/;
+
+#include "qcom-sdx65.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDX65 MTP";
+ compatible = "qcom,sdx65-mtp", "qcom,sdx65";
+ qcom,board-id = <0x2010008 0x302>;
+
+ aliases {
+ serial0 = &blsp1_uart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&blsp1_uart3 {
+ status = "ok";
+};
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
new file mode 100644
index 0000000..5aecb00
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -0,0 +1,210 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * SDX65 SoC device tree source
+ *
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ */
+
+#include <dt-bindings/clock/qcom,gcc-sdx65.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
+ interrupt-parent = <&intc>;
+
+ memory {
+ device_type = "memory";
+ reg = <0 0>;
+ };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <76800000>;
+ clock-output-names = "xo_board";
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32764>;
+ clock-output-names = "sleep_clk";
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ cmd_db: reserved-memory@8fee0000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x8fee0000 0x20000>;
+ no-map;
+ };
+ };
+
+ soc: soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "simple-bus";
+
+ gcc: clock-controller@100000 {
+ compatible = "qcom,gcc-sdx65";
+ reg = <0x00100000 0x001f7400>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>;
+ clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ blsp1_uart3: serial@831000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x00831000 0x200>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ pdc: interrupt-controller@b210000 {
+ compatible = "qcom,sdx65-pdc", "qcom,pdc";
+ reg = <0xb210000 0x10000>;
+ qcom,pdc-ranges = <0 147 52>, <52 266 32>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ intc: interrupt-controller@17800000 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <3>;
+ reg = <0x17800000 0x1000>,
+ <0x17802000 0x1000>;
+ };
+
+ timer@17820000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x17820000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@17821000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 7 0x4>,
+ <GIC_SPI 6 0x4>;
+ reg = <0x17821000 0x1000>,
+ <0x17822000 0x1000>;
+ };
+
+ frame@17823000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 8 0x4>;
+ reg = <0x17823000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17824000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 9 0x4>;
+ reg = <0x17824000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17825000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 10 0x4>;
+ reg = <0x17825000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17826000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 11 0x4>;
+ reg = <0x17826000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17827000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 12 0x4>;
+ reg = <0x17827000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17828000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 13 0x4>;
+ reg = <0x17828000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17829000 {
+ frame-number = <7>;
+ interrupts = <GIC_SPI 14 0x4>;
+ reg = <0x17829000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ apps_rsc: rsc@17830000 {
+ label = "apps_rsc";
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x17830000 0x10000>,
+ <0x17840000 0x10000>;
+ reg-names = "drv-0", "drv-1";
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <1>;
+ qcom,tcs-config = <ACTIVE_TCS 2>,
+ <SLEEP_TCS 2>,
+ <WAKE_TCS 2>,
+ <CONTROL_TCS 1>;
+
+ rpmhcc: clock-controller@1 {
+ compatible = "qcom,sdx65-rpmh-clk";
+ #clock-cells = <1>;
+ clock-names = "xo";
+ clocks = <&xo_board>;
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 13 0xf08>,
+ <1 12 0xf08>,
+ <1 10 0xf08>,
+ <1 11 0xf08>;
+ clock-frequency = <19200000>;
+ };
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v3 3/3] ARM: dts: qcom: sdx65: Add pincontrol node
2021-10-30 0:02 [PATCH v3 0/3] Add devicetree support for SDX65 Modem and MTP quic_vamslank
2021-10-30 0:02 ` [PATCH v3 1/3] dt-bindings: arm: qcom: Document SDX65 platform and boards quic_vamslank
2021-10-30 0:02 ` [PATCH v3 2/3] ARM: dts: qcom: Add SDX65 platform and MTP board support quic_vamslank
@ 2021-10-30 0:02 ` quic_vamslank
2021-12-02 0:34 ` [PATCH v3 0/3] Add devicetree support for SDX65 Modem and MTP Vamsi Krishna Lanka
2021-12-15 22:27 ` Bjorn Andersson
4 siblings, 0 replies; 8+ messages in thread
From: quic_vamslank @ 2021-10-30 0:02 UTC (permalink / raw)
To: agross, bjorn.andersson, olof, soc, linus.walleij, sboyd, robh+dt
Cc: linux-arm-msm, linux-kernel, devicetree, linux-gpio,
manivannan.sadhasivam, Vamsi krishna Lanka
From: Vamsi krishna Lanka <quic_vamslank@quicinc.com>
This commit adds pincontrol node to SDX65 dts.
Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 5aecb00..796641d 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -91,6 +91,18 @@
status = "disabled";
};
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,sdx65-tlmm";
+ reg = <0xf100000 0x300000>;
+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 109>;
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <2>;
+ };
+
pdc: interrupt-controller@b210000 {
compatible = "qcom,sdx65-pdc", "qcom,pdc";
reg = <0xb210000 0x10000>;
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v3 0/3] Add devicetree support for SDX65 Modem and MTP
2021-10-30 0:02 [PATCH v3 0/3] Add devicetree support for SDX65 Modem and MTP quic_vamslank
` (2 preceding siblings ...)
2021-10-30 0:02 ` [PATCH v3 3/3] ARM: dts: qcom: sdx65: Add pincontrol node quic_vamslank
@ 2021-12-02 0:34 ` Vamsi Krishna Lanka
2021-12-15 22:27 ` Bjorn Andersson
4 siblings, 0 replies; 8+ messages in thread
From: Vamsi Krishna Lanka @ 2021-12-02 0:34 UTC (permalink / raw)
To: agross, bjorn.andersson, olof, soc, linus.walleij, sboyd, robh+dt
Cc: linux-arm-msm, linux-kernel, devicetree, linux-gpio,
manivannan.sadhasivam
On Fri, Oct 29, 2021 at 05:02:02PM -0700, quic_vamslank@quicinc.com wrote:
> From: Vamsi Krishna Lanka <quic_vamslank@quicinc.com>
>
> Hello,
>
> Changes from v2:
> - Added cmd-db node to the sdx65 dtsi file
>
> Changes from v1:
> - Addressed Bjorn's comments
>
> This series adds devicetree support for Qualcomm SDX65 platform and MTP
> board. This series functionally depends on Add Pdc, GCC and RPMh Clock support
> series [1] and Add pinctrl support for SDX65 [2] which are under review.
>
> With this current devicetree support, the MTP can boot into initramfs
> shell.
>
> Thanks,
> Vamsi
Can you please review this patch series. It's been pending since longtime now.
Thanks,
Vamsi
>
> Vamsi krishna Lanka (3):
> dt-bindings: arm: qcom: Document SDX65 platform and boards
> ARM: dts: qcom: Add SDX65 platform and MTP board support
> ARM: dts: qcom: sdx65: Add pincontrol node
>
> Documentation/devicetree/bindings/arm/qcom.yaml | 6 +
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/qcom-sdx65-mtp.dts | 25 +++
> arch/arm/boot/dts/qcom-sdx65.dtsi | 222 ++++++++++++++++++++++++
> 4 files changed, 255 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/qcom-sdx65-mtp.dts
> create mode 100644 arch/arm/boot/dts/qcom-sdx65.dtsi
>
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 8+ messages in thread