* [tip: x86/urgent] x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN
[not found] <20220121174743.1875294-2-tony.luck@intel.com>
@ 2022-01-25 17:55 ` tip-bot2 for Tony Luck
0 siblings, 0 replies; only message in thread
From: tip-bot2 for Tony Luck @ 2022-01-25 17:55 UTC (permalink / raw)
To: linux-tip-commits
Cc: Ailin Xu, Tony Luck, Borislav Petkov, stable, x86, linux-kernel
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: e464121f2d40eabc7d11823fb26db807ce945df4
Gitweb: https://git.kernel.org/tip/e464121f2d40eabc7d11823fb26db807ce945df4
Author: Tony Luck <tony.luck@intel.com>
AuthorDate: Fri, 21 Jan 2022 09:47:38 -08:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Tue, 25 Jan 2022 18:40:30 +01:00
x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN
Missed adding the Icelake-D CPU to the list. It uses the same MSRs
to control and read the inventory number as all the other models.
Fixes: dc6b025de95b ("x86/mce: Add Xeon Icelake to list of CPUs that support PPIN")
Reported-by: Ailin Xu <ailin.xu@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20220121174743.1875294-2-tony.luck@intel.com
---
arch/x86/kernel/cpu/mce/intel.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index bb9a46a..baafbb3 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
case INTEL_FAM6_BROADWELL_X:
case INTEL_FAM6_SKYLAKE_X:
case INTEL_FAM6_ICELAKE_X:
+ case INTEL_FAM6_ICELAKE_D:
case INTEL_FAM6_SAPPHIRERAPIDS_X:
case INTEL_FAM6_XEON_PHI_KNL:
case INTEL_FAM6_XEON_PHI_KNM:
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2022-01-25 17:55 ` [tip: x86/urgent] x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN tip-bot2 for Tony Luck
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