[PATCH] drm/i915: disable sampler indirect state in bindless heap

[PATCH] drm/i915: disable sampler indirect state in bindless heap

[Lionel Landwerlin]

By default the indirect state sampler data (border colors) are stored
in the same heap as the SAMPLER_STATE structure. For userspace drivers
that can be 2 different heaps (dynamic state heap & bindless sampler
state heap). This means that border colors have to copied in 2
different places so that the same SAMPLER_STATE structure find the
right data.

This change is forcing the indirect state sampler data to only be in
the dynamic state pool (more convinient for userspace drivers, they
only have to have one copy of the border colors). This is reproducing
the behavior of the Windows drivers.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 +++++++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 08d76aa06974c..1aaa471d08c56 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1141,6 +1141,7 @@
 #define   ENABLE_SMALLPL			REG_BIT(15)
 #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
 #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
+#define   GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE	REG_BIT(0)
 
 #define GEN9_HALF_SLICE_CHICKEN7		MCR_REG(0xe194)
 #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 32aa1647721ae..734b64e714647 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2542,6 +2542,23 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 				 ENABLE_SMALLPL);
 	}
 
+	if (GRAPHICS_VER(i915) >= 11) {
+		/* This is not a Wa (although referred to as
+		 * WaSetInidrectStateOverride in places), this allows
+		 * applications that reference sampler states through
+		 * the BindlessSamplerStateBaseAddress to have their
+		 * border color relative to DynamicStateBaseAddress
+		 * rather than BindlessSamplerStateBaseAddress.
+		 *
+		 * Otherwise SAMPLER_STATE border colors have to be
+		 * copied in multiple heaps (DynamicStateBaseAddress &
+		 * BindlessSamplerStateBaseAddress)
+		 */
+		wa_mcr_masked_en(wal,
+				 GEN10_SAMPLER_MODE,
+				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
+	}
+
 	if (GRAPHICS_VER(i915) == 11) {
 		/* This is not an Wa. Enable for better image quality */
 		wa_masked_en(wal,
-- 
2.34.1

Re: [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap

[Kalvala, Haridhar]

On 3/9/2023 8:56 PM, Lionel Landwerlin wrote:
> By default the indirect state sampler data (border colors) are stored
> in the same heap as the SAMPLER_STATE structure. For userspace drivers
> that can be 2 different heaps (dynamic state heap & bindless sampler
> state heap). This means that border colors have to copied in 2
> different places so that the same SAMPLER_STATE structure find the
> right data.
>
> This change is forcing the indirect state sampler data to only be in
> the dynamic state pool (more convinient for userspace drivers, they
> only have to have one copy of the border colors). This is reproducing
> the behavior of the Windows drivers.
>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Cc: stable@vger.kernel.org
> ---
>   drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  1 +
>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 +++++++++++++++++
>   2 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 08d76aa06974c..1aaa471d08c56 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1141,6 +1141,7 @@
>   #define   ENABLE_SMALLPL			REG_BIT(15)
>   #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
>   #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
> +#define   GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE	REG_BIT(0)
>   
>   #define GEN9_HALF_SLICE_CHICKEN7		MCR_REG(0xe194)
>   #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 32aa1647721ae..734b64e714647 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2542,6 +2542,23 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>   				 ENABLE_SMALLPL);
>   	}
>   
> +	if (GRAPHICS_VER(i915) >= 11) {

Hi Lionel,

Not sure should this implementation be part of "rcs_engine_wa_init" or 
"general_render_compute_wa_init".

> +		/* This is not a Wa (although referred to as
> +		 * WaSetInidrectStateOverride in places), this allows
> +		 * applications that reference sampler states through
> +		 * the BindlessSamplerStateBaseAddress to have their
> +		 * border color relative to DynamicStateBaseAddress
> +		 * rather than BindlessSamplerStateBaseAddress.
> +		 *
> +		 * Otherwise SAMPLER_STATE border colors have to be
> +		 * copied in multiple heaps (DynamicStateBaseAddress &
> +		 * BindlessSamplerStateBaseAddress)
> +		 */
> +		wa_mcr_masked_en(wal,
> +				 GEN10_SAMPLER_MODE,

  since we checking the condition for GEN11 or above, can this register 
be defined as GEN11_SAMPLER_MODE

> +				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> +	}
> +
>   	if (GRAPHICS_VER(i915) == 11) {
>   		/* This is not an Wa. Enable for better image quality */
>   		wa_masked_en(wal,

-- 
Regards,
Haridhar Kalvala

Re: [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap

[Matt Atwood]

On Tue, Mar 28, 2023 at 04:14:33PM +0530, Kalvala, Haridhar wrote:
> 
> On 3/9/2023 8:56 PM, Lionel Landwerlin wrote:
> > By default the indirect state sampler data (border colors) are stored
> > in the same heap as the SAMPLER_STATE structure. For userspace drivers
> > that can be 2 different heaps (dynamic state heap & bindless sampler
> > state heap). This means that border colors have to copied in 2
> > different places so that the same SAMPLER_STATE structure find the
> > right data.
> > 
> > This change is forcing the indirect state sampler data to only be in
> > the dynamic state pool (more convinient for userspace drivers, they
> > only have to have one copy of the border colors). This is reproducing
> > the behavior of the Windows drivers.
> > 
Bspec:46052
> > Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> > Cc: stable@vger.kernel.org
> > ---
> >   drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  1 +
> >   drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 +++++++++++++++++
> >   2 files changed, 18 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index 08d76aa06974c..1aaa471d08c56 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -1141,6 +1141,7 @@
> >   #define   ENABLE_SMALLPL			REG_BIT(15)
> >   #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
> >   #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
> > +#define   GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE	REG_BIT(0)
> >   #define GEN9_HALF_SLICE_CHICKEN7		MCR_REG(0xe194)
> >   #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 32aa1647721ae..734b64e714647 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -2542,6 +2542,23 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> >   				 ENABLE_SMALLPL);
> >   	}
> > +	if (GRAPHICS_VER(i915) >= 11) {
> 
> Hi Lionel,
> 
> Not sure should this implementation be part of "rcs_engine_wa_init" or
> "general_render_compute_wa_init".
> 
> > +		/* This is not a Wa (although referred to as
> > +		 * WaSetInidrectStateOverride in places), this allows
> > +		 * applications that reference sampler states through
> > +		 * the BindlessSamplerStateBaseAddress to have their
> > +		 * border color relative to DynamicStateBaseAddress
> > +		 * rather than BindlessSamplerStateBaseAddress.
> > +		 *
> > +		 * Otherwise SAMPLER_STATE border colors have to be
> > +		 * copied in multiple heaps (DynamicStateBaseAddress &
> > +		 * BindlessSamplerStateBaseAddress)
> > +		 */
> > +		wa_mcr_masked_en(wal,
> > +				 GEN10_SAMPLER_MODE,
> 
>  since we checking the condition for GEN11 or above, can this register be
> defined as GEN11_SAMPLER_MODE
We use the name of the first time the register was introduced, gen 10 is
fine here.
> > +				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> > +	}
> > +
> >   	if (GRAPHICS_VER(i915) == 11) {
> >   		/* This is not an Wa. Enable for better image quality */
> >   		wa_masked_en(wal,
> 
> -- 
> Regards,
> Haridhar Kalvala
>
Regards,
MattA

Re: [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap

[Lionel Landwerlin]

On 29/03/2023 01:49, Matt Atwood wrote:
> On Tue, Mar 28, 2023 at 04:14:33PM +0530, Kalvala, Haridhar wrote:
>> On 3/9/2023 8:56 PM, Lionel Landwerlin wrote:
>>> By default the indirect state sampler data (border colors) are stored
>>> in the same heap as the SAMPLER_STATE structure. For userspace drivers
>>> that can be 2 different heaps (dynamic state heap & bindless sampler
>>> state heap). This means that border colors have to copied in 2
>>> different places so that the same SAMPLER_STATE structure find the
>>> right data.
>>>
>>> This change is forcing the indirect state sampler data to only be in
>>> the dynamic state pool (more convinient for userspace drivers, they
>>> only have to have one copy of the border colors). This is reproducing
>>> the behavior of the Windows drivers.
>>>
> Bspec:46052


Sorry, missed your answer.


Should I just add the Bspec number to the commit message ?


Thanks,


-Lionel


>>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>> Cc: stable@vger.kernel.org
>>> ---
>>>    drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  1 +
>>>    drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 +++++++++++++++++
>>>    2 files changed, 18 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>> index 08d76aa06974c..1aaa471d08c56 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>> @@ -1141,6 +1141,7 @@
>>>    #define   ENABLE_SMALLPL			REG_BIT(15)
>>>    #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
>>>    #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
>>> +#define   GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE	REG_BIT(0)
>>>    #define GEN9_HALF_SLICE_CHICKEN7		MCR_REG(0xe194)
>>>    #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> index 32aa1647721ae..734b64e714647 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> @@ -2542,6 +2542,23 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>>    				 ENABLE_SMALLPL);
>>>    	}
>>> +	if (GRAPHICS_VER(i915) >= 11) {
>> Hi Lionel,
>>
>> Not sure should this implementation be part of "rcs_engine_wa_init" or
>> "general_render_compute_wa_init".
>>
>>> +		/* This is not a Wa (although referred to as
>>> +		 * WaSetInidrectStateOverride in places), this allows
>>> +		 * applications that reference sampler states through
>>> +		 * the BindlessSamplerStateBaseAddress to have their
>>> +		 * border color relative to DynamicStateBaseAddress
>>> +		 * rather than BindlessSamplerStateBaseAddress.
>>> +		 *
>>> +		 * Otherwise SAMPLER_STATE border colors have to be
>>> +		 * copied in multiple heaps (DynamicStateBaseAddress &
>>> +		 * BindlessSamplerStateBaseAddress)
>>> +		 */
>>> +		wa_mcr_masked_en(wal,
>>> +				 GEN10_SAMPLER_MODE,
>>   since we checking the condition for GEN11 or above, can this register be
>> defined as GEN11_SAMPLER_MODE
> We use the name of the first time the register was introduced, gen 10 is
> fine here.
>>> +				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>>> +	}
>>> +
>>>    	if (GRAPHICS_VER(i915) == 11) {
>>>    		/* This is not an Wa. Enable for better image quality */
>>>    		wa_masked_en(wal,
>> -- 
>> Regards,
>> Haridhar Kalvala
>>
> Regards,
> MattA

[v2] drm/i915: disable sampler indirect state in bindless heap

[Lionel Landwerlin]

By default the indirect state sampler data (border colors) are stored
in the same heap as the SAMPLER_STATE structure. For userspace drivers
that can be 2 different heaps (dynamic state heap & bindless sampler
state heap). This means that border colors have to copied in 2
different places so that the same SAMPLER_STATE structure find the
right data.

This change is forcing the indirect state sampler data to only be in
the dynamic state pool (more convinient for userspace drivers, they
only have to have one copy of the border colors). This is reproducing
the behavior of the Windows drivers.

BSpec: 46052

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 19 +++++++++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 4aecb5a7b6318..f298dc461a72f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1144,6 +1144,7 @@
 #define   ENABLE_SMALLPL			REG_BIT(15)
 #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
 #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
+#define   GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE	REG_BIT(0)
 
 #define GEN9_HALF_SLICE_CHICKEN7		MCR_REG(0xe194)
 #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e7ee24bcad893..0ce1c8c23c631 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2535,6 +2535,25 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 				 ENABLE_SMALLPL);
 	}
 
+	if (GRAPHICS_VER(i915) >= 11) {
+		/* This is not a Wa (although referred to as
+		 * WaSetInidrectStateOverride in places), this allows
+		 * applications that reference sampler states through
+		 * the BindlessSamplerStateBaseAddress to have their
+		 * border color relative to DynamicStateBaseAddress
+		 * rather than BindlessSamplerStateBaseAddress.
+		 *
+		 * Otherwise SAMPLER_STATE border colors have to be
+		 * copied in multiple heaps (DynamicStateBaseAddress &
+		 * BindlessSamplerStateBaseAddress)
+		 *
+		 * BSpec: 46052
+		 */
+		wa_mcr_masked_en(wal,
+				 GEN10_SAMPLER_MODE,
+				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
+	}
+
 	if (GRAPHICS_VER(i915) == 11) {
 		/* This is not an Wa. Enable for better image quality */
 		wa_masked_en(wal,
-- 
2.34.1

Re: [Intel-gfx] [v2] drm/i915: disable sampler indirect state in bindless heap

[Matt Atwood]

On Thu, Mar 30, 2023 at 08:47:40PM +0300, Lionel Landwerlin wrote:
> By default the indirect state sampler data (border colors) are stored
> in the same heap as the SAMPLER_STATE structure. For userspace drivers
> that can be 2 different heaps (dynamic state heap & bindless sampler
> state heap). This means that border colors have to copied in 2
> different places so that the same SAMPLER_STATE structure find the
> right data.
> 
> This change is forcing the indirect state sampler data to only be in
> the dynamic state pool (more convinient for userspace drivers, they
			       convenient 
> only have to have one copy of the border colors). This is reproducing
> the behavior of the Windows drivers.
> 
> BSpec: 46052
> 
Assuming still good CI results..
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Cc: stable@vger.kernel.org
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  1 +
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 19 +++++++++++++++++++
>  2 files changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 4aecb5a7b6318..f298dc461a72f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1144,6 +1144,7 @@
>  #define   ENABLE_SMALLPL			REG_BIT(15)
>  #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
>  #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
> +#define   GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE	REG_BIT(0)
>  
>  #define GEN9_HALF_SLICE_CHICKEN7		MCR_REG(0xe194)
>  #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e7ee24bcad893..0ce1c8c23c631 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2535,6 +2535,25 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  				 ENABLE_SMALLPL);
>  	}
>  
> +	if (GRAPHICS_VER(i915) >= 11) {
> +		/* This is not a Wa (although referred to as
> +		 * WaSetInidrectStateOverride in places), this allows
> +		 * applications that reference sampler states through
> +		 * the BindlessSamplerStateBaseAddress to have their
> +		 * border color relative to DynamicStateBaseAddress
> +		 * rather than BindlessSamplerStateBaseAddress.
> +		 *
> +		 * Otherwise SAMPLER_STATE border colors have to be
> +		 * copied in multiple heaps (DynamicStateBaseAddress &
> +		 * BindlessSamplerStateBaseAddress)
> +		 *
> +		 * BSpec: 46052
> +		 */
> +		wa_mcr_masked_en(wal,
> +				 GEN10_SAMPLER_MODE,
> +				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> +	}
> +
>  	if (GRAPHICS_VER(i915) == 11) {
>  		/* This is not an Wa. Enable for better image quality */
>  		wa_masked_en(wal,
> -- 
> 2.34.1
> 

Re: [Intel-gfx] [v2] drm/i915: disable sampler indirect state in bindless heap

[Matt Atwood]

On Thu, Mar 30, 2023 at 12:27:33PM -0700, Matt Atwood wrote:
> On Thu, Mar 30, 2023 at 08:47:40PM +0300, Lionel Landwerlin wrote:
> > By default the indirect state sampler data (border colors) are stored
> > in the same heap as the SAMPLER_STATE structure. For userspace drivers
> > that can be 2 different heaps (dynamic state heap & bindless sampler
> > state heap). This means that border colors have to copied in 2
> > different places so that the same SAMPLER_STATE structure find the
> > right data.
> > 
> > This change is forcing the indirect state sampler data to only be in
> > the dynamic state pool (more convinient for userspace drivers, they
> 			       convenient 
> > only have to have one copy of the border colors). This is reproducing
> > the behavior of the Windows drivers.
> > 
> > BSpec: 46052
> > 
> Assuming still good CI results..
> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
My mistake version 3 required. comments inline.
> > Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> > Cc: stable@vger.kernel.org
> > ---
> >  drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  1 +
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 19 +++++++++++++++++++
> >  2 files changed, 20 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index 4aecb5a7b6318..f298dc461a72f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -1144,6 +1144,7 @@
> >  #define   ENABLE_SMALLPL			REG_BIT(15)
> >  #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
> >  #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
> > +#define   GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE	REG_BIT(0)
> >  
> >  #define GEN9_HALF_SLICE_CHICKEN7		MCR_REG(0xe194)
> >  #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index e7ee24bcad893..0ce1c8c23c631 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -2535,6 +2535,25 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> >  				 ENABLE_SMALLPL);
> >  	}
> >  
This workaround belongs in general render workarounds not rcs, as per
the address space in i915_regs.h 0x2xxx.

#define RENDER_RING_BASE        0x02000


> > +	if (GRAPHICS_VER(i915) >= 11) {
> > +		/* This is not a Wa (although referred to as
> > +		 * WaSetInidrectStateOverride in places), this allows
> > +		 * applications that reference sampler states through
> > +		 * the BindlessSamplerStateBaseAddress to have their
> > +		 * border color relative to DynamicStateBaseAddress
> > +		 * rather than BindlessSamplerStateBaseAddress.
> > +		 *
> > +		 * Otherwise SAMPLER_STATE border colors have to be
> > +		 * copied in multiple heaps (DynamicStateBaseAddress &
> > +		 * BindlessSamplerStateBaseAddress)
> > +		 *
> > +		 * BSpec: 46052
> > +		 */
> > +		wa_mcr_masked_en(wal,
> > +				 GEN10_SAMPLER_MODE,
> > +				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> > +	}
> > +
> >  	if (GRAPHICS_VER(i915) == 11) {
> >  		/* This is not an Wa. Enable for better image quality */
> >  		wa_masked_en(wal,
> > -- 
> > 2.34.1
> > 
MattA

[v3] drm/i915: disable sampler indirect state in bindless heap

[Lionel Landwerlin]

By default the indirect state sampler data (border colors) are stored
in the same heap as the SAMPLER_STATE structure. For userspace drivers
that can be 2 different heaps (dynamic state heap & bindless sampler
state heap). This means that border colors have to copied in 2
different places so that the same SAMPLER_STATE structure find the
right data.

This change is forcing the indirect state sampler data to only be in
the dynamic state pool (more convinient for userspace drivers, they
only have to have one copy of the border colors). This is reproducing
the behavior of the Windows drivers.

BSpec: 46052

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 19 +++++++++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 4aecb5a7b6318..f298dc461a72f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1144,6 +1144,7 @@
 #define   ENABLE_SMALLPL			REG_BIT(15)
 #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
 #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
+#define   GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE	REG_BIT(0)
 
 #define GEN9_HALF_SLICE_CHICKEN7		MCR_REG(0xe194)
 #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e7ee24bcad893..5bfc864d5fcc0 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2971,6 +2971,25 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 
 	add_render_compute_tuning_settings(i915, wal);
 
+	if (GRAPHICS_VER(i915) >= 11) {
+		/* This is not a Wa (although referred to as
+		 * WaSetInidrectStateOverride in places), this allows
+		 * applications that reference sampler states through
+		 * the BindlessSamplerStateBaseAddress to have their
+		 * border color relative to DynamicStateBaseAddress
+		 * rather than BindlessSamplerStateBaseAddress.
+		 *
+		 * Otherwise SAMPLER_STATE border colors have to be
+		 * copied in multiple heaps (DynamicStateBaseAddress &
+		 * BindlessSamplerStateBaseAddress)
+		 *
+		 * BSpec: 46052
+		 */
+		wa_mcr_masked_en(wal,
+				 GEN10_SAMPLER_MODE,
+				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
+	}
+
 	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
 	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
 	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
-- 
2.34.1

Re: [Intel-gfx] [v2] drm/i915: disable sampler indirect state in bindless heap

[Lionel Landwerlin]

On 30/03/2023 22:38, Matt Atwood wrote:
> On Thu, Mar 30, 2023 at 12:27:33PM -0700, Matt Atwood wrote:
>> On Thu, Mar 30, 2023 at 08:47:40PM +0300, Lionel Landwerlin wrote:
>>> By default the indirect state sampler data (border colors) are stored
>>> in the same heap as the SAMPLER_STATE structure. For userspace drivers
>>> that can be 2 different heaps (dynamic state heap & bindless sampler
>>> state heap). This means that border colors have to copied in 2
>>> different places so that the same SAMPLER_STATE structure find the
>>> right data.
>>>
>>> This change is forcing the indirect state sampler data to only be in
>>> the dynamic state pool (more convinient for userspace drivers, they
>> 			       convenient
>>> only have to have one copy of the border colors). This is reproducing
>>> the behavior of the Windows drivers.
>>>
>>> BSpec: 46052
>>>
>> Assuming still good CI results..
>> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> My mistake version 3 required. comments inline.
>>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>> Cc: stable@vger.kernel.org
>>> ---
>>>   drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  1 +
>>>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 19 +++++++++++++++++++
>>>   2 files changed, 20 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>> index 4aecb5a7b6318..f298dc461a72f 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>> @@ -1144,6 +1144,7 @@
>>>   #define   ENABLE_SMALLPL			REG_BIT(15)
>>>   #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
>>>   #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
>>> +#define   GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE	REG_BIT(0)
>>>   
>>>   #define GEN9_HALF_SLICE_CHICKEN7		MCR_REG(0xe194)
>>>   #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> index e7ee24bcad893..0ce1c8c23c631 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> @@ -2535,6 +2535,25 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>>   				 ENABLE_SMALLPL);
>>>   	}
>>>   
> This workaround belongs in general render workarounds not rcs, as per
> the address space in i915_regs.h 0x2xxx.
>
> #define RENDER_RING_BASE        0x02000


Thanks makes sense.


-Lionel


>
>
>>> +	if (GRAPHICS_VER(i915) >= 11) {
>>> +		/* This is not a Wa (although referred to as
>>> +		 * WaSetInidrectStateOverride in places), this allows
>>> +		 * applications that reference sampler states through
>>> +		 * the BindlessSamplerStateBaseAddress to have their
>>> +		 * border color relative to DynamicStateBaseAddress
>>> +		 * rather than BindlessSamplerStateBaseAddress.
>>> +		 *
>>> +		 * Otherwise SAMPLER_STATE border colors have to be
>>> +		 * copied in multiple heaps (DynamicStateBaseAddress &
>>> +		 * BindlessSamplerStateBaseAddress)
>>> +		 *
>>> +		 * BSpec: 46052
>>> +		 */
>>> +		wa_mcr_masked_en(wal,
>>> +				 GEN10_SAMPLER_MODE,
>>> +				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>>> +	}
>>> +
>>>   	if (GRAPHICS_VER(i915) == 11) {
>>>   		/* This is not an Wa. Enable for better image quality */
>>>   		wa_masked_en(wal,
>>> -- 
>>> 2.34.1
>>>
> MattA

Re: [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap

[Kalvala, Haridhar]

On 3/30/2023 10:49 PM, Lionel Landwerlin wrote:
> On 29/03/2023 01:49, Matt Atwood wrote:
>> On Tue, Mar 28, 2023 at 04:14:33PM +0530, Kalvala, Haridhar wrote:
>>> On 3/9/2023 8:56 PM, Lionel Landwerlin wrote:
>>>> By default the indirect state sampler data (border colors) are stored
>>>> in the same heap as the SAMPLER_STATE structure. For userspace drivers
>>>> that can be 2 different heaps (dynamic state heap & bindless sampler
>>>> state heap). This means that border colors have to copied in 2
>>>> different places so that the same SAMPLER_STATE structure find the
>>>> right data.
>>>>
>>>> This change is forcing the indirect state sampler data to only be in
>>>> the dynamic state pool (more convinient for userspace drivers, they
>>>> only have to have one copy of the border colors). This is reproducing
>>>> the behavior of the Windows drivers.
>>>>
>> Bspec:46052
>
>
> Sorry, missed your answer.
>
>
> Should I just add the Bspec number to the commit message ?
>
>
> Thanks,
>
>
> -Lionel
>
>
>>>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>>> Cc: stable@vger.kernel.org
>>>> ---
>>>>    drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  1 +
>>>>    drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 +++++++++++++++++
>>>>    2 files changed, 18 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
>>>> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>> index 08d76aa06974c..1aaa471d08c56 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>> @@ -1141,6 +1141,7 @@
>>>>    #define   ENABLE_SMALLPL            REG_BIT(15)
>>>>    #define   SC_DISABLE_POWER_OPTIMIZATION_EBB    REG_BIT(9)
>>>>    #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG    REG_BIT(5)
>>>> +#define   GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
>>>>    #define GEN9_HALF_SLICE_CHICKEN7        MCR_REG(0xe194)
>>>>    #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
>>>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>> index 32aa1647721ae..734b64e714647 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>> @@ -2542,6 +2542,23 @@ rcs_engine_wa_init(struct intel_engine_cs 
>>>> *engine, struct i915_wa_list *wal)
>>>>                     ENABLE_SMALLPL);
>>>>        }
>>>> +    if (GRAPHICS_VER(i915) >= 11) {
>>> Hi Lionel,
>>>
>>> Not sure should this implementation be part of "rcs_engine_wa_init" or
>>> "general_render_compute_wa_init" ?

>>>> +        /* This is not a Wa (although referred to as
>>>> +         * WaSetInidrectStateOverride in places), this allows
>>>> +         * applications that reference sampler states through
>>>> +         * the BindlessSamplerStateBaseAddress to have their
>>>> +         * border color relative to DynamicStateBaseAddress
>>>> +         * rather than BindlessSamplerStateBaseAddress.
>>>> +         *
>>>> +         * Otherwise SAMPLER_STATE border colors have to be
>>>> +         * copied in multiple heaps (DynamicStateBaseAddress &
>>>> +         * BindlessSamplerStateBaseAddress)
>>>> +         */
>>>> +        wa_mcr_masked_en(wal,
>>>> +                 GEN10_SAMPLER_MODE,
>>>   since we checking the condition for GEN11 or above, can this 
>>> register be
>>> defined as GEN11_SAMPLER_MODE
>> We use the name of the first time the register was introduced, gen 10 is
>> fine here.
ok
>>>> + GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>>>> +    }
>>>> +
>>>>        if (GRAPHICS_VER(i915) == 11) {
>>>>            /* This is not an Wa. Enable for better image quality */
>>>>            wa_masked_en(wal,
>>> -- 
>>> Regards,
>>> Haridhar Kalvala
>>>
>> Regards,
>> MattA
>
>
-- 
Regards,
Haridhar Kalvala

Re: [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap

[Kalvala, Haridhar]

On 3/31/2023 12:35 PM, Kalvala, Haridhar wrote:
>
> On 3/30/2023 10:49 PM, Lionel Landwerlin wrote:
>> On 29/03/2023 01:49, Matt Atwood wrote:
>>> On Tue, Mar 28, 2023 at 04:14:33PM +0530, Kalvala, Haridhar wrote:
>>>> On 3/9/2023 8:56 PM, Lionel Landwerlin wrote:
>>>>> By default the indirect state sampler data (border colors) are stored
>>>>> in the same heap as the SAMPLER_STATE structure. For userspace 
>>>>> drivers
>>>>> that can be 2 different heaps (dynamic state heap & bindless sampler
>>>>> state heap). This means that border colors have to copied in 2
>>>>> different places so that the same SAMPLER_STATE structure find the
>>>>> right data.
>>>>>
>>>>> This change is forcing the indirect state sampler data to only be in
>>>>> the dynamic state pool (more convinient for userspace drivers, they
>>>>> only have to have one copy of the border colors). This is reproducing
>>>>> the behavior of the Windows drivers.
>>>>>
>>> Bspec:46052
>>
>>
>> Sorry, missed your answer.
>>
>>
>> Should I just add the Bspec number to the commit message ?
>>
>>
>> Thanks,
>>
>>
>> -Lionel
>>
>>
>>>>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>>>> Cc: stable@vger.kernel.org
>>>>> ---
>>>>>    drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  1 +
>>>>>    drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 +++++++++++++++++
>>>>>    2 files changed, 18 insertions(+)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
>>>>> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>>> index 08d76aa06974c..1aaa471d08c56 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>>> @@ -1141,6 +1141,7 @@
>>>>>    #define   ENABLE_SMALLPL            REG_BIT(15)
>>>>>    #define   SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
>>>>>    #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
>>>>> +#define   GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
>>>>>    #define GEN9_HALF_SLICE_CHICKEN7        MCR_REG(0xe194)
>>>>>    #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
>>>>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>> index 32aa1647721ae..734b64e714647 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>> @@ -2542,6 +2542,23 @@ rcs_engine_wa_init(struct intel_engine_cs 
>>>>> *engine, struct i915_wa_list *wal)
>>>>>                     ENABLE_SMALLPL);
>>>>>        }
>>>>> +    if (GRAPHICS_VER(i915) >= 11) {
>>>> Hi Lionel,
>>>>
>>>> Not sure should this implementation be part of "rcs_engine_wa_init" or
>>>> "general_render_compute_wa_init" ?


I checked with Matt Ropper as well, looks like this implementation 
should be part of "general_render_compute_wa_init".

>
>>>>> +        /* This is not a Wa (although referred to as
>>>>> +         * WaSetInidrectStateOverride in places), this allows
>>>>> +         * applications that reference sampler states through
>>>>> +         * the BindlessSamplerStateBaseAddress to have their
>>>>> +         * border color relative to DynamicStateBaseAddress
>>>>> +         * rather than BindlessSamplerStateBaseAddress.
>>>>> +         *
>>>>> +         * Otherwise SAMPLER_STATE border colors have to be
>>>>> +         * copied in multiple heaps (DynamicStateBaseAddress &
>>>>> +         * BindlessSamplerStateBaseAddress)
>>>>> +         */
>>>>> +        wa_mcr_masked_en(wal,
>>>>> +                 GEN10_SAMPLER_MODE,
>>>>   since we checking the condition for GEN11 or above, can this 
>>>> register be
>>>> defined as GEN11_SAMPLER_MODE
>>> We use the name of the first time the register was introduced, gen 
>>> 10 is
>>> fine here.
> ok
>>>>> + GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>>>>> +    }
>>>>> +
>>>>>        if (GRAPHICS_VER(i915) == 11) {
>>>>>            /* This is not an Wa. Enable for better image quality */
>>>>>            wa_masked_en(wal,
>>>> -- 
>>>> Regards,
>>>> Haridhar Kalvala
>>>>
>>> Regards,
>>> MattA
>>
>>
-- 
Regards,
Haridhar Kalvala

Re: [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap

[Lionel Landwerlin]

On 03/04/2023 21:22, Kalvala, Haridhar wrote:
>
> On 3/31/2023 12:35 PM, Kalvala, Haridhar wrote:
>>
>> On 3/30/2023 10:49 PM, Lionel Landwerlin wrote:
>>> On 29/03/2023 01:49, Matt Atwood wrote:
>>>> On Tue, Mar 28, 2023 at 04:14:33PM +0530, Kalvala, Haridhar wrote:
>>>>> On 3/9/2023 8:56 PM, Lionel Landwerlin wrote:
>>>>>> By default the indirect state sampler data (border colors) are 
>>>>>> stored
>>>>>> in the same heap as the SAMPLER_STATE structure. For userspace 
>>>>>> drivers
>>>>>> that can be 2 different heaps (dynamic state heap & bindless sampler
>>>>>> state heap). This means that border colors have to copied in 2
>>>>>> different places so that the same SAMPLER_STATE structure find the
>>>>>> right data.
>>>>>>
>>>>>> This change is forcing the indirect state sampler data to only be in
>>>>>> the dynamic state pool (more convinient for userspace drivers, they
>>>>>> only have to have one copy of the border colors). This is 
>>>>>> reproducing
>>>>>> the behavior of the Windows drivers.
>>>>>>
>>>> Bspec:46052
>>>
>>>
>>> Sorry, missed your answer.
>>>
>>>
>>> Should I just add the Bspec number to the commit message ?
>>>
>>>
>>> Thanks,
>>>
>>>
>>> -Lionel
>>>
>>>
>>>>>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>>>>> Cc: stable@vger.kernel.org
>>>>>> ---
>>>>>>    drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  1 +
>>>>>>    drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 
>>>>>> +++++++++++++++++
>>>>>>    2 files changed, 18 insertions(+)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
>>>>>> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>>>> index 08d76aa06974c..1aaa471d08c56 100644
>>>>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>>>> @@ -1141,6 +1141,7 @@
>>>>>>    #define   ENABLE_SMALLPL            REG_BIT(15)
>>>>>>    #define   SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
>>>>>>    #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
>>>>>> +#define   GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
>>>>>>    #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
>>>>>>    #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
>>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
>>>>>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>>> index 32aa1647721ae..734b64e714647 100644
>>>>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>>> @@ -2542,6 +2542,23 @@ rcs_engine_wa_init(struct intel_engine_cs 
>>>>>> *engine, struct i915_wa_list *wal)
>>>>>>                     ENABLE_SMALLPL);
>>>>>>        }
>>>>>> +    if (GRAPHICS_VER(i915) >= 11) {
>>>>> Hi Lionel,
>>>>>
>>>>> Not sure should this implementation be part of 
>>>>> "rcs_engine_wa_init" or
>>>>> "general_render_compute_wa_init" ?
>
>
> I checked with Matt Ropper as well, looks like this implementation 
> should be part of "general_render_compute_wa_init".


I did send a v3 of the patch last Thursday to address this.

Let me know if that's good.


Thanks,


-Lionel


>
>>
>>>>>> +        /* This is not a Wa (although referred to as
>>>>>> +         * WaSetInidrectStateOverride in places), this allows
>>>>>> +         * applications that reference sampler states through
>>>>>> +         * the BindlessSamplerStateBaseAddress to have their
>>>>>> +         * border color relative to DynamicStateBaseAddress
>>>>>> +         * rather than BindlessSamplerStateBaseAddress.
>>>>>> +         *
>>>>>> +         * Otherwise SAMPLER_STATE border colors have to be
>>>>>> +         * copied in multiple heaps (DynamicStateBaseAddress &
>>>>>> +         * BindlessSamplerStateBaseAddress)
>>>>>> +         */
>>>>>> +        wa_mcr_masked_en(wal,
>>>>>> +                 GEN10_SAMPLER_MODE,
>>>>>   since we checking the condition for GEN11 or above, can this 
>>>>> register be
>>>>> defined as GEN11_SAMPLER_MODE
>>>> We use the name of the first time the register was introduced, gen 
>>>> 10 is
>>>> fine here.
>> ok
>>>>>> + GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>>>>>> +    }
>>>>>> +
>>>>>>        if (GRAPHICS_VER(i915) == 11) {
>>>>>>            /* This is not an Wa. Enable for better image quality */
>>>>>>            wa_masked_en(wal,
>>>>> -- 
>>>>> Regards,
>>>>> Haridhar Kalvala
>>>>>
>>>> Regards,
>>>> MattA
>>>
>>>

Re: [Intel-gfx] [v3] drm/i915: disable sampler indirect state in bindless heap

[Matt Atwood]

On Thu, Mar 30, 2023 at 11:42:28PM +0300, Lionel Landwerlin wrote:
> By default the indirect state sampler data (border colors) are stored
> in the same heap as the SAMPLER_STATE structure. For userspace drivers
> that can be 2 different heaps (dynamic state heap & bindless sampler
> state heap). This means that border colors have to copied in 2
> different places so that the same SAMPLER_STATE structure find the
> right data.
> 
> This change is forcing the indirect state sampler data to only be in
> the dynamic state pool (more convinient for userspace drivers, they
> only have to have one copy of the border colors). This is reproducing
> the behavior of the Windows drivers.
> 
> BSpec: 46052
> 
ci failed to build, respin and submit
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Cc: stable@vger.kernel.org
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  1 +
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 19 +++++++++++++++++++
>  2 files changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 4aecb5a7b6318..f298dc461a72f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1144,6 +1144,7 @@
>  #define   ENABLE_SMALLPL			REG_BIT(15)
>  #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
>  #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
> +#define   GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE	REG_BIT(0)
>  
>  #define GEN9_HALF_SLICE_CHICKEN7		MCR_REG(0xe194)
>  #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e7ee24bcad893..5bfc864d5fcc0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2971,6 +2971,25 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>  
>  	add_render_compute_tuning_settings(i915, wal);
>  
> +	if (GRAPHICS_VER(i915) >= 11) {
> +		/* This is not a Wa (although referred to as
> +		 * WaSetInidrectStateOverride in places), this allows
> +		 * applications that reference sampler states through
> +		 * the BindlessSamplerStateBaseAddress to have their
> +		 * border color relative to DynamicStateBaseAddress
> +		 * rather than BindlessSamplerStateBaseAddress.
> +		 *
> +		 * Otherwise SAMPLER_STATE border colors have to be
> +		 * copied in multiple heaps (DynamicStateBaseAddress &
> +		 * BindlessSamplerStateBaseAddress)
> +		 *
> +		 * BSpec: 46052
> +		 */
> +		wa_mcr_masked_en(wal,
> +				 GEN10_SAMPLER_MODE,
> +				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> +	}
> +
>  	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>  	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>  	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> -- 
> 2.34.1
>