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* [PATCH] drm/mgag200: Fix PLL setup for g200wb and g200ew
@ 2022-03-08 17:11 Jocelyn Falempe
  2022-03-08 17:31 ` Greg KH
  2022-03-08 17:43 ` [PATCH v2] " Jocelyn Falempe
  0 siblings, 2 replies; 5+ messages in thread
From: Jocelyn Falempe @ 2022-03-08 17:11 UTC (permalink / raw)
  To: dri-devel; +Cc: michel, lyude, tzimmermann, Jocelyn Falempe, stable

commit f86c3ed55920ca1d874758cc290890902a6cffc4 ("drm/mgag200: Split PLL
setup into compute and update functions") introduced a regression for
g200wb and g200ew.
The PLLs are not set up properly, and VGA screen stays
black, or displays "out of range" message.

MGA1064_WB_PIX_PLLC_N/M/P was mistakenly replaced with
MGA1064_PIX_PLLC_N/M/P which have different addresses.

Patch tested on a Dell T310 with g200wb

Fixes: f86c3ed55920ca1d874758cc290890902a6cffc4
Cc: stable@vger.kernel.org
Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
---
 drivers/gpu/drm/mgag200/mgag200_pll.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/mgag200/mgag200_pll.c b/drivers/gpu/drm/mgag200/mgag200_pll.c
index e9ae22b4f813..52be08b744ad 100644
--- a/drivers/gpu/drm/mgag200/mgag200_pll.c
+++ b/drivers/gpu/drm/mgag200/mgag200_pll.c
@@ -404,9 +404,9 @@ mgag200_pixpll_update_g200wb(struct mgag200_pll *pixpll, const struct mgag200_pl
 		udelay(50);
 
 		/* program pixel pll register */
-		WREG_DAC(MGA1064_PIX_PLLC_N, xpixpllcn);
-		WREG_DAC(MGA1064_PIX_PLLC_M, xpixpllcm);
-		WREG_DAC(MGA1064_PIX_PLLC_P, xpixpllcp);
+		WREG_DAC(MGA1064_WB_PIX_PLLC_N, xpixpllcn);
+		WREG_DAC(MGA1064_WB_PIX_PLLC_M, xpixpllcm);
+		WREG_DAC(MGA1064_WB_PIX_PLLC_P, xpixpllcp);
 
 		udelay(50);
 
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH] drm/mgag200: Fix PLL setup for g200wb and g200ew
  2022-03-08 17:11 [PATCH] drm/mgag200: Fix PLL setup for g200wb and g200ew Jocelyn Falempe
@ 2022-03-08 17:31 ` Greg KH
  2022-03-08 17:36   ` Jocelyn Falempe
  2022-03-08 17:43 ` [PATCH v2] " Jocelyn Falempe
  1 sibling, 1 reply; 5+ messages in thread
From: Greg KH @ 2022-03-08 17:31 UTC (permalink / raw)
  To: Jocelyn Falempe; +Cc: dri-devel, michel, lyude, tzimmermann, stable

On Tue, Mar 08, 2022 at 06:11:11PM +0100, Jocelyn Falempe wrote:
> commit f86c3ed55920ca1d874758cc290890902a6cffc4 ("drm/mgag200: Split PLL
> setup into compute and update functions") introduced a regression for
> g200wb and g200ew.

No need for all those digits in the sha1, see below:

> The PLLs are not set up properly, and VGA screen stays
> black, or displays "out of range" message.
> 
> MGA1064_WB_PIX_PLLC_N/M/P was mistakenly replaced with
> MGA1064_PIX_PLLC_N/M/P which have different addresses.
> 
> Patch tested on a Dell T310 with g200wb
> 
> Fixes: f86c3ed55920ca1d874758cc290890902a6cffc4

As per the documentation that line should read:

Fixes: f86c3ed55920 ("drm/mgag200: Split PLL setup into compute and update functions")

thanks,

greg k-h

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH] drm/mgag200: Fix PLL setup for g200wb and g200ew
  2022-03-08 17:31 ` Greg KH
@ 2022-03-08 17:36   ` Jocelyn Falempe
  0 siblings, 0 replies; 5+ messages in thread
From: Jocelyn Falempe @ 2022-03-08 17:36 UTC (permalink / raw)
  To: Greg KH; +Cc: stable, michel, tzimmermann, dri-devel

On 08/03/2022 18:31, Greg KH wrote:
> On Tue, Mar 08, 2022 at 06:11:11PM +0100, Jocelyn Falempe wrote:
>> commit f86c3ed55920ca1d874758cc290890902a6cffc4 ("drm/mgag200: Split PLL
>> setup into compute and update functions") introduced a regression for
>> g200wb and g200ew.
> 
> No need for all those digits in the sha1, see below:
> 
>> The PLLs are not set up properly, and VGA screen stays
>> black, or displays "out of range" message.
>>
>> MGA1064_WB_PIX_PLLC_N/M/P was mistakenly replaced with
>> MGA1064_PIX_PLLC_N/M/P which have different addresses.
>>
>> Patch tested on a Dell T310 with g200wb
>>
>> Fixes: f86c3ed55920ca1d874758cc290890902a6cffc4
> 
> As per the documentation that line should read:
> 
> Fixes: f86c3ed55920 ("drm/mgag200: Split PLL setup into compute and update functions")

Sorry, I will send a v2 shortly.
> 
> thanks,
> 
> greg k-h
> 


^ permalink raw reply	[flat|nested] 5+ messages in thread
* [PATCH v2] drm/mgag200: Fix PLL setup for g200wb and g200ew
  2022-03-08 17:11 [PATCH] drm/mgag200: Fix PLL setup for g200wb and g200ew Jocelyn Falempe
  2022-03-08 17:31 ` Greg KH
@ 2022-03-08 17:43 ` Jocelyn Falempe
  2022-03-13 19:39   ` Thomas Zimmermann
  1 sibling, 1 reply; 5+ messages in thread
From: Jocelyn Falempe @ 2022-03-08 17:43 UTC (permalink / raw)
  To: dri-devel; +Cc: michel, lyude, tzimmermann, Jocelyn Falempe, stable

commit f86c3ed55920 ("drm/mgag200: Split PLL setup into compute and
 update functions") introduced a regression for g200wb and g200ew.
The PLLs are not set up properly, and VGA screen stays
black, or displays "out of range" message.

MGA1064_WB_PIX_PLLC_N/M/P was mistakenly replaced with
MGA1064_PIX_PLLC_N/M/P which have different addresses.

Patch tested on a Dell T310 with g200wb

Fixes: f86c3ed55920 ("drm/mgag200: Split PLL setup into compute and update functions")
Cc: stable@vger.kernel.org
Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
---
 drivers/gpu/drm/mgag200/mgag200_pll.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/mgag200/mgag200_pll.c b/drivers/gpu/drm/mgag200/mgag200_pll.c
index e9ae22b4f813..52be08b744ad 100644
--- a/drivers/gpu/drm/mgag200/mgag200_pll.c
+++ b/drivers/gpu/drm/mgag200/mgag200_pll.c
@@ -404,9 +404,9 @@ mgag200_pixpll_update_g200wb(struct mgag200_pll *pixpll, const struct mgag200_pl
 		udelay(50);
 
 		/* program pixel pll register */
-		WREG_DAC(MGA1064_PIX_PLLC_N, xpixpllcn);
-		WREG_DAC(MGA1064_PIX_PLLC_M, xpixpllcm);
-		WREG_DAC(MGA1064_PIX_PLLC_P, xpixpllcp);
+		WREG_DAC(MGA1064_WB_PIX_PLLC_N, xpixpllcn);
+		WREG_DAC(MGA1064_WB_PIX_PLLC_M, xpixpllcm);
+		WREG_DAC(MGA1064_WB_PIX_PLLC_P, xpixpllcp);
 
 		udelay(50);
 
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH v2] drm/mgag200: Fix PLL setup for g200wb and g200ew
  2022-03-08 17:43 ` [PATCH v2] " Jocelyn Falempe
@ 2022-03-13 19:39   ` Thomas Zimmermann
  0 siblings, 0 replies; 5+ messages in thread
From: Thomas Zimmermann @ 2022-03-13 19:39 UTC (permalink / raw)
  To: Jocelyn Falempe, dri-devel; +Cc: stable, michel


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Hi

Am 08.03.22 um 18:43 schrieb Jocelyn Falempe:
> commit f86c3ed55920 ("drm/mgag200: Split PLL setup into compute and
>   update functions") introduced a regression for g200wb and g200ew.
> The PLLs are not set up properly, and VGA screen stays
> black, or displays "out of range" message.
> 
> MGA1064_WB_PIX_PLLC_N/M/P was mistakenly replaced with
> MGA1064_PIX_PLLC_N/M/P which have different addresses.
> 
> Patch tested on a Dell T310 with g200wb
> 
> Fixes: f86c3ed55920 ("drm/mgag200: Split PLL setup into compute and update functions")
> Cc: stable@vger.kernel.org
> Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>

Thank you so much. I've added the patch to drm-misc-fixes. One small 
nit: next time, please include a little change log that says what each 
version of the patch changes; even if it's only the style of the commit 
message.

Best regards
Thomas

> ---
>   drivers/gpu/drm/mgag200/mgag200_pll.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mgag200/mgag200_pll.c b/drivers/gpu/drm/mgag200/mgag200_pll.c
> index e9ae22b4f813..52be08b744ad 100644
> --- a/drivers/gpu/drm/mgag200/mgag200_pll.c
> +++ b/drivers/gpu/drm/mgag200/mgag200_pll.c
> @@ -404,9 +404,9 @@ mgag200_pixpll_update_g200wb(struct mgag200_pll *pixpll, const struct mgag200_pl
>   		udelay(50);
>   
>   		/* program pixel pll register */
> -		WREG_DAC(MGA1064_PIX_PLLC_N, xpixpllcn);
> -		WREG_DAC(MGA1064_PIX_PLLC_M, xpixpllcm);
> -		WREG_DAC(MGA1064_PIX_PLLC_P, xpixpllcp);
> +		WREG_DAC(MGA1064_WB_PIX_PLLC_N, xpixpllcn);
> +		WREG_DAC(MGA1064_WB_PIX_PLLC_M, xpixpllcm);
> +		WREG_DAC(MGA1064_WB_PIX_PLLC_P, xpixpllcp);
>   
>   		udelay(50);
>   

-- 
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Ivo Totev

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^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-03-13 19:39 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-08 17:11 [PATCH] drm/mgag200: Fix PLL setup for g200wb and g200ew Jocelyn Falempe
2022-03-08 17:31 ` Greg KH
2022-03-08 17:36   ` Jocelyn Falempe
2022-03-08 17:43 ` [PATCH v2] " Jocelyn Falempe
2022-03-13 19:39   ` Thomas Zimmermann

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