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* [PATCH] xtensa: add missing isync to the cpu_reset TLB code
@ 2019-08-12 22:08 Max Filippov
       [not found] ` <20190813124815.D64A520840@mail.kernel.org>
  0 siblings, 1 reply; 2+ messages in thread
From: Max Filippov @ 2019-08-12 22:08 UTC (permalink / raw)
  To: linux-xtensa; +Cc: Chris Zankel, Max Filippov, stable

ITLB entry modifications must be followed by the isync instruction
before the new entries are possibly used. cpu_reset lacks one isync
between ITLB way 6 initialization and jump to the identity mapping.
Add missing isync to xtensa cpu_reset.

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
 arch/xtensa/kernel/setup.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c
index 5cb8a62e091c..7c3106093c75 100644
--- a/arch/xtensa/kernel/setup.c
+++ b/arch/xtensa/kernel/setup.c
@@ -511,6 +511,7 @@ void cpu_reset(void)
 				      "add	%2, %2, %7\n\t"
 				      "addi	%0, %0, -1\n\t"
 				      "bnez	%0, 1b\n\t"
+				      "isync\n\t"
 				      /* Jump to identity mapping */
 				      "jx	%3\n"
 				      "2:\n\t"
-- 
2.11.0


^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH] xtensa: add missing isync to the cpu_reset TLB code
       [not found] ` <20190813124815.D64A520840@mail.kernel.org>
@ 2019-08-13 14:53   ` Max Filippov
  0 siblings, 0 replies; 2+ messages in thread
From: Max Filippov @ 2019-08-13 14:53 UTC (permalink / raw)
  To: Sasha Levin
  Cc: open list:TENSILICA XTENSA PORT (xtensa), Chris Zankel, stable

Hi Sasha,

On Tue, Aug 13, 2019 at 5:48 AM Sasha Levin <sashal@kernel.org> wrote:
> This commit has been processed because it contains a -stable tag.
> The stable tag indicates that it's relevant for the following trees: all
>
> The bot has tested the following trees: v5.2.8, v4.19.66, v4.14.138, v4.9.189, v4.4.189.
>
> v5.2.8: Build OK!
> v4.19.66: Build OK!
> v4.14.138: Build OK!
> v4.4.189: Failed to apply! Possible dependencies:
>     4f2056873ff0 ("xtensa: extract common CPU reset code into separate function")
>     bf15f86b343e ("xtensa: initialize MMU before jumping to reset vector")
>     ea951c34ea95 ("xtensa: fix icountlevel setting in cpu_reset")
>
>
> NOTE: The patch will not be queued to stable trees until it is upstream.
>
> How should we proceed with this patch?

It should be applied to stable trees for linux versions 4.10 and newer.

-- 
Thanks.
-- Max

^ permalink raw reply	[flat|nested] 2+ messages in thread

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2019-08-12 22:08 [PATCH] xtensa: add missing isync to the cpu_reset TLB code Max Filippov
     [not found] ` <20190813124815.D64A520840@mail.kernel.org>
2019-08-13 14:53   ` Max Filippov

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