* [PATCH 0/4] phy-mode cleanup
@ 2021-09-18 12:32 Vladimir Oltean
2021-09-18 12:32 ` [PATCH 1/4] net: replace the "xfi" phy-mode with "10gbase-r" Vladimir Oltean
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Vladimir Oltean @ 2021-09-18 12:32 UTC (permalink / raw)
To: u-boot
Cc: Joe Hershberger, Ramon Fried, Priyanka Jain, Madalin Bucur,
Ioana Ciornei, Camelia Groza, Scott Wood, Pali Rohár,
Marcin Wojtas, Stefan Chulski
Michael Walle did an excellent job in starting the process of bringing
U-Boot and Linux device tree bindings in sync for the NXP LS1028A:
https://patchwork.ozlabs.org/project/uboot/cover/20210902164558.1920849-1-michael@walle.cc/
but there still are some hairy issues which need to be addressed head
on, and which Michael said he'd rather leave for NXP to do, so here we
are /shrug/
NXP LS1028A has 2 Ethernet controllers:
drivers/net/fsl_enetc.c for the endpoint ports and DSA master
drivers/net/mscc_eswitch/felix_switch.c for the switch ports
but in fact, the MAC-side Physical Coding Sublayer (PCS) device used for
translating the MAC layer data into a serial bit stream is the same kind
between the enetc and the switch, as well as the same kind as the PCS
used in the other NXP SoCs (those based on DPAA1 and those based on DPAA2).
So most of the conclusions we draw about the LS1028A PCS apply equally
to the other NXP SoCs from the family.
There are 3 general directions in this patch series:
- the "sgmii-2500" idea was rejected in Linux due to the inability to
explain what it is. Linux has standardized on "2500base-x" as a way to
describe both fiber ports and MAC-to-PHY links. Convert the NXP
devices to use the phy-mode accepted in Linux.
- the "xfi" phy-mode was rejected in Linux because it is an electrical
standard covering more than a single SERDES protocol. For Ethernet
things were standardized as "10gbase-r" which describes the 64b/66b
coding scheme used there (the "R" in 10GBase-R).
- the "xgmii" phy-mode is pretty much bogus, there are no NXP devices
with this pinout. This pretty much stems from the idea that the device
tree should describe an internal set of wires between the MAC and the
PCS (the much speculated semantic difference between "phy-mode" and
"phy-connection-type"), which it should not. Even though I'm pretty
sure that no NXP devices have an external pinout of XGMII, I have only
replaced this usage in the LS1028A networking drivers, because I am
not completely sure of all the implications my changes would have in
the DPAA1 and DPAA2 drivers.
Vladimir Oltean (4):
net: replace the "xfi" phy-mode with "10gbase-r"
net: freescale: replace usage of phy-mode = "sgmii-2500" with
"2500base-x"
net: enetc: remove support for "xgmii" phy-mode
net: dsa: felix: remove "xgmii" phy-mode
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +-
.../cpu/armv8/fsl-layerscape/doc/README.soc | 8 +++----
.../cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 2 +-
.../dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi | 2 +-
.../dts/fsl-ls1028a-qds-7777-sch-30841.dtsi | 8 +++----
.../dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi | 4 ++--
.../dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi | 2 +-
.../dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi | 2 +-
arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi | 4 ++--
arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi | 4 ++--
arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi | 16 +++++++-------
arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 16 +++++++-------
arch/arm/dts/fsl-sch-30841.dtsi | 2 +-
arch/arm/dts/fsl-sch-30842.dtsi | 2 +-
board/Marvell/octeon_ebb7304/board.c | 6 ++---
board/freescale/ls1012aqds/eth.c | 4 ++--
board/freescale/ls1012aqds/ls1012aqds.c | 4 ++--
board/freescale/ls1012aqds/ls1012aqds_pfe.h | 2 +-
board/freescale/ls1012ardb/eth.c | 4 ++--
board/freescale/ls1043aqds/README | 2 +-
board/freescale/ls1043aqds/eth.c | 12 +++++-----
board/freescale/ls1043ardb/README | 2 +-
board/freescale/ls1043ardb/eth.c | 2 +-
board/freescale/ls1046aqds/README | 2 +-
board/freescale/ls1046aqds/eth.c | 8 +++----
board/freescale/ls1046ardb/README | 4 ++--
board/freescale/ls1046ardb/eth.c | 2 +-
board/freescale/ls1088a/README | 4 ++--
board/freescale/ls1088a/eth_ls1088ardb.c | 6 ++---
board/freescale/ls2080aqds/README | 2 +-
board/freescale/ls2080aqds/eth.c | 13 +++++------
board/freescale/ls2080ardb/README | 2 +-
board/freescale/t102xrdb/README | 2 +-
board/freescale/t102xrdb/eth_t102xrdb.c | 8 +++----
board/freescale/t208xqds/README | 18 +++++++--------
board/freescale/t208xqds/eth_t208xqds.c | 22 +++++++++----------
board/freescale/t208xqds/t208xqds.c | 8 +++----
board/freescale/t208xrdb/README | 4 ++--
board/freescale/t4rdb/eth.c | 2 +-
doc/device-tree-bindings/net/ethernet.txt | 12 +++++++++-
drivers/net/fm/b4860.c | 2 +-
drivers/net/fm/eth.c | 10 ++++-----
drivers/net/fm/ls1043.c | 4 ++--
drivers/net/fm/ls1046.c | 2 +-
drivers/net/fm/memac.c | 6 ++---
drivers/net/fm/t1024.c | 2 +-
drivers/net/fsl_enetc.c | 10 ++++-----
drivers/net/mscc_eswitch/felix_switch.c | 7 +++---
drivers/net/pfe_eth/pfe_mdio.c | 4 ++--
drivers/net/phy/aquantia.c | 18 +++++++--------
include/phy.h | 2 +-
include/phy_interface.h | 4 ++--
52 files changed, 154 insertions(+), 148 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/4] net: replace the "xfi" phy-mode with "10gbase-r" 2021-09-18 12:32 [PATCH 0/4] phy-mode cleanup Vladimir Oltean @ 2021-09-18 12:32 ` Vladimir Oltean 2021-09-28 13:28 ` Ramon Fried 2021-09-18 12:32 ` [PATCH 2/4] net: freescale: replace usage of phy-mode = "sgmii-2500" with "2500base-x" Vladimir Oltean ` (2 subsequent siblings) 3 siblings, 1 reply; 9+ messages in thread From: Vladimir Oltean @ 2021-09-18 12:32 UTC (permalink / raw) To: u-boot Cc: Joe Hershberger, Ramon Fried, Priyanka Jain, Madalin Bucur, Ioana Ciornei, Camelia Groza, Scott Wood, Pali Rohár, Marcin Wojtas, Stefan Chulski As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +- .../cpu/armv8/fsl-layerscape/doc/README.soc | 8 +++---- .../cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 2 +- arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi | 4 ++-- arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi | 4 ++-- arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi | 16 +++++++------- arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 16 +++++++------- arch/arm/dts/fsl-sch-30841.dtsi | 2 +- arch/arm/dts/fsl-sch-30842.dtsi | 2 +- board/Marvell/octeon_ebb7304/board.c | 6 ++--- board/freescale/ls1043aqds/README | 2 +- board/freescale/ls1043aqds/eth.c | 4 ++-- board/freescale/ls1043ardb/README | 2 +- board/freescale/ls1043ardb/eth.c | 2 +- board/freescale/ls1046aqds/README | 2 +- board/freescale/ls1046aqds/eth.c | 4 ++-- board/freescale/ls1046ardb/README | 4 ++-- board/freescale/ls1046ardb/eth.c | 2 +- board/freescale/ls1088a/README | 4 ++-- board/freescale/ls1088a/eth_ls1088ardb.c | 6 ++--- board/freescale/ls2080aqds/README | 2 +- board/freescale/ls2080aqds/eth.c | 13 +++++------ board/freescale/ls2080ardb/README | 2 +- board/freescale/t102xrdb/README | 2 +- board/freescale/t102xrdb/eth_t102xrdb.c | 2 +- board/freescale/t208xqds/README | 18 +++++++-------- board/freescale/t208xqds/eth_t208xqds.c | 22 +++++++++---------- board/freescale/t208xqds/t208xqds.c | 8 +++---- board/freescale/t208xrdb/README | 4 ++-- board/freescale/t4rdb/eth.c | 2 +- doc/device-tree-bindings/net/ethernet.txt | 12 +++++++++- drivers/net/fm/b4860.c | 2 +- drivers/net/fm/memac.c | 4 ++-- drivers/net/fsl_enetc.c | 4 ++-- drivers/net/mscc_eswitch/felix_switch.c | 2 +- drivers/net/phy/aquantia.c | 14 ++++++------ include/phy.h | 2 +- include/phy_interface.h | 4 ++-- 38 files changed, 111 insertions(+), 102 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d0103fc8811e..1a359d060e82 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1147,7 +1147,7 @@ int arch_early_init_r(void) #endif #ifdef CONFIG_SYS_FSL_HAS_RGMII /* some dpmacs in armv8a based freescale layerscape SOCs can be - * configured via both serdes(sgmii, xfi, xlaui etc) bits and via + * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via * EC*_PMUX(rgmii) bits in RCW. * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index f33d05d0539f..f2efd4cc1d70 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -31,7 +31,7 @@ The LS1043A SoC includes the following function and features: - Hardware buffer management for buffer allocation and de-allocation (BMan) - Cryptography acceleration (SEC) - Ethernet interfaces by FMan - - Up to 1 x XFI supporting 10G interface + - Up to 1 x 10GBase-R supporting 10G interface - Up to 1 x QSGMII - Up to 4 x SGMII supporting 1000Mbps - Up to 2 x SGMII supporting 2500Mbps @@ -190,7 +190,7 @@ The LS1046A SoC includes the following function and features: - Two PLLs per four-lane SerDes - Support for 10G operation - Ethernet interfaces by FMan - - Up to 2 x XFI supporting 10G interface (MAC 9, 10) + - Up to 2 x 10GBase-R supporting 10G interface (MAC 9, 10) - Up to 1 x QSGMII (MAC 5, 6, 10, 1) - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10) - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10) @@ -295,7 +295,7 @@ The LX2160A SoC includes the following function and features: Single WRIOP tile supporting 130Gbps using 18 MACs Support for 10G-SXGMII (aka USXGMII). Support for SGMII (and 1000Base-KX) - Support for XFI (and 10GBase-KR) + Support for 10GBase-R (and 10GBase-KR) Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G). Support for XLAUI (and 40GBase-KR4) for 40G. Support for two RGMII parallel interfaces. @@ -400,7 +400,7 @@ The LX2162A SoC includes the following function and features: Ethernet interfaces Support for 10G-SXGMII (aka USXGMII). Support for SGMII (and 1000Base-KX) - Support for XFI (and 10GBase-KR) + Support for 10GBase-R (and 10GBase-KR) Support for CAUI2 (50G) and 25G-AUI(25G). Support for XLAUI (and 40GBase-KR4) for 40G. Support for two RGMII parallel interfaces. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c index 280afbbf98f7..26f8a4982692 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c @@ -100,7 +100,7 @@ enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) return 0; /* - * LS1044A/1048A support only one XFI port + * LS1044A/1048A support only one 10GBase-R port * Disable MAC1 for LS1044A/1048A */ if (serdes == FSL_SRDS_1 && lane == 2) { diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi index e0a6c04835bf..df39cca6961c 100644 --- a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi +++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi @@ -9,12 +9,12 @@ &dpmac1 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac2 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac4 { diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi index 65e95300ab56..99f74c2fc4d3 100644 --- a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi +++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi @@ -9,10 +9,10 @@ &dpmac1 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac2 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; diff --git a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi index ccbb5de1eaef..72297f48ca65 100644 --- a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi +++ b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi @@ -9,40 +9,40 @@ &dpmac1 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac2 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac3 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac4 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac5 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac6 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac7 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac8 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts index 179ed19bf2c1..9e68c147e607 100644 --- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts +++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts @@ -24,49 +24,49 @@ &dpmac1 { status = "okay"; phy-handle = <&mdio1_phy1>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac2 { status = "okay"; phy-handle = <&mdio1_phy2>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac3 { status = "okay"; phy-handle = <&mdio1_phy3>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac4 { status = "okay"; phy-handle = <&mdio1_phy4>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac5 { status = "okay"; phy-handle = <&mdio2_phy1>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac6 { status = "okay"; phy-handle = <&mdio2_phy2>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac7 { status = "okay"; phy-handle = <&mdio2_phy3>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac8 { status = "okay"; phy-handle = <&mdio2_phy4>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &emdio1 { diff --git a/arch/arm/dts/fsl-sch-30841.dtsi b/arch/arm/dts/fsl-sch-30841.dtsi index ca437d178281..0a723c21b8f8 100644 --- a/arch/arm/dts/fsl-sch-30841.dtsi +++ b/arch/arm/dts/fsl-sch-30841.dtsi @@ -9,7 +9,7 @@ * SCH-30841 is a 4 port add-on card used with various FSL QDS boards. * It integrates a AQR412C quad PHY which supports 4 interfaces either muxed * together on a single lane or mapped 1:1 to serdes lanes. - * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI. + * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, 10GBase-R. * PHY addresses are 0x00 - 0x03. * On the card the first port is the bottom port (closest to PEX connector). */ diff --git a/arch/arm/dts/fsl-sch-30842.dtsi b/arch/arm/dts/fsl-sch-30842.dtsi index fa0f2cdb1096..b64aeb3fcce6 100644 --- a/arch/arm/dts/fsl-sch-30842.dtsi +++ b/arch/arm/dts/fsl-sch-30842.dtsi @@ -8,7 +8,7 @@ /* * SCH-30842 is a single port add-on card used with various FSL QDS boards. * It integrates a AQR112 PHY, which supports several protocols - SGMII, - * SGMII-2500, USXGMII, XFI. + * SGMII-2500, USXGMII, 10GBase-R. * PHY address is 0x02. */ phy@02 { diff --git a/board/Marvell/octeon_ebb7304/board.c b/board/Marvell/octeon_ebb7304/board.c index 9aac5f0b09f5..e8e2d547c1ee 100644 --- a/board/Marvell/octeon_ebb7304/board.c +++ b/board/Marvell/octeon_ebb7304/board.c @@ -339,7 +339,7 @@ void __fixup_fdt(void) case CVMX_QLM_MODE_XFI: case CVMX_QLM_MODE_RGMII_XFI: case CVMX_QLM_MODE_RGMII_XFI_1X1: - type_str = "xfi"; + type_str = "10gbase-r"; break; case CVMX_QLM_MODE_10G_KR: case CVMX_QLM_MODE_RGMII_10G_KR: @@ -393,7 +393,7 @@ void __fixup_fdt(void) if (pmd_control.s.train_en) type_str = "10G_KR"; else - type_str = "xfi"; + type_str = "10gbase-r"; break; case 4: if (pmd_control.s.train_en) @@ -618,7 +618,7 @@ static void board_configure_qlms(void) speed[qlm] = 103125; } printf("QLM %d: XLAUI\n", qlm); - } else if (!strncmp(mode_str, "xfi", 3)) { + } else if (!strncmp(mode_str, "10gbase-r", 3)) { bool rgmii = false; speed[qlm] = 103125; diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README index 913537d45190..f5aa51da87eb 100644 --- a/board/freescale/ls1043aqds/README +++ b/board/freescale/ls1043aqds/README @@ -18,7 +18,7 @@ SoC overview. - SGMII, SGMII 2.5 - QSGMII - SATA 3.0 - - XFI + - 10GBase-R - DDR Controller - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s -IFC/Local Bus diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index c3efe8a0be64..81e18f6e82b5 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -242,13 +242,13 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, "qsgmii"); } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && port == FM1_10GEC1) { - /* XFI interface */ + /* 10GBase-R interface */ f_link.phy_id = cpu_to_fdt32(port); f_link.duplex = cpu_to_fdt32(1); f_link.link_speed = cpu_to_fdt32(10000); f_link.pause = 0; f_link.asym_pause = 0; - /* no PHY for XFI */ + /* no PHY for 10GBase-R */ fdt_delprop(fdt, offset, "phy-handle"); fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README index 709ddbbef31a..66ee578e99d9 100644 --- a/board/freescale/ls1043ardb/README +++ b/board/freescale/ls1043ardb/README @@ -17,7 +17,7 @@ SoC overview. - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and standard PCIe card - QSGMII with x4 RJ45 connector - - XFI with x1 RJ45 connector + - 10GBase-R with x1 RJ45 connector - DDR Controller - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s -IFC/Local Bus diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c index 1f01c1551656..fa59116ce57b 100644 --- a/board/freescale/ls1043ardb/eth.c +++ b/board/freescale/ls1043ardb/eth.c @@ -65,7 +65,7 @@ int board_eth_init(struct bd_info *bis) for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) fm_info_set_mdio(i, dev); - /* XFI on lane A, MAC 9 */ + /* 10GBase-R on lane A, MAC 9 */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); fm_info_set_mdio(FM1_10GEC1, dev); diff --git a/board/freescale/ls1046aqds/README b/board/freescale/ls1046aqds/README index b8fa32652b0d..d6469019bd26 100644 --- a/board/freescale/ls1046aqds/README +++ b/board/freescale/ls1046aqds/README @@ -18,7 +18,7 @@ SoC overview. - SGMII, SGMII 2.5 - QSGMII - SATA 3.0 - - XFI + - 10GBase-R - DDR Controller - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s -IFC/Local Bus diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index 33db552adb8a..23528324662e 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -217,13 +217,13 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, /* Backplane KR mode: skip fixups */ printf("Interface %d in backplane KR mode\n", port); } else { - /* XFI interface */ + /* 10GBase-R interface */ f_link.phy_id = cpu_to_fdt32(port); f_link.duplex = cpu_to_fdt32(1); f_link.link_speed = cpu_to_fdt32(10000); f_link.pause = 0; f_link.asym_pause = 0; - /* no PHY for XFI */ + /* no PHY for 10GBase-R */ fdt_delprop(fdt, offset, "phy-handle"); fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); diff --git a/board/freescale/ls1046ardb/README b/board/freescale/ls1046ardb/README index a38c9d48300e..1660f7c7cf90 100644 --- a/board/freescale/ls1046ardb/README +++ b/board/freescale/ls1046ardb/README @@ -14,8 +14,8 @@ SoC overview. LS1046ARDB board Overview ----------------------- - SERDES1 Connections, 4 lanes supporting: - - Lane0: XFI with x1 RJ45 connector - - Lane1: XFI Cage + - Lane0: 10GBase-R with x1 RJ45 connector + - Lane1: 10GBase-R Cage - Lane2: SGMII.5 - Lane3: SGMII.6 - SERDES2 Connections, 4 lanes supporting: diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c index 4905302d8cd9..a3e147a48b98 100644 --- a/board/freescale/ls1046ardb/eth.c +++ b/board/freescale/ls1046ardb/eth.c @@ -67,7 +67,7 @@ int board_eth_init(struct bd_info *bis) for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) fm_info_set_mdio(i, dev); - /* XFI on lane A, MAC 9 */ + /* 10GBase-R on lane A, MAC 9 */ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); fm_info_set_mdio(FM1_10GEC1, dev); diff --git a/board/freescale/ls1088a/README b/board/freescale/ls1088a/README index aa0fb6ac676f..5315909defc8 100644 --- a/board/freescale/ls1088a/README +++ b/board/freescale/ls1088a/README @@ -42,7 +42,7 @@ Alternately you can use this command to switch from QSPI to SD - SERDES Connections, 16 lanes supporting: - PCI Express - 3.0 - SATA 3.0 - - XFI + - 10GBase-R - QSGMII - DDR Controller - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four @@ -106,7 +106,7 @@ SW12 1111 1111 - SERDES Connections, 16 lanes supporting: - PCI Express - 3.0 - SATA 3.0 - - 2 XFI + - 2 10GBase-R - QSGMII, SGMII with help for Riser card - 2 RGMII - 5 slot for Riser card or PCIe NIC diff --git a/board/freescale/ls1088a/eth_ls1088ardb.c b/board/freescale/ls1088a/eth_ls1088ardb.c index a8e9ef15dc48..1ba5e94d0a0a 100644 --- a/board/freescale/ls1088a/eth_ls1088ardb.c +++ b/board/freescale/ls1088a/eth_ls1088ardb.c @@ -52,9 +52,9 @@ int board_eth_init(struct bd_info *bis) switch (srds_s1) { case 0x1D: /* - * XFI does not need a PHY to work, but to avoid U-boot use - * default PHY address which is zero to a MAC when it found - * a MAC has no PHY address, we give a PHY address to XFI + * 10GBase-R does not need a PHY to work, but to avoid U-boot + * use default PHY address which is zero to a MAC when it found + * a MAC has no PHY address, we give a PHY address to 10GBase-R * MAC error. */ wriop_set_phy_address(WRIOP1_DPMAC1, 0, 0x0a); diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README index 8e31e9e41e3e..04c1941b056e 100644 --- a/board/freescale/ls2080aqds/README +++ b/board/freescale/ls2080aqds/README @@ -19,7 +19,7 @@ LS2088A SoC overview. - QSGMII - SATA 3.0 - XAUI - - XFI + - 10GBase-R - DDR Controller - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four chip-selects and two DIMM connectors. Support is up to 2133MT/s. diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 914cd0a9ab59..7db37898220a 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -874,13 +874,12 @@ void ls2080a_handle_phy_interface_xsgmii(int i) case 0x4B: case 0x4C: /* - * XFI does not need a PHY to work, but to avoid U-Boot use - * default PHY address which is zero to a MAC when it found - * a MAC has no PHY address, we give a PHY address to XFI - * MAC, and should not use a real XAUI PHY address, since - * MDIO can access it successfully, and then MDIO thinks - * the XAUI card is used for the XFI MAC, which will cause - * error. + * 10GBase-R does not need a PHY to work, but to avoid U-Boot + * use default PHY address which is zero to a MAC when it found + * a MAC has no PHY address, we give a PHY address to 10GBase-R + * MAC, and should not use a real XAUI PHY address, since MDIO + * can access it successfully, and then MDIO thinks the XAUI + * card is used for the 10GBase-R MAC, which will cause error. */ wriop_set_phy_address(i, 0, i + 4); ls2080a_qds_enable_SFP_TX(SFP_TX); diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README index 205c45cb2af3..75a633ccb4ef 100644 --- a/board/freescale/ls2080ardb/README +++ b/board/freescale/ls2080ardb/README @@ -18,7 +18,7 @@ LS2081A, LS2088A SoC overview. - SERDES Connections, 16 lanes supporting: - PCI Express - 3.0 - SATA 3.0 - - XFI + - 10GBase-R - DDR Controller - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four chip-selects and two DIMM connectors. Support is up to 2133MT/s. diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README index dde3f8ca37f6..84deb9562a14 100644 --- a/board/freescale/t102xrdb/README +++ b/board/freescale/t102xrdb/README @@ -39,7 +39,7 @@ The T1024 SoC includes the following function and features: - One QSGMII interface - Four SGMII interface supporting 1000 Mbps - Three SGMII interfaces supporting up to 2500 Mbps - - 10GbE XFI or 10Base-KR interface + - 10GBase-R or 10Base-KR interface - Additional peripheral interfaces - Two USB 2.0 controllers with integrated PHY - SD/eSDHC/eMMC diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index 56e6109288f7..b28c5457d67e 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -64,7 +64,7 @@ int board_eth_init(struct bd_info *bis) /* set the on-board RGMII2 PHY */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); - /* set 10G XFI with Aquantia AQR105 PHY */ + /* set 10GBase-R with Aquantia AQR105 PHY */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); break; #endif diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README index d690857f2e28..b52d9610e981 100755 --- a/board/freescale/t208xqds/README +++ b/board/freescale/t208xqds/README @@ -55,14 +55,14 @@ Memory: - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support Ethernet interfaces: - Two 1Gbps RGMII on-board ports - - Four 10Gbps XFI on-board cages + - Four 10GBase-R on-board cages - 1Gbps/2.5Gbps SGMII Riser card - 10Gbps XAUI Riser card Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes: - 16 lanes up to 10.3125GHz - - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI + - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, 10GBase-R and XAUI IFC: - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA eSPI: @@ -85,14 +85,14 @@ System Logic: - QIXIS-II FPGA system controll Debug Features: - Support Legacy, COP/JTAG, Aurora, Event and EVT -XFI: - - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to +10GBase-R: + - 10GBase-R is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to a on-board SFP+ cages, which to house optical module (fiber cable) or direct attach cable(copper), the copper cable is used to emulate 10GBASE-KR scenario. - So, for XFI usage, there are two scenarios, one will use fiber cable, + So, for 10GBase-R usage, there are two scenarios, one will use fiber cable, another will use copper cable. An hwconfig env "fsl_10gkr_copper" is - introduced to indicate a XFI port will use copper cable, and U-Boot + introduced to indicate a 10GBase-R port will use copper cable, and U-Boot will fixup the dtb accordingly. It's used as: fsl_10gkr_copper:<10g_mac_name> The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they @@ -100,10 +100,10 @@ XFI: "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable will be used by default. for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in - hwconfig, then both four XFI ports will use copper cable. + hwconfig, then both four 10GBase-R ports will use copper cable. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two - XFI ports will use copper cable, the other two XFI ports will use fiber - cable. + 10GBase-R ports will use copper cable, the other two 10GBase-R ports will use + fiber cable. 1000BASE-KX(1G-KX): - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 705387af3c31..2d7fc8bdda2e 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -310,16 +310,16 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { switch (srds_s1) { - case 0x66: /* XFI interface */ + case 0x66: /* 10GBase-R interface */ case 0x6b: case 0x6c: case 0x6d: case 0x71: /* - * if the 10G is XFI, check hwconfig to see what is the - * media type, there are two types, fiber or copper, - * fix the dtb accordingly. - */ + * Check hwconfig to see what is the media type, there + * are two types, fiber or copper, fix the dtb + * accordingly. + */ switch (port) { case FM1_10GEC1: if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { @@ -378,7 +378,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, printf("Interface %d in backplane KR mode\n", port); } else { - /* fixed-link for XFI fiber cable */ + /* fixed-link for 10GBase-R fiber cable */ f_link.phy_id = port; f_link.duplex = 1; f_link.link_speed = 10000; @@ -538,12 +538,12 @@ int board_eth_init(struct bd_info *bis) case 0x66: case 0x67: /* - * XFI does not need a PHY to work, but to avoid U-Boot use - * default PHY address which is zero to a MAC when it found - * a MAC has no PHY address, we give a PHY address to XFI + * 10GBase-R does not need a PHY to work, but to avoid U-Boot + * use default PHY address which is zero to a MAC when it found + * a MAC has no PHY address, we give a PHY address to 10GBase-R * MAC, and should not use a real XAUI PHY address, since * MDIO can access it successfully, and then MDIO thinks - * the XAUI card is used for the XFI MAC, which will cause + * the XAUI card is used for the 10GBase-R MAC, which will cause * error. */ fm_info_set_phy_address(FM1_10GEC1, 4); @@ -701,7 +701,7 @@ int board_eth_init(struct bd_info *bis) (srds_s1 == 0x6a) || (srds_s1 == 0x70) || (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || (srds_s1 == 0x71)) { - /* As XFI is in cage intead of a slot, so + /* As 10GBase-R is in cage intead of a slot, so * ensure doesn't disable the corresponding port */ break; diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 715de106d69b..e54672a80ba4 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -136,14 +136,14 @@ int brd_mux_lane_to_slot(void) break; case 0x66: case 0x67: - /* SD1(A:D) => XFI cage + /* SD1(A:D) => 10GBase-R cage * SD1(E:H) => SLOT1 PCIe4 */ QIXIS_WRITE(brdcfg[12], 0xfe); break; case 0x6a: case 0x6b: - /* SD1(A:D) => XFI cage + /* SD1(A:D) => 10GBase-R cage * SD1(E) => SLOT1 PCIe4 * SD1(F:H) => SLOT2 SGMII */ @@ -151,14 +151,14 @@ int brd_mux_lane_to_slot(void) break; case 0x6c: case 0x6d: - /* SD1(A:B) => XFI cage + /* SD1(A:B) => 10GBase-R cage * SD1(C:D) => SLOT3 SGMII * SD1(E:H) => SLOT1 PCIe4 */ QIXIS_WRITE(brdcfg[12], 0xda); break; case 0x6e: - /* SD1(A:B) => SFP Module, XFI + /* SD1(A:B) => SFP Module, 10GBase-R * SD1(C:D) => SLOT3 SGMII * SD1(E:F) => SLOT1 PCIe4 x2 * SD1(G:H) => SLOT2 SGMII diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README index ec47c96f2b1a..c4bfd3b466f4 100644 --- a/board/freescale/t208xrdb/README +++ b/board/freescale/t208xrdb/README @@ -54,7 +54,7 @@ Differences between T2080 and T2081 T2080PCIe-RDB board Overview ---------------------------- - SERDES Configuration - - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10) + - SerDes-1 Lane A-B: to two 10GBase-R fiber (MAC9 & MAC10) - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) @@ -62,7 +62,7 @@ T2080PCIe-RDB board Overview - SerDes-2 Lane G-H: to SATA1 & SATA2 - Ethernet - Two on-board 10M/100M/1G RGMII ethernet ports - - Two on-board 10Gbps XFI fiber ports + - Two on-board 10GBase-R fiber ports - Two on-board 10Gbps Base-T copper ports - DDR Memory - Supports 72bit 4GB DDR3-LP SODIMM diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c index c815a3a4fa52..34ffaa6aeb54 100644 --- a/board/freescale/t4rdb/eth.c +++ b/board/freescale/t4rdb/eth.c @@ -106,7 +106,7 @@ int board_eth_init(struct bd_info *bis) #if (CONFIG_SYS_NUM_FMAN == 2) if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) { - /* SGMII && XFI */ + /* SGMII && 10GBase-R */ fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7); diff --git a/doc/device-tree-bindings/net/ethernet.txt b/doc/device-tree-bindings/net/ethernet.txt index cfc376bc977a..648a1aee694d 100644 --- a/doc/device-tree-bindings/net/ethernet.txt +++ b/doc/device-tree-bindings/net/ethernet.txt @@ -41,7 +41,17 @@ Documentation/devicetree/bindings/phy/phy-bindings.txt. * "2500base-x", * "rxaui" * "xaui" - * "10gbase-kr" (10GBASE-KR, XFI, SFI) + * "10gbase-r" (This is the IEEE 802.3 Clause 49 defined 10GBASE-R protocol + used with various different mediums. Please refer to the IEEE standard for + a definition of this. Note: 10GBASE-R is just one protocol that can be used + with XFI and SFI. XFI and SFI permit multiple protocols over a single + SERDES lane, and also defines the electrical characteristics of the signals + with a host compliance board plugged into the host XFP/SFP connector. + Therefore, XFI and SFI are not PHY interface types in their own right.) + * "10gbase-kr" (This is the IEEE 802.3 Clause 49 defined 10GBASE-R with + Clause 73 autonegotiation. Please refer to the IEEE standard for further + information. Note: due to legacy usage, some 10GBASE-R usage incorrectly + makes use of this definition). - phy-connection-type: the same as "phy-mode" property but described in the Devicetree Specification; - phy-handle: phandle, specifies a reference to a node representing a PHY diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c index 5be0ad2ab3db..6e3d008199a5 100644 --- a/drivers/net/fm/b4860.c +++ b/drivers/net/fm/b4860.c @@ -100,7 +100,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) env_get_f("hwconfig", buffer, sizeof(buffer)); buf = buffer; - /* check if XFI interface enable in hwconfig for 10g */ + /* check if 10GBase-R interface enable in hwconfig for 10g */ if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2", "sfp_amc", "sfp", buf)) { if ((port == FM1_10GEC1 || diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c index 36f50d27826e..e1f812b688b1 100644 --- a/drivers/net/fm/memac.c +++ b/drivers/net/fm/memac.c @@ -98,7 +98,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, if_mode &= ~IF_MODE_MASK; if_mode |= (IF_MODE_GMII); break; - case PHY_INTERFACE_MODE_XFI: + case PHY_INTERFACE_MODE_10GBASER: case PHY_INTERFACE_MODE_XGMII: if_mode &= ~IF_MODE_MASK; if_mode |= IF_MODE_XGMII; @@ -107,7 +107,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, break; } /* Enable automatic speed selection for Non-XGMII */ - if (type != PHY_INTERFACE_MODE_XGMII && type != PHY_INTERFACE_MODE_XFI) + if (type != PHY_INTERFACE_MODE_XGMII && type != PHY_INTERFACE_MODE_10GBASER) if_mode |= IF_MODE_EN_AUTO; if (type == PHY_INTERFACE_MODE_RGMII || diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index 566cdc7e546a..12d9942b65d4 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -228,7 +228,7 @@ static void enetc_setup_mac_iface(struct udevice *dev, break; case PHY_INTERFACE_MODE_XGMII: case PHY_INTERFACE_MODE_USXGMII: - case PHY_INTERFACE_MODE_XFI: + case PHY_INTERFACE_MODE_10GBASER: /* set ifmode to (US)XGMII */ if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE); if_mode &= ~ENETC_PM_IF_IFMODE_MASK; @@ -296,7 +296,7 @@ static void enetc_start_pcs(struct udevice *dev) break; case PHY_INTERFACE_MODE_XGMII: case PHY_INTERFACE_MODE_USXGMII: - case PHY_INTERFACE_MODE_XFI: + case PHY_INTERFACE_MODE_10GBASER: enetc_init_sxgmii(dev); break; }; diff --git a/drivers/net/mscc_eswitch/felix_switch.c b/drivers/net/mscc_eswitch/felix_switch.c index 6aa79784460d..67b2879e8585 100644 --- a/drivers/net/mscc_eswitch/felix_switch.c +++ b/drivers/net/mscc_eswitch/felix_switch.c @@ -223,7 +223,7 @@ static void felix_start_pcs(struct udevice *dev, int port, felix_init_sgmii(imdio, port, autoneg); break; case PHY_INTERFACE_MODE_XGMII: - case PHY_INTERFACE_MODE_XFI: + case PHY_INTERFACE_MODE_10GBASER: case PHY_INTERFACE_MODE_USXGMII: if (felix_init_sxgmii(imdio, port)) dev_err(dev, "PCS reset timeout on port %d\n", port); diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index d3d35a75d065..66d1d9856825 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -310,7 +310,7 @@ struct { AQUANTIA_VND1_GSTART_RATE_1G}, [PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G, AQUANTIA_VND1_GSTART_RATE_2_5G}, - [PHY_INTERFACE_MODE_XFI] = {0x100, AQUANTIA_VND1_GSYSCFG_10G, + [PHY_INTERFACE_MODE_10GBASER] = {0x100, AQUANTIA_VND1_GSYSCFG_10G, AQUANTIA_VND1_GSTART_RATE_10G}, [PHY_INTERFACE_MODE_USXGMII] = {0x080, AQUANTIA_VND1_GSYSCFG_10G, AQUANTIA_VND1_GSTART_RATE_10G}, @@ -443,18 +443,18 @@ int aquantia_config(struct phy_device *phydev) return ret; } /* - * for backward compatibility convert XGMII into either XFI or USX based - * on FW config + * for backward compatibility convert XGMII into either 10GBase-R or + * USXGMII based on FW config */ if (interface == PHY_INTERFACE_MODE_XGMII) { - debug("use XFI or USXGMII SI protos, XGMII is not valid\n"); + debug("use 10GBase-R or USXGMII SI protos, XGMII is not valid\n"); reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS, AQUANTIA_SYSTEM_INTERFACE_SR); if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII) interface = PHY_INTERFACE_MODE_USXGMII; else - interface = PHY_INTERFACE_MODE_XFI; + interface = PHY_INTERFACE_MODE_10GBASER; } /* @@ -494,7 +494,7 @@ int aquantia_config(struct phy_device *phydev) case PHY_INTERFACE_MODE_USXGMII: usx_an = 1; /* FALLTHROUGH */ - case PHY_INTERFACE_MODE_XFI: + case PHY_INTERFACE_MODE_10GBASER: /* 10GBASE-T mode */ phydev->advertising = SUPPORTED_10000baseT_Full; phydev->supported = phydev->advertising; @@ -515,7 +515,7 @@ int aquantia_config(struct phy_device *phydev) phydev->dev->name); } else { reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA; - debug("%s: system interface XFI\n", + debug("%s: system interface 10GBase-R\n", phydev->dev->name); } diff --git a/include/phy.h b/include/phy.h index 6b928636b6d7..b9d8dc3a61ed 100644 --- a/include/phy.h +++ b/include/phy.h @@ -368,7 +368,7 @@ static inline int is_10g_interface(phy_interface_t interface) { return interface == PHY_INTERFACE_MODE_XGMII || interface == PHY_INTERFACE_MODE_USXGMII || - interface == PHY_INTERFACE_MODE_XFI; + interface == PHY_INTERFACE_MODE_10GBASER; } #endif diff --git a/include/phy_interface.h b/include/phy_interface.h index ebb18ecd40c0..f075abe9c9c0 100644 --- a/include/phy_interface.h +++ b/include/phy_interface.h @@ -37,7 +37,7 @@ typedef enum { PHY_INTERFACE_MODE_CAUI2, PHY_INTERFACE_MODE_CAUI4, PHY_INTERFACE_MODE_NCSI, - PHY_INTERFACE_MODE_XFI, + PHY_INTERFACE_MODE_10GBASER, PHY_INTERFACE_MODE_USXGMII, PHY_INTERFACE_MODE_NONE, /* Must be last */ @@ -69,7 +69,7 @@ static const char * const phy_interface_strings[] = { [PHY_INTERFACE_MODE_CAUI2] = "caui2", [PHY_INTERFACE_MODE_CAUI4] = "caui4", [PHY_INTERFACE_MODE_NCSI] = "NC-SI", - [PHY_INTERFACE_MODE_XFI] = "xfi", + [PHY_INTERFACE_MODE_10GBASER] = "10gbase-r", [PHY_INTERFACE_MODE_USXGMII] = "usxgmii", [PHY_INTERFACE_MODE_NONE] = "", }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/4] net: replace the "xfi" phy-mode with "10gbase-r" 2021-09-18 12:32 ` [PATCH 1/4] net: replace the "xfi" phy-mode with "10gbase-r" Vladimir Oltean @ 2021-09-28 13:28 ` Ramon Fried 0 siblings, 0 replies; 9+ messages in thread From: Ramon Fried @ 2021-09-28 13:28 UTC (permalink / raw) To: Vladimir Oltean Cc: U-Boot Mailing List, Joe Hershberger, Priyanka Jain, Madalin Bucur, Ioana Ciornei, Camelia Groza, Scott Wood, Pali Rohár, Marcin Wojtas, Stefan Chulski On Sat, Sep 18, 2021 at 3:34 PM Vladimir Oltean <vladimir.oltean@nxp.com> wrote: > > As part of the effort of making U-Boot work with the same device tree as > Linux, there is an issue with the "xfi" phy-mode. To be precise, in > Linux there was a discussion (for those who have time to read: > https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) > > which led to a patch: > https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 > > TL;DR: "xfi" was standardized in Linux as "10gbase-r". > > This patch changes the relevant occurrences in U-Boot to use "10gbase-r" > instead of "xfi" wherever applicable. > > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> > --- > arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +- > .../cpu/armv8/fsl-layerscape/doc/README.soc | 8 +++---- > .../cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 2 +- > arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi | 4 ++-- > arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi | 4 ++-- > arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi | 16 +++++++------- > arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 16 +++++++------- > arch/arm/dts/fsl-sch-30841.dtsi | 2 +- > arch/arm/dts/fsl-sch-30842.dtsi | 2 +- > board/Marvell/octeon_ebb7304/board.c | 6 ++--- > board/freescale/ls1043aqds/README | 2 +- > board/freescale/ls1043aqds/eth.c | 4 ++-- > board/freescale/ls1043ardb/README | 2 +- > board/freescale/ls1043ardb/eth.c | 2 +- > board/freescale/ls1046aqds/README | 2 +- > board/freescale/ls1046aqds/eth.c | 4 ++-- > board/freescale/ls1046ardb/README | 4 ++-- > board/freescale/ls1046ardb/eth.c | 2 +- > board/freescale/ls1088a/README | 4 ++-- > board/freescale/ls1088a/eth_ls1088ardb.c | 6 ++--- > board/freescale/ls2080aqds/README | 2 +- > board/freescale/ls2080aqds/eth.c | 13 +++++------ > board/freescale/ls2080ardb/README | 2 +- > board/freescale/t102xrdb/README | 2 +- > board/freescale/t102xrdb/eth_t102xrdb.c | 2 +- > board/freescale/t208xqds/README | 18 +++++++-------- > board/freescale/t208xqds/eth_t208xqds.c | 22 +++++++++---------- > board/freescale/t208xqds/t208xqds.c | 8 +++---- > board/freescale/t208xrdb/README | 4 ++-- > board/freescale/t4rdb/eth.c | 2 +- > doc/device-tree-bindings/net/ethernet.txt | 12 +++++++++- > drivers/net/fm/b4860.c | 2 +- > drivers/net/fm/memac.c | 4 ++-- > drivers/net/fsl_enetc.c | 4 ++-- > drivers/net/mscc_eswitch/felix_switch.c | 2 +- > drivers/net/phy/aquantia.c | 14 ++++++------ > include/phy.h | 2 +- > include/phy_interface.h | 4 ++-- > 38 files changed, 111 insertions(+), 102 deletions(-) > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > index d0103fc8811e..1a359d060e82 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > @@ -1147,7 +1147,7 @@ int arch_early_init_r(void) > #endif > #ifdef CONFIG_SYS_FSL_HAS_RGMII > /* some dpmacs in armv8a based freescale layerscape SOCs can be > - * configured via both serdes(sgmii, xfi, xlaui etc) bits and via > + * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via > * EC*_PMUX(rgmii) bits in RCW. > * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from > * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc > index f33d05d0539f..f2efd4cc1d70 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc > +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc > @@ -31,7 +31,7 @@ The LS1043A SoC includes the following function and features: > - Hardware buffer management for buffer allocation and de-allocation (BMan) > - Cryptography acceleration (SEC) > - Ethernet interfaces by FMan > - - Up to 1 x XFI supporting 10G interface > + - Up to 1 x 10GBase-R supporting 10G interface > - Up to 1 x QSGMII > - Up to 4 x SGMII supporting 1000Mbps > - Up to 2 x SGMII supporting 2500Mbps > @@ -190,7 +190,7 @@ The LS1046A SoC includes the following function and features: > - Two PLLs per four-lane SerDes > - Support for 10G operation > - Ethernet interfaces by FMan > - - Up to 2 x XFI supporting 10G interface (MAC 9, 10) > + - Up to 2 x 10GBase-R supporting 10G interface (MAC 9, 10) > - Up to 1 x QSGMII (MAC 5, 6, 10, 1) > - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10) > - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10) > @@ -295,7 +295,7 @@ The LX2160A SoC includes the following function and features: > Single WRIOP tile supporting 130Gbps using 18 MACs > Support for 10G-SXGMII (aka USXGMII). > Support for SGMII (and 1000Base-KX) > - Support for XFI (and 10GBase-KR) > + Support for 10GBase-R (and 10GBase-KR) > Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G). > Support for XLAUI (and 40GBase-KR4) for 40G. > Support for two RGMII parallel interfaces. > @@ -400,7 +400,7 @@ The LX2162A SoC includes the following function and features: > Ethernet interfaces > Support for 10G-SXGMII (aka USXGMII). > Support for SGMII (and 1000Base-KX) > - Support for XFI (and 10GBase-KR) > + Support for 10GBase-R (and 10GBase-KR) > Support for CAUI2 (50G) and 25G-AUI(25G). > Support for XLAUI (and 40GBase-KR4) for 40G. > Support for two RGMII parallel interfaces. > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c > index 280afbbf98f7..26f8a4982692 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c > +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c > @@ -100,7 +100,7 @@ enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) > if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) > return 0; > /* > - * LS1044A/1048A support only one XFI port > + * LS1044A/1048A support only one 10GBase-R port > * Disable MAC1 for LS1044A/1048A > */ > if (serdes == FSL_SRDS_1 && lane == 2) { > diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi > index e0a6c04835bf..df39cca6961c 100644 > --- a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi > +++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi > @@ -9,12 +9,12 @@ > > &dpmac1 { > status = "okay"; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > > &dpmac2 { > status = "okay"; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > > &dpmac4 { > diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi > index 65e95300ab56..99f74c2fc4d3 100644 > --- a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi > +++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi > @@ -9,10 +9,10 @@ > > &dpmac1 { > status = "okay"; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > > &dpmac2 { > status = "okay"; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > diff --git a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi > index ccbb5de1eaef..72297f48ca65 100644 > --- a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi > +++ b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi > @@ -9,40 +9,40 @@ > > &dpmac1 { > status = "okay"; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > > &dpmac2 { > status = "okay"; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > > &dpmac3 { > status = "okay"; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > > &dpmac4 { > status = "okay"; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > > &dpmac5 { > status = "okay"; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > > &dpmac6 { > status = "okay"; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > > &dpmac7 { > status = "okay"; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > > &dpmac8 { > status = "okay"; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts > index 179ed19bf2c1..9e68c147e607 100644 > --- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts > +++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts > @@ -24,49 +24,49 @@ > &dpmac1 { > status = "okay"; > phy-handle = <&mdio1_phy1>; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > > &dpmac2 { > status = "okay"; > phy-handle = <&mdio1_phy2>; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > > &dpmac3 { > status = "okay"; > phy-handle = <&mdio1_phy3>; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > > &dpmac4 { > status = "okay"; > phy-handle = <&mdio1_phy4>; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > > &dpmac5 { > status = "okay"; > phy-handle = <&mdio2_phy1>; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > > &dpmac6 { > status = "okay"; > phy-handle = <&mdio2_phy2>; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > > &dpmac7 { > status = "okay"; > phy-handle = <&mdio2_phy3>; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > > &dpmac8 { > status = "okay"; > phy-handle = <&mdio2_phy4>; > - phy-connection-type = "xfi"; > + phy-connection-type = "10gbase-r"; > }; > > &emdio1 { > diff --git a/arch/arm/dts/fsl-sch-30841.dtsi b/arch/arm/dts/fsl-sch-30841.dtsi > index ca437d178281..0a723c21b8f8 100644 > --- a/arch/arm/dts/fsl-sch-30841.dtsi > +++ b/arch/arm/dts/fsl-sch-30841.dtsi > @@ -9,7 +9,7 @@ > * SCH-30841 is a 4 port add-on card used with various FSL QDS boards. > * It integrates a AQR412C quad PHY which supports 4 interfaces either muxed > * together on a single lane or mapped 1:1 to serdes lanes. > - * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI. > + * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, 10GBase-R. > * PHY addresses are 0x00 - 0x03. > * On the card the first port is the bottom port (closest to PEX connector). > */ > diff --git a/arch/arm/dts/fsl-sch-30842.dtsi b/arch/arm/dts/fsl-sch-30842.dtsi > index fa0f2cdb1096..b64aeb3fcce6 100644 > --- a/arch/arm/dts/fsl-sch-30842.dtsi > +++ b/arch/arm/dts/fsl-sch-30842.dtsi > @@ -8,7 +8,7 @@ > /* > * SCH-30842 is a single port add-on card used with various FSL QDS boards. > * It integrates a AQR112 PHY, which supports several protocols - SGMII, > - * SGMII-2500, USXGMII, XFI. > + * SGMII-2500, USXGMII, 10GBase-R. > * PHY address is 0x02. > */ > phy@02 { > diff --git a/board/Marvell/octeon_ebb7304/board.c b/board/Marvell/octeon_ebb7304/board.c > index 9aac5f0b09f5..e8e2d547c1ee 100644 > --- a/board/Marvell/octeon_ebb7304/board.c > +++ b/board/Marvell/octeon_ebb7304/board.c > @@ -339,7 +339,7 @@ void __fixup_fdt(void) > case CVMX_QLM_MODE_XFI: > case CVMX_QLM_MODE_RGMII_XFI: > case CVMX_QLM_MODE_RGMII_XFI_1X1: > - type_str = "xfi"; > + type_str = "10gbase-r"; > break; > case CVMX_QLM_MODE_10G_KR: > case CVMX_QLM_MODE_RGMII_10G_KR: > @@ -393,7 +393,7 @@ void __fixup_fdt(void) > if (pmd_control.s.train_en) > type_str = "10G_KR"; > else > - type_str = "xfi"; > + type_str = "10gbase-r"; > break; > case 4: > if (pmd_control.s.train_en) > @@ -618,7 +618,7 @@ static void board_configure_qlms(void) > speed[qlm] = 103125; > } > printf("QLM %d: XLAUI\n", qlm); > - } else if (!strncmp(mode_str, "xfi", 3)) { > + } else if (!strncmp(mode_str, "10gbase-r", 3)) { > bool rgmii = false; > > speed[qlm] = 103125; > diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README > index 913537d45190..f5aa51da87eb 100644 > --- a/board/freescale/ls1043aqds/README > +++ b/board/freescale/ls1043aqds/README > @@ -18,7 +18,7 @@ SoC overview. > - SGMII, SGMII 2.5 > - QSGMII > - SATA 3.0 > - - XFI > + - 10GBase-R > - DDR Controller > - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s > -IFC/Local Bus > diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c > index c3efe8a0be64..81e18f6e82b5 100644 > --- a/board/freescale/ls1043aqds/eth.c > +++ b/board/freescale/ls1043aqds/eth.c > @@ -242,13 +242,13 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, > "qsgmii"); > } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && > port == FM1_10GEC1) { > - /* XFI interface */ > + /* 10GBase-R interface */ > f_link.phy_id = cpu_to_fdt32(port); > f_link.duplex = cpu_to_fdt32(1); > f_link.link_speed = cpu_to_fdt32(10000); > f_link.pause = 0; > f_link.asym_pause = 0; > - /* no PHY for XFI */ > + /* no PHY for 10GBase-R */ > fdt_delprop(fdt, offset, "phy-handle"); > fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); > fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); > diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README > index 709ddbbef31a..66ee578e99d9 100644 > --- a/board/freescale/ls1043ardb/README > +++ b/board/freescale/ls1043ardb/README > @@ -17,7 +17,7 @@ SoC overview. > - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and > standard PCIe card > - QSGMII with x4 RJ45 connector > - - XFI with x1 RJ45 connector > + - 10GBase-R with x1 RJ45 connector > - DDR Controller > - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s > -IFC/Local Bus > diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c > index 1f01c1551656..fa59116ce57b 100644 > --- a/board/freescale/ls1043ardb/eth.c > +++ b/board/freescale/ls1043ardb/eth.c > @@ -65,7 +65,7 @@ int board_eth_init(struct bd_info *bis) > for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) > fm_info_set_mdio(i, dev); > > - /* XFI on lane A, MAC 9 */ > + /* 10GBase-R on lane A, MAC 9 */ > fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); > dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); > fm_info_set_mdio(FM1_10GEC1, dev); > diff --git a/board/freescale/ls1046aqds/README b/board/freescale/ls1046aqds/README > index b8fa32652b0d..d6469019bd26 100644 > --- a/board/freescale/ls1046aqds/README > +++ b/board/freescale/ls1046aqds/README > @@ -18,7 +18,7 @@ SoC overview. > - SGMII, SGMII 2.5 > - QSGMII > - SATA 3.0 > - - XFI > + - 10GBase-R > - DDR Controller > - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s > -IFC/Local Bus > diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c > index 33db552adb8a..23528324662e 100644 > --- a/board/freescale/ls1046aqds/eth.c > +++ b/board/freescale/ls1046aqds/eth.c > @@ -217,13 +217,13 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, > /* Backplane KR mode: skip fixups */ > printf("Interface %d in backplane KR mode\n", port); > } else { > - /* XFI interface */ > + /* 10GBase-R interface */ > f_link.phy_id = cpu_to_fdt32(port); > f_link.duplex = cpu_to_fdt32(1); > f_link.link_speed = cpu_to_fdt32(10000); > f_link.pause = 0; > f_link.asym_pause = 0; > - /* no PHY for XFI */ > + /* no PHY for 10GBase-R */ > fdt_delprop(fdt, offset, "phy-handle"); > fdt_setprop(fdt, offset, "fixed-link", &f_link, > sizeof(f_link)); > diff --git a/board/freescale/ls1046ardb/README b/board/freescale/ls1046ardb/README > index a38c9d48300e..1660f7c7cf90 100644 > --- a/board/freescale/ls1046ardb/README > +++ b/board/freescale/ls1046ardb/README > @@ -14,8 +14,8 @@ SoC overview. > LS1046ARDB board Overview > ----------------------- > - SERDES1 Connections, 4 lanes supporting: > - - Lane0: XFI with x1 RJ45 connector > - - Lane1: XFI Cage > + - Lane0: 10GBase-R with x1 RJ45 connector > + - Lane1: 10GBase-R Cage > - Lane2: SGMII.5 > - Lane3: SGMII.6 > - SERDES2 Connections, 4 lanes supporting: > diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c > index 4905302d8cd9..a3e147a48b98 100644 > --- a/board/freescale/ls1046ardb/eth.c > +++ b/board/freescale/ls1046ardb/eth.c > @@ -67,7 +67,7 @@ int board_eth_init(struct bd_info *bis) > for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) > fm_info_set_mdio(i, dev); > > - /* XFI on lane A, MAC 9 */ > + /* 10GBase-R on lane A, MAC 9 */ > dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); > fm_info_set_mdio(FM1_10GEC1, dev); > > diff --git a/board/freescale/ls1088a/README b/board/freescale/ls1088a/README > index aa0fb6ac676f..5315909defc8 100644 > --- a/board/freescale/ls1088a/README > +++ b/board/freescale/ls1088a/README > @@ -42,7 +42,7 @@ Alternately you can use this command to switch from QSPI to SD > - SERDES Connections, 16 lanes supporting: > - PCI Express - 3.0 > - SATA 3.0 > - - XFI > + - 10GBase-R > - QSGMII > - DDR Controller > - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four > @@ -106,7 +106,7 @@ SW12 1111 1111 > - SERDES Connections, 16 lanes supporting: > - PCI Express - 3.0 > - SATA 3.0 > - - 2 XFI > + - 2 10GBase-R > - QSGMII, SGMII with help for Riser card > - 2 RGMII > - 5 slot for Riser card or PCIe NIC > diff --git a/board/freescale/ls1088a/eth_ls1088ardb.c b/board/freescale/ls1088a/eth_ls1088ardb.c > index a8e9ef15dc48..1ba5e94d0a0a 100644 > --- a/board/freescale/ls1088a/eth_ls1088ardb.c > +++ b/board/freescale/ls1088a/eth_ls1088ardb.c > @@ -52,9 +52,9 @@ int board_eth_init(struct bd_info *bis) > switch (srds_s1) { > case 0x1D: > /* > - * XFI does not need a PHY to work, but to avoid U-boot use > - * default PHY address which is zero to a MAC when it found > - * a MAC has no PHY address, we give a PHY address to XFI > + * 10GBase-R does not need a PHY to work, but to avoid U-boot > + * use default PHY address which is zero to a MAC when it found > + * a MAC has no PHY address, we give a PHY address to 10GBase-R > * MAC error. > */ > wriop_set_phy_address(WRIOP1_DPMAC1, 0, 0x0a); > diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README > index 8e31e9e41e3e..04c1941b056e 100644 > --- a/board/freescale/ls2080aqds/README > +++ b/board/freescale/ls2080aqds/README > @@ -19,7 +19,7 @@ LS2088A SoC overview. > - QSGMII > - SATA 3.0 > - XAUI > - - XFI > + - 10GBase-R > - DDR Controller > - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four > chip-selects and two DIMM connectors. Support is up to 2133MT/s. > diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c > index 914cd0a9ab59..7db37898220a 100644 > --- a/board/freescale/ls2080aqds/eth.c > +++ b/board/freescale/ls2080aqds/eth.c > @@ -874,13 +874,12 @@ void ls2080a_handle_phy_interface_xsgmii(int i) > case 0x4B: > case 0x4C: > /* > - * XFI does not need a PHY to work, but to avoid U-Boot use > - * default PHY address which is zero to a MAC when it found > - * a MAC has no PHY address, we give a PHY address to XFI > - * MAC, and should not use a real XAUI PHY address, since > - * MDIO can access it successfully, and then MDIO thinks > - * the XAUI card is used for the XFI MAC, which will cause > - * error. > + * 10GBase-R does not need a PHY to work, but to avoid U-Boot > + * use default PHY address which is zero to a MAC when it found > + * a MAC has no PHY address, we give a PHY address to 10GBase-R > + * MAC, and should not use a real XAUI PHY address, since MDIO > + * can access it successfully, and then MDIO thinks the XAUI > + * card is used for the 10GBase-R MAC, which will cause error. > */ > wriop_set_phy_address(i, 0, i + 4); > ls2080a_qds_enable_SFP_TX(SFP_TX); > diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README > index 205c45cb2af3..75a633ccb4ef 100644 > --- a/board/freescale/ls2080ardb/README > +++ b/board/freescale/ls2080ardb/README > @@ -18,7 +18,7 @@ LS2081A, LS2088A SoC overview. > - SERDES Connections, 16 lanes supporting: > - PCI Express - 3.0 > - SATA 3.0 > - - XFI > + - 10GBase-R > - DDR Controller > - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four > chip-selects and two DIMM connectors. Support is up to 2133MT/s. > diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README > index dde3f8ca37f6..84deb9562a14 100644 > --- a/board/freescale/t102xrdb/README > +++ b/board/freescale/t102xrdb/README > @@ -39,7 +39,7 @@ The T1024 SoC includes the following function and features: > - One QSGMII interface > - Four SGMII interface supporting 1000 Mbps > - Three SGMII interfaces supporting up to 2500 Mbps > - - 10GbE XFI or 10Base-KR interface > + - 10GBase-R or 10Base-KR interface > - Additional peripheral interfaces > - Two USB 2.0 controllers with integrated PHY > - SD/eSDHC/eMMC > diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c > index 56e6109288f7..b28c5457d67e 100644 > --- a/board/freescale/t102xrdb/eth_t102xrdb.c > +++ b/board/freescale/t102xrdb/eth_t102xrdb.c > @@ -64,7 +64,7 @@ int board_eth_init(struct bd_info *bis) > /* set the on-board RGMII2 PHY */ > fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); > > - /* set 10G XFI with Aquantia AQR105 PHY */ > + /* set 10GBase-R with Aquantia AQR105 PHY */ > fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); > break; > #endif > diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README > index d690857f2e28..b52d9610e981 100755 > --- a/board/freescale/t208xqds/README > +++ b/board/freescale/t208xqds/README > @@ -55,14 +55,14 @@ Memory: > - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support > Ethernet interfaces: > - Two 1Gbps RGMII on-board ports > - - Four 10Gbps XFI on-board cages > + - Four 10GBase-R on-board cages > - 1Gbps/2.5Gbps SGMII Riser card > - 10Gbps XAUI Riser card > Accelerator: > - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC > SerDes: > - 16 lanes up to 10.3125GHz > - - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI > + - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, 10GBase-R and XAUI > IFC: > - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA > eSPI: > @@ -85,14 +85,14 @@ System Logic: > - QIXIS-II FPGA system controll > Debug Features: > - Support Legacy, COP/JTAG, Aurora, Event and EVT > -XFI: > - - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to > +10GBase-R: > + - 10GBase-R is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to > a on-board SFP+ cages, which to house optical module (fiber cable) or > direct attach cable(copper), the copper cable is used to emulate > 10GBASE-KR scenario. > - So, for XFI usage, there are two scenarios, one will use fiber cable, > + So, for 10GBase-R usage, there are two scenarios, one will use fiber cable, > another will use copper cable. An hwconfig env "fsl_10gkr_copper" is > - introduced to indicate a XFI port will use copper cable, and U-Boot > + introduced to indicate a 10GBase-R port will use copper cable, and U-Boot > will fixup the dtb accordingly. > It's used as: fsl_10gkr_copper:<10g_mac_name> > The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they > @@ -100,10 +100,10 @@ XFI: > "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable > will be used by default. > for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in > - hwconfig, then both four XFI ports will use copper cable. > + hwconfig, then both four 10GBase-R ports will use copper cable. > set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two > - XFI ports will use copper cable, the other two XFI ports will use fiber > - cable. > + 10GBase-R ports will use copper cable, the other two 10GBase-R ports will use > + fiber cable. > 1000BASE-KX(1G-KX): > - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane > runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane > diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c > index 705387af3c31..2d7fc8bdda2e 100644 > --- a/board/freescale/t208xqds/eth_t208xqds.c > +++ b/board/freescale/t208xqds/eth_t208xqds.c > @@ -310,16 +310,16 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, > > } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { > switch (srds_s1) { > - case 0x66: /* XFI interface */ > + case 0x66: /* 10GBase-R interface */ > case 0x6b: > case 0x6c: > case 0x6d: > case 0x71: > /* > - * if the 10G is XFI, check hwconfig to see what is the > - * media type, there are two types, fiber or copper, > - * fix the dtb accordingly. > - */ > + * Check hwconfig to see what is the media type, there > + * are two types, fiber or copper, fix the dtb > + * accordingly. > + */ > switch (port) { > case FM1_10GEC1: > if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { > @@ -378,7 +378,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, > printf("Interface %d in backplane KR mode\n", > port); > } else { > - /* fixed-link for XFI fiber cable */ > + /* fixed-link for 10GBase-R fiber cable */ > f_link.phy_id = port; > f_link.duplex = 1; > f_link.link_speed = 10000; > @@ -538,12 +538,12 @@ int board_eth_init(struct bd_info *bis) > case 0x66: > case 0x67: > /* > - * XFI does not need a PHY to work, but to avoid U-Boot use > - * default PHY address which is zero to a MAC when it found > - * a MAC has no PHY address, we give a PHY address to XFI > + * 10GBase-R does not need a PHY to work, but to avoid U-Boot > + * use default PHY address which is zero to a MAC when it found > + * a MAC has no PHY address, we give a PHY address to 10GBase-R > * MAC, and should not use a real XAUI PHY address, since > * MDIO can access it successfully, and then MDIO thinks > - * the XAUI card is used for the XFI MAC, which will cause > + * the XAUI card is used for the 10GBase-R MAC, which will cause > * error. > */ > fm_info_set_phy_address(FM1_10GEC1, 4); > @@ -701,7 +701,7 @@ int board_eth_init(struct bd_info *bis) > (srds_s1 == 0x6a) || (srds_s1 == 0x70) || > (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || > (srds_s1 == 0x71)) { > - /* As XFI is in cage intead of a slot, so > + /* As 10GBase-R is in cage intead of a slot, so > * ensure doesn't disable the corresponding port > */ > break; > diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c > index 715de106d69b..e54672a80ba4 100644 > --- a/board/freescale/t208xqds/t208xqds.c > +++ b/board/freescale/t208xqds/t208xqds.c > @@ -136,14 +136,14 @@ int brd_mux_lane_to_slot(void) > break; > case 0x66: > case 0x67: > - /* SD1(A:D) => XFI cage > + /* SD1(A:D) => 10GBase-R cage > * SD1(E:H) => SLOT1 PCIe4 > */ > QIXIS_WRITE(brdcfg[12], 0xfe); > break; > case 0x6a: > case 0x6b: > - /* SD1(A:D) => XFI cage > + /* SD1(A:D) => 10GBase-R cage > * SD1(E) => SLOT1 PCIe4 > * SD1(F:H) => SLOT2 SGMII > */ > @@ -151,14 +151,14 @@ int brd_mux_lane_to_slot(void) > break; > case 0x6c: > case 0x6d: > - /* SD1(A:B) => XFI cage > + /* SD1(A:B) => 10GBase-R cage > * SD1(C:D) => SLOT3 SGMII > * SD1(E:H) => SLOT1 PCIe4 > */ > QIXIS_WRITE(brdcfg[12], 0xda); > break; > case 0x6e: > - /* SD1(A:B) => SFP Module, XFI > + /* SD1(A:B) => SFP Module, 10GBase-R > * SD1(C:D) => SLOT3 SGMII > * SD1(E:F) => SLOT1 PCIe4 x2 > * SD1(G:H) => SLOT2 SGMII > diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README > index ec47c96f2b1a..c4bfd3b466f4 100644 > --- a/board/freescale/t208xrdb/README > +++ b/board/freescale/t208xrdb/README > @@ -54,7 +54,7 @@ Differences between T2080 and T2081 > T2080PCIe-RDB board Overview > ---------------------------- > - SERDES Configuration > - - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10) > + - SerDes-1 Lane A-B: to two 10GBase-R fiber (MAC9 & MAC10) > - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) > - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) > - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) > @@ -62,7 +62,7 @@ T2080PCIe-RDB board Overview > - SerDes-2 Lane G-H: to SATA1 & SATA2 > - Ethernet > - Two on-board 10M/100M/1G RGMII ethernet ports > - - Two on-board 10Gbps XFI fiber ports > + - Two on-board 10GBase-R fiber ports > - Two on-board 10Gbps Base-T copper ports > - DDR Memory > - Supports 72bit 4GB DDR3-LP SODIMM > diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c > index c815a3a4fa52..34ffaa6aeb54 100644 > --- a/board/freescale/t4rdb/eth.c > +++ b/board/freescale/t4rdb/eth.c > @@ -106,7 +106,7 @@ int board_eth_init(struct bd_info *bis) > > #if (CONFIG_SYS_NUM_FMAN == 2) > if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) { > - /* SGMII && XFI */ > + /* SGMII && 10GBase-R */ > fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); > fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); > fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7); > diff --git a/doc/device-tree-bindings/net/ethernet.txt b/doc/device-tree-bindings/net/ethernet.txt > index cfc376bc977a..648a1aee694d 100644 > --- a/doc/device-tree-bindings/net/ethernet.txt > +++ b/doc/device-tree-bindings/net/ethernet.txt > @@ -41,7 +41,17 @@ Documentation/devicetree/bindings/phy/phy-bindings.txt. > * "2500base-x", > * "rxaui" > * "xaui" > - * "10gbase-kr" (10GBASE-KR, XFI, SFI) > + * "10gbase-r" (This is the IEEE 802.3 Clause 49 defined 10GBASE-R protocol > + used with various different mediums. Please refer to the IEEE standard for > + a definition of this. Note: 10GBASE-R is just one protocol that can be used > + with XFI and SFI. XFI and SFI permit multiple protocols over a single > + SERDES lane, and also defines the electrical characteristics of the signals > + with a host compliance board plugged into the host XFP/SFP connector. > + Therefore, XFI and SFI are not PHY interface types in their own right.) > + * "10gbase-kr" (This is the IEEE 802.3 Clause 49 defined 10GBASE-R with > + Clause 73 autonegotiation. Please refer to the IEEE standard for further > + information. Note: due to legacy usage, some 10GBASE-R usage incorrectly > + makes use of this definition). > - phy-connection-type: the same as "phy-mode" property but described in the > Devicetree Specification; > - phy-handle: phandle, specifies a reference to a node representing a PHY > diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c > index 5be0ad2ab3db..6e3d008199a5 100644 > --- a/drivers/net/fm/b4860.c > +++ b/drivers/net/fm/b4860.c > @@ -100,7 +100,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) > env_get_f("hwconfig", buffer, sizeof(buffer)); > buf = buffer; > > - /* check if XFI interface enable in hwconfig for 10g */ > + /* check if 10GBase-R interface enable in hwconfig for 10g */ > if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2", > "sfp_amc", "sfp", buf)) { > if ((port == FM1_10GEC1 || > diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c > index 36f50d27826e..e1f812b688b1 100644 > --- a/drivers/net/fm/memac.c > +++ b/drivers/net/fm/memac.c > @@ -98,7 +98,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, > if_mode &= ~IF_MODE_MASK; > if_mode |= (IF_MODE_GMII); > break; > - case PHY_INTERFACE_MODE_XFI: > + case PHY_INTERFACE_MODE_10GBASER: > case PHY_INTERFACE_MODE_XGMII: > if_mode &= ~IF_MODE_MASK; > if_mode |= IF_MODE_XGMII; > @@ -107,7 +107,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, > break; > } > /* Enable automatic speed selection for Non-XGMII */ > - if (type != PHY_INTERFACE_MODE_XGMII && type != PHY_INTERFACE_MODE_XFI) > + if (type != PHY_INTERFACE_MODE_XGMII && type != PHY_INTERFACE_MODE_10GBASER) > if_mode |= IF_MODE_EN_AUTO; > > if (type == PHY_INTERFACE_MODE_RGMII || > diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c > index 566cdc7e546a..12d9942b65d4 100644 > --- a/drivers/net/fsl_enetc.c > +++ b/drivers/net/fsl_enetc.c > @@ -228,7 +228,7 @@ static void enetc_setup_mac_iface(struct udevice *dev, > break; > case PHY_INTERFACE_MODE_XGMII: > case PHY_INTERFACE_MODE_USXGMII: > - case PHY_INTERFACE_MODE_XFI: > + case PHY_INTERFACE_MODE_10GBASER: > /* set ifmode to (US)XGMII */ > if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE); > if_mode &= ~ENETC_PM_IF_IFMODE_MASK; > @@ -296,7 +296,7 @@ static void enetc_start_pcs(struct udevice *dev) > break; > case PHY_INTERFACE_MODE_XGMII: > case PHY_INTERFACE_MODE_USXGMII: > - case PHY_INTERFACE_MODE_XFI: > + case PHY_INTERFACE_MODE_10GBASER: > enetc_init_sxgmii(dev); > break; > }; > diff --git a/drivers/net/mscc_eswitch/felix_switch.c b/drivers/net/mscc_eswitch/felix_switch.c > index 6aa79784460d..67b2879e8585 100644 > --- a/drivers/net/mscc_eswitch/felix_switch.c > +++ b/drivers/net/mscc_eswitch/felix_switch.c > @@ -223,7 +223,7 @@ static void felix_start_pcs(struct udevice *dev, int port, > felix_init_sgmii(imdio, port, autoneg); > break; > case PHY_INTERFACE_MODE_XGMII: > - case PHY_INTERFACE_MODE_XFI: > + case PHY_INTERFACE_MODE_10GBASER: > case PHY_INTERFACE_MODE_USXGMII: > if (felix_init_sxgmii(imdio, port)) > dev_err(dev, "PCS reset timeout on port %d\n", port); > diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c > index d3d35a75d065..66d1d9856825 100644 > --- a/drivers/net/phy/aquantia.c > +++ b/drivers/net/phy/aquantia.c > @@ -310,7 +310,7 @@ struct { > AQUANTIA_VND1_GSTART_RATE_1G}, > [PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G, > AQUANTIA_VND1_GSTART_RATE_2_5G}, > - [PHY_INTERFACE_MODE_XFI] = {0x100, AQUANTIA_VND1_GSYSCFG_10G, > + [PHY_INTERFACE_MODE_10GBASER] = {0x100, AQUANTIA_VND1_GSYSCFG_10G, > AQUANTIA_VND1_GSTART_RATE_10G}, > [PHY_INTERFACE_MODE_USXGMII] = {0x080, AQUANTIA_VND1_GSYSCFG_10G, > AQUANTIA_VND1_GSTART_RATE_10G}, > @@ -443,18 +443,18 @@ int aquantia_config(struct phy_device *phydev) > return ret; > } > /* > - * for backward compatibility convert XGMII into either XFI or USX based > - * on FW config > + * for backward compatibility convert XGMII into either 10GBase-R or > + * USXGMII based on FW config > */ > if (interface == PHY_INTERFACE_MODE_XGMII) { > - debug("use XFI or USXGMII SI protos, XGMII is not valid\n"); > + debug("use 10GBase-R or USXGMII SI protos, XGMII is not valid\n"); > > reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS, > AQUANTIA_SYSTEM_INTERFACE_SR); > if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII) > interface = PHY_INTERFACE_MODE_USXGMII; > else > - interface = PHY_INTERFACE_MODE_XFI; > + interface = PHY_INTERFACE_MODE_10GBASER; > } > > /* > @@ -494,7 +494,7 @@ int aquantia_config(struct phy_device *phydev) > case PHY_INTERFACE_MODE_USXGMII: > usx_an = 1; > /* FALLTHROUGH */ > - case PHY_INTERFACE_MODE_XFI: > + case PHY_INTERFACE_MODE_10GBASER: > /* 10GBASE-T mode */ > phydev->advertising = SUPPORTED_10000baseT_Full; > phydev->supported = phydev->advertising; > @@ -515,7 +515,7 @@ int aquantia_config(struct phy_device *phydev) > phydev->dev->name); > } else { > reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA; > - debug("%s: system interface XFI\n", > + debug("%s: system interface 10GBase-R\n", > phydev->dev->name); > } > > diff --git a/include/phy.h b/include/phy.h > index 6b928636b6d7..b9d8dc3a61ed 100644 > --- a/include/phy.h > +++ b/include/phy.h > @@ -368,7 +368,7 @@ static inline int is_10g_interface(phy_interface_t interface) > { > return interface == PHY_INTERFACE_MODE_XGMII || > interface == PHY_INTERFACE_MODE_USXGMII || > - interface == PHY_INTERFACE_MODE_XFI; > + interface == PHY_INTERFACE_MODE_10GBASER; > } > > #endif > diff --git a/include/phy_interface.h b/include/phy_interface.h > index ebb18ecd40c0..f075abe9c9c0 100644 > --- a/include/phy_interface.h > +++ b/include/phy_interface.h > @@ -37,7 +37,7 @@ typedef enum { > PHY_INTERFACE_MODE_CAUI2, > PHY_INTERFACE_MODE_CAUI4, > PHY_INTERFACE_MODE_NCSI, > - PHY_INTERFACE_MODE_XFI, > + PHY_INTERFACE_MODE_10GBASER, > PHY_INTERFACE_MODE_USXGMII, > PHY_INTERFACE_MODE_NONE, /* Must be last */ > > @@ -69,7 +69,7 @@ static const char * const phy_interface_strings[] = { > [PHY_INTERFACE_MODE_CAUI2] = "caui2", > [PHY_INTERFACE_MODE_CAUI4] = "caui4", > [PHY_INTERFACE_MODE_NCSI] = "NC-SI", > - [PHY_INTERFACE_MODE_XFI] = "xfi", > + [PHY_INTERFACE_MODE_10GBASER] = "10gbase-r", > [PHY_INTERFACE_MODE_USXGMII] = "usxgmii", > [PHY_INTERFACE_MODE_NONE] = "", > }; > -- > 2.25.1 > Reviewed-by: Ramon Fried <rfried.dev@gmail.com> ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/4] net: freescale: replace usage of phy-mode = "sgmii-2500" with "2500base-x" 2021-09-18 12:32 [PATCH 0/4] phy-mode cleanup Vladimir Oltean 2021-09-18 12:32 ` [PATCH 1/4] net: replace the "xfi" phy-mode with "10gbase-r" Vladimir Oltean @ 2021-09-18 12:32 ` Vladimir Oltean 2021-09-28 13:29 ` Ramon Fried 2021-09-18 12:32 ` [PATCH 3/4] net: enetc: remove support for "xgmii" phy-mode Vladimir Oltean 2021-09-18 12:32 ` [PATCH 4/4] net: dsa: felix: remove " Vladimir Oltean 3 siblings, 1 reply; 9+ messages in thread From: Vladimir Oltean @ 2021-09-18 12:32 UTC (permalink / raw) To: u-boot Cc: Joe Hershberger, Ramon Fried, Priyanka Jain, Madalin Bucur, Ioana Ciornei, Camelia Groza, Scott Wood, Pali Rohár, Marcin Wojtas, Stefan Chulski After the discussion here: https://lore.kernel.org/netdev/20210603143453.if7hgifupx5k433b@pali/ which resulted in this patch: https://patchwork.kernel.org/project/netdevbpf/patch/20210704134325.24842-1-pali@kernel.org/ and many other discussions before it, notably: https://patchwork.kernel.org/project/linux-arm-kernel/patch/1512016235-15909-1-git-send-email-Bhaskar.Upadhaya@nxp.com/ it became apparent that nobody really knows what "SGMII 2500" is. Certainly, Freescale/NXP hardware engineers name this protocol "SGMII 2500" in the reference manuals, but the PCS devices do not support any "SGMII" specific features when operating at the speed of 2500 Mbps, no in-band autoneg and no speed change via symbol replication . So that leaves a fixed speed of 2500 Mbps using a coding of 8b/10b with a SERDES lane frequency of 3.125 GHz. In fact, "SGMII 2500 without in-band autoneg and at a fixed speed" is indistinguishable from "2500base-x without in-band autoneg", which is precisely what these NXP devices support. So it just appears that "SGMII 2500" is an unclear name with no clear definition that stuck. As such, in the Linux kernel, the drivers which use this SERDES protocol use the 2500base-x phy-mode. This patch converts U-Boot to use 2500base-x too, or at least, as much as it can. Note that I would have really liked to delete PHY_INTERFACE_MODE_SGMII_2500 completely, but the mvpp2 driver seems to even distinguish between SGMII 2500 and 2500base-X. Namely, it enables in-band autoneg for one but not the other, and forces flow control for one but not the other. This goes back to the idea that maybe 2500base-X is a fiber protocol and SGMII-2500 is an MII protocol (connects a MAC to a PHY such as Aquantia), but the two are practically indistinguishable through everything except use case. NXP devices can support both use cases through an identical configuration, for example RX flow control can be unconditionally enabled in order to support rate adaptation performed by an Aquantia PHY. At least I can find no indication in online documents published by Cisco which would point towards "SGMII-2500" being an actual standard with an actual definition, so I cannot say "yes, NXP devices support it". Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> --- arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi | 2 +- arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi | 8 ++++---- arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi | 4 ++-- arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi | 2 +- arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi | 2 +- arch/arm/dts/fsl-sch-30841.dtsi | 2 +- arch/arm/dts/fsl-sch-30842.dtsi | 2 +- board/freescale/ls1012aqds/eth.c | 4 ++-- board/freescale/ls1012aqds/ls1012aqds.c | 4 ++-- board/freescale/ls1012aqds/ls1012aqds_pfe.h | 2 +- board/freescale/ls1012ardb/eth.c | 4 ++-- board/freescale/ls1043aqds/eth.c | 8 ++++---- board/freescale/ls1046aqds/eth.c | 4 ++-- board/freescale/t102xrdb/eth_t102xrdb.c | 6 +++--- drivers/net/fm/eth.c | 10 +++++----- drivers/net/fm/ls1043.c | 4 ++-- drivers/net/fm/ls1046.c | 2 +- drivers/net/fm/memac.c | 2 +- drivers/net/fm/t1024.c | 2 +- drivers/net/fsl_enetc.c | 4 ++-- drivers/net/mscc_eswitch/felix_switch.c | 4 ++-- drivers/net/pfe_eth/pfe_mdio.c | 4 ++-- drivers/net/phy/aquantia.c | 4 ++-- 23 files changed, 45 insertions(+), 45 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi index c6558ae2e07b..96c9455e6d39 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi @@ -14,6 +14,6 @@ &enetc0 { status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi index 5a0f060c16e5..006e382991f2 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi @@ -30,25 +30,25 @@ &mscc_felix_port0 { status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>; }; &mscc_felix_port1 { status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>; }; &mscc_felix_port2 { status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; }; &mscc_felix_port3 { status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi index 39a83e10c4ce..55eea63808bb 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi @@ -19,13 +19,13 @@ &mscc_felix_port0 { status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; }; &mscc_felix_port3 { status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi index 1fb2cdf0c244..3bac45625341 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi @@ -19,7 +19,7 @@ &mscc_felix_port1 { status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi index 2333f74e5ae1..e5a35ba719bf 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi @@ -19,7 +19,7 @@ &mscc_felix_port2 { status = "okay"; - phy-mode = "sgmii-2500"; + phy-mode = "2500base-x"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>; }; diff --git a/arch/arm/dts/fsl-sch-30841.dtsi b/arch/arm/dts/fsl-sch-30841.dtsi index 0a723c21b8f8..cc6391d37081 100644 --- a/arch/arm/dts/fsl-sch-30841.dtsi +++ b/arch/arm/dts/fsl-sch-30841.dtsi @@ -9,7 +9,7 @@ * SCH-30841 is a 4 port add-on card used with various FSL QDS boards. * It integrates a AQR412C quad PHY which supports 4 interfaces either muxed * together on a single lane or mapped 1:1 to serdes lanes. - * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, 10GBase-R. + * It supports several protocols - SGMII, 2500base-X, USXGMII, M-USX, 10GBase-R. * PHY addresses are 0x00 - 0x03. * On the card the first port is the bottom port (closest to PEX connector). */ diff --git a/arch/arm/dts/fsl-sch-30842.dtsi b/arch/arm/dts/fsl-sch-30842.dtsi index b64aeb3fcce6..d5c7a2f94f87 100644 --- a/arch/arm/dts/fsl-sch-30842.dtsi +++ b/arch/arm/dts/fsl-sch-30842.dtsi @@ -8,7 +8,7 @@ /* * SCH-30842 is a single port add-on card used with various FSL QDS boards. * It integrates a AQR112 PHY, which supports several protocols - SGMII, - * SGMII-2500, USXGMII, 10GBase-R. + * 2500base-x, USXGMII, 10GBase-R. * PHY address is 0x02. */ phy@02 { diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c index 8189f41becb3..27f69abf6091 100644 --- a/board/freescale/ls1012aqds/eth.c +++ b/board/freescale/ls1012aqds/eth.c @@ -244,7 +244,7 @@ int pfe_eth_board_init(struct udevice *dev) bus = miiphy_get_dev_by_name(mdio_name); pfe_set_mdio(1, bus); pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR, - PHY_INTERFACE_MODE_SGMII_2500); + PHY_INTERFACE_MODE_2500BASEX); data8 = QIXIS_READ(brdcfg[12]); data8 |= 0x20; @@ -263,7 +263,7 @@ int pfe_eth_board_init(struct udevice *dev) pfe_set_mdio(0, bus); pfe_set_phy_address_mode(0, CONFIG_PFE_SGMII_2500_PHY1_ADDR, - PHY_INTERFACE_MODE_SGMII_2500); + PHY_INTERFACE_MODE_2500BASEX); } break; diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 33a0910a198a..6e21040601d2 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -265,7 +265,7 @@ static void fdt_fsl_fixup_of_pfe(void *blob) ETH_1_2_5G_MDIO_MUX); prop_val.phy_mask = cpu_to_fdt32( ETH_2_5G_MDIO_PHY_MASK); - prop_val.phy_mode = "sgmii-2500"; + prop_val.phy_mode = "2500base-x"; pfe_set_properties(l_blob, prop_val, ETH_1_PATH, ETH_1_MDIO); } else { @@ -277,7 +277,7 @@ static void fdt_fsl_fixup_of_pfe(void *blob) ETH_2_2_5G_MDIO_MUX); prop_val.phy_mask = cpu_to_fdt32( ETH_2_5G_MDIO_PHY_MASK); - prop_val.phy_mode = "sgmii-2500"; + prop_val.phy_mode = "2500base-x"; pfe_set_properties(l_blob, prop_val, ETH_2_PATH, ETH_2_MDIO); } diff --git a/board/freescale/ls1012aqds/ls1012aqds_pfe.h b/board/freescale/ls1012aqds/ls1012aqds_pfe.h index 05ccb71aa069..5ab283ce8d56 100644 --- a/board/freescale/ls1012aqds/ls1012aqds_pfe.h +++ b/board/freescale/ls1012aqds/ls1012aqds_pfe.h @@ -17,7 +17,7 @@ #define ETH_1_2_5G_PHY_ID 0x1 #define ETH_1_2_5G_MDIO_MUX 0x2 #define ETH_2_5G_MDIO_PHY_MASK 0xFFFFFFF9 -#define ETH_2_5G_PHY_MODE "sgmii-2500" +#define ETH_2_5G_PHY_MODE "2500base-x" #define ETH_2_2_5G_BUS_ID 0x1 #define ETH_2_2_5G_PHY_ID 0x2 #define ETH_2_2_5G_MDIO_MUX 0x3 diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c index bb3fbc71ef65..565f80059656 100644 --- a/board/freescale/ls1012ardb/eth.c +++ b/board/freescale/ls1012ardb/eth.c @@ -121,12 +121,12 @@ int pfe_eth_board_init(struct udevice *dev) /* MAC1 */ pfe_set_phy_address_mode(priv->gemac_port, CONFIG_PFE_EMAC1_PHY_ADDR, - PHY_INTERFACE_MODE_SGMII_2500); + PHY_INTERFACE_MODE_2500BASEX); } else { /* MAC2 */ pfe_set_phy_address_mode(priv->gemac_port, CONFIG_PFE_EMAC2_PHY_ADDR, - PHY_INTERFACE_MODE_SGMII_2500); + PHY_INTERFACE_MODE_2500BASEX); } break; default: diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index 81e18f6e82b5..e156ba010451 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -176,7 +176,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, "sgmii-riser-s4-p1"); } } else if (fm_info_get_enet_if(port) == - PHY_INTERFACE_MODE_SGMII_2500) { + PHY_INTERFACE_MODE_2500BASEX) { /* 2.5G SGMII interface */ f_link.phy_id = cpu_to_fdt32(port); f_link.duplex = cpu_to_fdt32(1); @@ -187,7 +187,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_delprop(fdt, offset, "phy-handle"); fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); fdt_setprop_string(fdt, offset, "phy-connection-type", - "sgmii-2500"); + "2500base-x"); } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { switch (mdio_mux[port]) { case EMI1_SLOT1: @@ -430,12 +430,12 @@ int board_eth_init(struct bd_info *bis) interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_2500BASEX: case PHY_INTERFACE_MODE_QSGMII: if (interface == PHY_INTERFACE_MODE_SGMII) { lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 + idx); - } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) { + } else if (interface == PHY_INTERFACE_MODE_2500BASEX) { lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_2500_FM1_DTSEC1 + idx); } else { diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index 23528324662e..8233f5461ee3 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -178,7 +178,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, default: break; } - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) { + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) { /* 2.5G SGMII interface */ f_link.phy_id = cpu_to_fdt32(port); f_link.duplex = cpu_to_fdt32(1); @@ -189,7 +189,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_delprop(fdt, offset, "phy-handle"); fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); fdt_setprop_string(fdt, offset, "phy-connection-type", - "sgmii-2500"); + "2500base-x"); } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { switch (port) { case FM1_DTSEC1: diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index b28c5457d67e..4f04d2ee06d6 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -103,7 +103,7 @@ int board_eth_init(struct bd_info *bis) #endif fm_info_set_mdio(i, dev); break; - case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_2500BASEX: dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); fm_info_set_mdio(i, dev); break; @@ -133,12 +133,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, enum fm_port port, int offset) { #if defined(CONFIG_TARGET_T1024RDB) - if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) || + if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) || (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) && (port == FM1_DTSEC3)) { fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4"); fdt_setprop_string(fdt, offset, "phy-connection-type", - "sgmii-2500"); + "2500base-x"); fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3"); } #endif diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 7c23ccc1f0e6..5e0d0bca9b53 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -50,7 +50,7 @@ static void dtsec_configure_serdes(struct fm_eth *priv) u32 value; struct mii_dev bus; bool sgmii_2500 = (priv->enet_if == - PHY_INTERFACE_MODE_SGMII_2500) ? true : false; + PHY_INTERFACE_MODE_2500BASEX) ? true : false; int i = 0, j; #ifndef CONFIG_DM_ETH @@ -133,7 +133,7 @@ static void dtsec_init_phy(struct fm_eth *fm_eth) if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII || fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII || - fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) + fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX) dtsec_configure_serdes(fm_eth); } @@ -432,7 +432,7 @@ static int fm_eth_startup(struct fm_eth *fm_eth) /* For some reason we need to set SPEED_100 */ if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) || - (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) || + (fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX) || (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) && mac->set_if_mode) mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100); @@ -829,7 +829,7 @@ static int init_phy(struct fm_eth *fm_eth) if (fm_eth->type == FM_ETH_10G_E) supported = PHY_10G_FEATURES; - if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) + if (fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX) supported |= SUPPORTED_2500baseX_Full; #endif @@ -1090,7 +1090,7 @@ static int fm_eth_probe(struct udevice *dev) if (fm_eth->num != 0) break; case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_2500BASEX: fm_eth->pcs_mdio = fm_get_internal_mdio(dev); break; default: diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c index ba4da69423aa..e1abf8f6bb71 100644 --- a/drivers/net/fm/ls1043.c +++ b/drivers/net/fm/ls1043.c @@ -79,7 +79,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) case FM1_DTSEC2: if ((port == FM1_DTSEC2) && is_serdes_configured(SGMII_2500_FM1_DTSEC2)) - return PHY_INTERFACE_MODE_SGMII_2500; + return PHY_INTERFACE_MODE_2500BASEX; case FM1_DTSEC5: case FM1_DTSEC6: case FM1_DTSEC9: @@ -87,7 +87,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) return PHY_INTERFACE_MODE_SGMII; else if ((port == FM1_DTSEC9) && is_serdes_configured(SGMII_2500_FM1_DTSEC9)) - return PHY_INTERFACE_MODE_SGMII_2500; + return PHY_INTERFACE_MODE_2500BASEX; break; default: break; diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c index 49b540bd30b0..09df0aa53766 100644 --- a/drivers/net/fm/ls1046.c +++ b/drivers/net/fm/ls1046.c @@ -99,7 +99,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) case FM1_DTSEC10: if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 + port - FM1_DTSEC5)) - return PHY_INTERFACE_MODE_SGMII_2500; + return PHY_INTERFACE_MODE_2500BASEX; break; default: break; diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c index e1f812b688b1..eeb67a39a77f 100644 --- a/drivers/net/fm/memac.c +++ b/drivers/net/fm/memac.c @@ -93,7 +93,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, if_mode |= (IF_MODE_GMII | IF_MODE_RM); break; case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_2500BASEX: case PHY_INTERFACE_MODE_QSGMII: if_mode &= ~IF_MODE_MASK; if_mode |= (IF_MODE_GMII); diff --git a/drivers/net/fm/t1024.c b/drivers/net/fm/t1024.c index 6fc3b9033701..696e74c9e6fe 100644 --- a/drivers/net/fm/t1024.c +++ b/drivers/net/fm/t1024.c @@ -63,7 +63,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) return PHY_INTERFACE_MODE_SGMII; else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1 + port - FM1_DTSEC1)) - return PHY_INTERFACE_MODE_SGMII_2500; + return PHY_INTERFACE_MODE_2500BASEX; break; default: break; diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index 12d9942b65d4..045527dcf7d9 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -144,7 +144,7 @@ static int enetc_init_sgmii(struct udevice *dev) if (!enetc_has_imdio(dev)) return 0; - if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500) + if (priv->if_type == PHY_INTERFACE_MODE_2500BASEX) is2500 = true; /* @@ -291,7 +291,7 @@ static void enetc_start_pcs(struct udevice *dev) switch (priv->if_type) { case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_2500BASEX: enetc_init_sgmii(dev); break; case PHY_INTERFACE_MODE_XGMII: diff --git a/drivers/net/mscc_eswitch/felix_switch.c b/drivers/net/mscc_eswitch/felix_switch.c index 67b2879e8585..bd40c3b8b1bb 100644 --- a/drivers/net/mscc_eswitch/felix_switch.c +++ b/drivers/net/mscc_eswitch/felix_switch.c @@ -213,12 +213,12 @@ static void felix_start_pcs(struct udevice *dev, int port, bool autoneg = true; if (phy->phy_id == PHY_FIXED_ID || - phy->interface == PHY_INTERFACE_MODE_SGMII_2500) + phy->interface == PHY_INTERFACE_MODE_2500BASEX) autoneg = false; switch (phy->interface) { case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_2500BASEX: case PHY_INTERFACE_MODE_QSGMII: felix_init_sgmii(imdio, port, autoneg); break; diff --git a/drivers/net/pfe_eth/pfe_mdio.c b/drivers/net/pfe_eth/pfe_mdio.c index 3228b8df49d4..ae5b6fc2800a 100644 --- a/drivers/net/pfe_eth/pfe_mdio.c +++ b/drivers/net/pfe_eth/pfe_mdio.c @@ -161,7 +161,7 @@ static void pfe_configure_serdes(struct pfe_eth_dev *priv) int value, sgmii_2500 = 0; struct gemac_s *gem = priv->gem; - if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) + if (gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX) sgmii_2500 = 1; @@ -220,7 +220,7 @@ int pfe_phy_configure(struct pfe_eth_dev *priv, int dev_id, int phy_id) /* Configure SGMII PCS */ if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII || - gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) { + gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX) { out_be32(&scfg->mdioselcr, 0x00000000); pfe_configure_serdes(priv); } diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index 66d1d9856825..83075f78c981 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -308,7 +308,7 @@ struct { } aquantia_syscfg[PHY_INTERFACE_MODE_COUNT] = { [PHY_INTERFACE_MODE_SGMII] = {0x04b, AQUANTIA_VND1_GSYSCFG_1G, AQUANTIA_VND1_GSTART_RATE_1G}, - [PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G, + [PHY_INTERFACE_MODE_2500BASEX] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G, AQUANTIA_VND1_GSTART_RATE_2_5G}, [PHY_INTERFACE_MODE_10GBASER] = {0x100, AQUANTIA_VND1_GSYSCFG_10G, AQUANTIA_VND1_GSTART_RATE_10G}, @@ -522,7 +522,7 @@ int aquantia_config(struct phy_device *phydev) phy_write(phydev, MDIO_MMD_PHYXS, AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1); break; - case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_2500BASEX: /* 2.5GBASE-T mode */ phydev->advertising = SUPPORTED_1000baseT_Full; phydev->supported = phydev->advertising; -- 2.25.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/4] net: freescale: replace usage of phy-mode = "sgmii-2500" with "2500base-x" 2021-09-18 12:32 ` [PATCH 2/4] net: freescale: replace usage of phy-mode = "sgmii-2500" with "2500base-x" Vladimir Oltean @ 2021-09-28 13:29 ` Ramon Fried 0 siblings, 0 replies; 9+ messages in thread From: Ramon Fried @ 2021-09-28 13:29 UTC (permalink / raw) To: Vladimir Oltean Cc: U-Boot Mailing List, Joe Hershberger, Priyanka Jain, Madalin Bucur, Ioana Ciornei, Camelia Groza, Scott Wood, Pali Rohár, Marcin Wojtas, Stefan Chulski On Sat, Sep 18, 2021 at 3:34 PM Vladimir Oltean <vladimir.oltean@nxp.com> wrote: > > After the discussion here: > https://lore.kernel.org/netdev/20210603143453.if7hgifupx5k433b@pali/ > > which resulted in this patch: > https://patchwork.kernel.org/project/netdevbpf/patch/20210704134325.24842-1-pali@kernel.org/ > > and many other discussions before it, notably: > https://patchwork.kernel.org/project/linux-arm-kernel/patch/1512016235-15909-1-git-send-email-Bhaskar.Upadhaya@nxp.com/ > > it became apparent that nobody really knows what "SGMII 2500" is. > Certainly, Freescale/NXP hardware engineers name this protocol > "SGMII 2500" in the reference manuals, but the PCS devices do not > support any "SGMII" specific features when operating at the speed of > 2500 Mbps, no in-band autoneg and no speed change via symbol replication > . So that leaves a fixed speed of 2500 Mbps using a coding of 8b/10b > with a SERDES lane frequency of 3.125 GHz. In fact, "SGMII 2500 without > in-band autoneg and at a fixed speed" is indistinguishable from > "2500base-x without in-band autoneg", which is precisely what these NXP > devices support. > > So it just appears that "SGMII 2500" is an unclear name with no clear > definition that stuck. > > As such, in the Linux kernel, the drivers which use this SERDES protocol > use the 2500base-x phy-mode. > > This patch converts U-Boot to use 2500base-x too, or at least, as much > as it can. > > Note that I would have really liked to delete PHY_INTERFACE_MODE_SGMII_2500 > completely, but the mvpp2 driver seems to even distinguish between SGMII > 2500 and 2500base-X. Namely, it enables in-band autoneg for one but not > the other, and forces flow control for one but not the other. This goes > back to the idea that maybe 2500base-X is a fiber protocol and SGMII-2500 > is an MII protocol (connects a MAC to a PHY such as Aquantia), but the > two are practically indistinguishable through everything except use case. > > NXP devices can support both use cases through an identical configuration, > for example RX flow control can be unconditionally enabled in order to > support rate adaptation performed by an Aquantia PHY. At least I can > find no indication in online documents published by Cisco which would > point towards "SGMII-2500" being an actual standard with an actual > definition, so I cannot say "yes, NXP devices support it". > > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> > --- > arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi | 2 +- > arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi | 8 ++++---- > arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi | 4 ++-- > arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi | 2 +- > arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi | 2 +- > arch/arm/dts/fsl-sch-30841.dtsi | 2 +- > arch/arm/dts/fsl-sch-30842.dtsi | 2 +- > board/freescale/ls1012aqds/eth.c | 4 ++-- > board/freescale/ls1012aqds/ls1012aqds.c | 4 ++-- > board/freescale/ls1012aqds/ls1012aqds_pfe.h | 2 +- > board/freescale/ls1012ardb/eth.c | 4 ++-- > board/freescale/ls1043aqds/eth.c | 8 ++++---- > board/freescale/ls1046aqds/eth.c | 4 ++-- > board/freescale/t102xrdb/eth_t102xrdb.c | 6 +++--- > drivers/net/fm/eth.c | 10 +++++----- > drivers/net/fm/ls1043.c | 4 ++-- > drivers/net/fm/ls1046.c | 2 +- > drivers/net/fm/memac.c | 2 +- > drivers/net/fm/t1024.c | 2 +- > drivers/net/fsl_enetc.c | 4 ++-- > drivers/net/mscc_eswitch/felix_switch.c | 4 ++-- > drivers/net/pfe_eth/pfe_mdio.c | 4 ++-- > drivers/net/phy/aquantia.c | 4 ++-- > 23 files changed, 45 insertions(+), 45 deletions(-) > > diff --git a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi > index c6558ae2e07b..96c9455e6d39 100644 > --- a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi > +++ b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi > @@ -14,6 +14,6 @@ > > &enetc0 { > status = "okay"; > - phy-mode = "sgmii-2500"; > + phy-mode = "2500base-x"; > phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; > }; > diff --git a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi > index 5a0f060c16e5..006e382991f2 100644 > --- a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi > +++ b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi > @@ -30,25 +30,25 @@ > > &mscc_felix_port0 { > status = "okay"; > - phy-mode = "sgmii-2500"; > + phy-mode = "2500base-x"; > phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>; > }; > > &mscc_felix_port1 { > status = "okay"; > - phy-mode = "sgmii-2500"; > + phy-mode = "2500base-x"; > phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>; > }; > > &mscc_felix_port2 { > status = "okay"; > - phy-mode = "sgmii-2500"; > + phy-mode = "2500base-x"; > phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; > }; > > &mscc_felix_port3 { > status = "okay"; > - phy-mode = "sgmii-2500"; > + phy-mode = "2500base-x"; > phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; > }; > > diff --git a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi > index 39a83e10c4ce..55eea63808bb 100644 > --- a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi > +++ b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi > @@ -19,13 +19,13 @@ > > &mscc_felix_port0 { > status = "okay"; > - phy-mode = "sgmii-2500"; > + phy-mode = "2500base-x"; > phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; > }; > > &mscc_felix_port3 { > status = "okay"; > - phy-mode = "sgmii-2500"; > + phy-mode = "2500base-x"; > phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; > }; > > diff --git a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi > index 1fb2cdf0c244..3bac45625341 100644 > --- a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi > +++ b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi > @@ -19,7 +19,7 @@ > > &mscc_felix_port1 { > status = "okay"; > - phy-mode = "sgmii-2500"; > + phy-mode = "2500base-x"; > phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>; > }; > > diff --git a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi > index 2333f74e5ae1..e5a35ba719bf 100644 > --- a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi > +++ b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi > @@ -19,7 +19,7 @@ > > &mscc_felix_port2 { > status = "okay"; > - phy-mode = "sgmii-2500"; > + phy-mode = "2500base-x"; > phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>; > }; > > diff --git a/arch/arm/dts/fsl-sch-30841.dtsi b/arch/arm/dts/fsl-sch-30841.dtsi > index 0a723c21b8f8..cc6391d37081 100644 > --- a/arch/arm/dts/fsl-sch-30841.dtsi > +++ b/arch/arm/dts/fsl-sch-30841.dtsi > @@ -9,7 +9,7 @@ > * SCH-30841 is a 4 port add-on card used with various FSL QDS boards. > * It integrates a AQR412C quad PHY which supports 4 interfaces either muxed > * together on a single lane or mapped 1:1 to serdes lanes. > - * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, 10GBase-R. > + * It supports several protocols - SGMII, 2500base-X, USXGMII, M-USX, 10GBase-R. > * PHY addresses are 0x00 - 0x03. > * On the card the first port is the bottom port (closest to PEX connector). > */ > diff --git a/arch/arm/dts/fsl-sch-30842.dtsi b/arch/arm/dts/fsl-sch-30842.dtsi > index b64aeb3fcce6..d5c7a2f94f87 100644 > --- a/arch/arm/dts/fsl-sch-30842.dtsi > +++ b/arch/arm/dts/fsl-sch-30842.dtsi > @@ -8,7 +8,7 @@ > /* > * SCH-30842 is a single port add-on card used with various FSL QDS boards. > * It integrates a AQR112 PHY, which supports several protocols - SGMII, > - * SGMII-2500, USXGMII, 10GBase-R. > + * 2500base-x, USXGMII, 10GBase-R. > * PHY address is 0x02. > */ > phy@02 { > diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c > index 8189f41becb3..27f69abf6091 100644 > --- a/board/freescale/ls1012aqds/eth.c > +++ b/board/freescale/ls1012aqds/eth.c > @@ -244,7 +244,7 @@ int pfe_eth_board_init(struct udevice *dev) > bus = miiphy_get_dev_by_name(mdio_name); > pfe_set_mdio(1, bus); > pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR, > - PHY_INTERFACE_MODE_SGMII_2500); > + PHY_INTERFACE_MODE_2500BASEX); > > data8 = QIXIS_READ(brdcfg[12]); > data8 |= 0x20; > @@ -263,7 +263,7 @@ int pfe_eth_board_init(struct udevice *dev) > pfe_set_mdio(0, bus); > pfe_set_phy_address_mode(0, > CONFIG_PFE_SGMII_2500_PHY1_ADDR, > - PHY_INTERFACE_MODE_SGMII_2500); > + PHY_INTERFACE_MODE_2500BASEX); > } > break; > > diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c > index 33a0910a198a..6e21040601d2 100644 > --- a/board/freescale/ls1012aqds/ls1012aqds.c > +++ b/board/freescale/ls1012aqds/ls1012aqds.c > @@ -265,7 +265,7 @@ static void fdt_fsl_fixup_of_pfe(void *blob) > ETH_1_2_5G_MDIO_MUX); > prop_val.phy_mask = cpu_to_fdt32( > ETH_2_5G_MDIO_PHY_MASK); > - prop_val.phy_mode = "sgmii-2500"; > + prop_val.phy_mode = "2500base-x"; > pfe_set_properties(l_blob, prop_val, ETH_1_PATH, > ETH_1_MDIO); > } else { > @@ -277,7 +277,7 @@ static void fdt_fsl_fixup_of_pfe(void *blob) > ETH_2_2_5G_MDIO_MUX); > prop_val.phy_mask = cpu_to_fdt32( > ETH_2_5G_MDIO_PHY_MASK); > - prop_val.phy_mode = "sgmii-2500"; > + prop_val.phy_mode = "2500base-x"; > pfe_set_properties(l_blob, prop_val, ETH_2_PATH, > ETH_2_MDIO); > } > diff --git a/board/freescale/ls1012aqds/ls1012aqds_pfe.h b/board/freescale/ls1012aqds/ls1012aqds_pfe.h > index 05ccb71aa069..5ab283ce8d56 100644 > --- a/board/freescale/ls1012aqds/ls1012aqds_pfe.h > +++ b/board/freescale/ls1012aqds/ls1012aqds_pfe.h > @@ -17,7 +17,7 @@ > #define ETH_1_2_5G_PHY_ID 0x1 > #define ETH_1_2_5G_MDIO_MUX 0x2 > #define ETH_2_5G_MDIO_PHY_MASK 0xFFFFFFF9 > -#define ETH_2_5G_PHY_MODE "sgmii-2500" > +#define ETH_2_5G_PHY_MODE "2500base-x" > #define ETH_2_2_5G_BUS_ID 0x1 > #define ETH_2_2_5G_PHY_ID 0x2 > #define ETH_2_2_5G_MDIO_MUX 0x3 > diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c > index bb3fbc71ef65..565f80059656 100644 > --- a/board/freescale/ls1012ardb/eth.c > +++ b/board/freescale/ls1012ardb/eth.c > @@ -121,12 +121,12 @@ int pfe_eth_board_init(struct udevice *dev) > /* MAC1 */ > pfe_set_phy_address_mode(priv->gemac_port, > CONFIG_PFE_EMAC1_PHY_ADDR, > - PHY_INTERFACE_MODE_SGMII_2500); > + PHY_INTERFACE_MODE_2500BASEX); > } else { > /* MAC2 */ > pfe_set_phy_address_mode(priv->gemac_port, > CONFIG_PFE_EMAC2_PHY_ADDR, > - PHY_INTERFACE_MODE_SGMII_2500); > + PHY_INTERFACE_MODE_2500BASEX); > } > break; > default: > diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c > index 81e18f6e82b5..e156ba010451 100644 > --- a/board/freescale/ls1043aqds/eth.c > +++ b/board/freescale/ls1043aqds/eth.c > @@ -176,7 +176,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, > "sgmii-riser-s4-p1"); > } > } else if (fm_info_get_enet_if(port) == > - PHY_INTERFACE_MODE_SGMII_2500) { > + PHY_INTERFACE_MODE_2500BASEX) { > /* 2.5G SGMII interface */ > f_link.phy_id = cpu_to_fdt32(port); > f_link.duplex = cpu_to_fdt32(1); > @@ -187,7 +187,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, > fdt_delprop(fdt, offset, "phy-handle"); > fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); > fdt_setprop_string(fdt, offset, "phy-connection-type", > - "sgmii-2500"); > + "2500base-x"); > } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { > switch (mdio_mux[port]) { > case EMI1_SLOT1: > @@ -430,12 +430,12 @@ int board_eth_init(struct bd_info *bis) > interface = fm_info_get_enet_if(i); > switch (interface) { > case PHY_INTERFACE_MODE_SGMII: > - case PHY_INTERFACE_MODE_SGMII_2500: > + case PHY_INTERFACE_MODE_2500BASEX: > case PHY_INTERFACE_MODE_QSGMII: > if (interface == PHY_INTERFACE_MODE_SGMII) { > lane = serdes_get_first_lane(FSL_SRDS_1, > SGMII_FM1_DTSEC1 + idx); > - } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) { > + } else if (interface == PHY_INTERFACE_MODE_2500BASEX) { > lane = serdes_get_first_lane(FSL_SRDS_1, > SGMII_2500_FM1_DTSEC1 + idx); > } else { > diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c > index 23528324662e..8233f5461ee3 100644 > --- a/board/freescale/ls1046aqds/eth.c > +++ b/board/freescale/ls1046aqds/eth.c > @@ -178,7 +178,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, > default: > break; > } > - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) { > + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) { > /* 2.5G SGMII interface */ > f_link.phy_id = cpu_to_fdt32(port); > f_link.duplex = cpu_to_fdt32(1); > @@ -189,7 +189,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, > fdt_delprop(fdt, offset, "phy-handle"); > fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); > fdt_setprop_string(fdt, offset, "phy-connection-type", > - "sgmii-2500"); > + "2500base-x"); > } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { > switch (port) { > case FM1_DTSEC1: > diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c > index b28c5457d67e..4f04d2ee06d6 100644 > --- a/board/freescale/t102xrdb/eth_t102xrdb.c > +++ b/board/freescale/t102xrdb/eth_t102xrdb.c > @@ -103,7 +103,7 @@ int board_eth_init(struct bd_info *bis) > #endif > fm_info_set_mdio(i, dev); > break; > - case PHY_INTERFACE_MODE_SGMII_2500: > + case PHY_INTERFACE_MODE_2500BASEX: > dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); > fm_info_set_mdio(i, dev); > break; > @@ -133,12 +133,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, > enum fm_port port, int offset) > { > #if defined(CONFIG_TARGET_T1024RDB) > - if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) || > + if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) || > (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) && > (port == FM1_DTSEC3)) { > fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4"); > fdt_setprop_string(fdt, offset, "phy-connection-type", > - "sgmii-2500"); > + "2500base-x"); > fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3"); > } > #endif > diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c > index 7c23ccc1f0e6..5e0d0bca9b53 100644 > --- a/drivers/net/fm/eth.c > +++ b/drivers/net/fm/eth.c > @@ -50,7 +50,7 @@ static void dtsec_configure_serdes(struct fm_eth *priv) > u32 value; > struct mii_dev bus; > bool sgmii_2500 = (priv->enet_if == > - PHY_INTERFACE_MODE_SGMII_2500) ? true : false; > + PHY_INTERFACE_MODE_2500BASEX) ? true : false; > int i = 0, j; > > #ifndef CONFIG_DM_ETH > @@ -133,7 +133,7 @@ static void dtsec_init_phy(struct fm_eth *fm_eth) > > if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII || > fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII || > - fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) > + fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX) > dtsec_configure_serdes(fm_eth); > } > > @@ -432,7 +432,7 @@ static int fm_eth_startup(struct fm_eth *fm_eth) > > /* For some reason we need to set SPEED_100 */ > if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) || > - (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) || > + (fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX) || > (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) && > mac->set_if_mode) > mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100); > @@ -829,7 +829,7 @@ static int init_phy(struct fm_eth *fm_eth) > > if (fm_eth->type == FM_ETH_10G_E) > supported = PHY_10G_FEATURES; > - if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) > + if (fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX) > supported |= SUPPORTED_2500baseX_Full; > #endif > > @@ -1090,7 +1090,7 @@ static int fm_eth_probe(struct udevice *dev) > if (fm_eth->num != 0) > break; > case PHY_INTERFACE_MODE_SGMII: > - case PHY_INTERFACE_MODE_SGMII_2500: > + case PHY_INTERFACE_MODE_2500BASEX: > fm_eth->pcs_mdio = fm_get_internal_mdio(dev); > break; > default: > diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c > index ba4da69423aa..e1abf8f6bb71 100644 > --- a/drivers/net/fm/ls1043.c > +++ b/drivers/net/fm/ls1043.c > @@ -79,7 +79,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) > case FM1_DTSEC2: > if ((port == FM1_DTSEC2) && > is_serdes_configured(SGMII_2500_FM1_DTSEC2)) > - return PHY_INTERFACE_MODE_SGMII_2500; > + return PHY_INTERFACE_MODE_2500BASEX; > case FM1_DTSEC5: > case FM1_DTSEC6: > case FM1_DTSEC9: > @@ -87,7 +87,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) > return PHY_INTERFACE_MODE_SGMII; > else if ((port == FM1_DTSEC9) && > is_serdes_configured(SGMII_2500_FM1_DTSEC9)) > - return PHY_INTERFACE_MODE_SGMII_2500; > + return PHY_INTERFACE_MODE_2500BASEX; > break; > default: > break; > diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c > index 49b540bd30b0..09df0aa53766 100644 > --- a/drivers/net/fm/ls1046.c > +++ b/drivers/net/fm/ls1046.c > @@ -99,7 +99,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) > case FM1_DTSEC10: > if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 + > port - FM1_DTSEC5)) > - return PHY_INTERFACE_MODE_SGMII_2500; > + return PHY_INTERFACE_MODE_2500BASEX; > break; > default: > break; > diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c > index e1f812b688b1..eeb67a39a77f 100644 > --- a/drivers/net/fm/memac.c > +++ b/drivers/net/fm/memac.c > @@ -93,7 +93,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, > if_mode |= (IF_MODE_GMII | IF_MODE_RM); > break; > case PHY_INTERFACE_MODE_SGMII: > - case PHY_INTERFACE_MODE_SGMII_2500: > + case PHY_INTERFACE_MODE_2500BASEX: > case PHY_INTERFACE_MODE_QSGMII: > if_mode &= ~IF_MODE_MASK; > if_mode |= (IF_MODE_GMII); > diff --git a/drivers/net/fm/t1024.c b/drivers/net/fm/t1024.c > index 6fc3b9033701..696e74c9e6fe 100644 > --- a/drivers/net/fm/t1024.c > +++ b/drivers/net/fm/t1024.c > @@ -63,7 +63,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) > return PHY_INTERFACE_MODE_SGMII; > else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1 > + port - FM1_DTSEC1)) > - return PHY_INTERFACE_MODE_SGMII_2500; > + return PHY_INTERFACE_MODE_2500BASEX; > break; > default: > break; > diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c > index 12d9942b65d4..045527dcf7d9 100644 > --- a/drivers/net/fsl_enetc.c > +++ b/drivers/net/fsl_enetc.c > @@ -144,7 +144,7 @@ static int enetc_init_sgmii(struct udevice *dev) > if (!enetc_has_imdio(dev)) > return 0; > > - if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500) > + if (priv->if_type == PHY_INTERFACE_MODE_2500BASEX) > is2500 = true; > > /* > @@ -291,7 +291,7 @@ static void enetc_start_pcs(struct udevice *dev) > > switch (priv->if_type) { > case PHY_INTERFACE_MODE_SGMII: > - case PHY_INTERFACE_MODE_SGMII_2500: > + case PHY_INTERFACE_MODE_2500BASEX: > enetc_init_sgmii(dev); > break; > case PHY_INTERFACE_MODE_XGMII: > diff --git a/drivers/net/mscc_eswitch/felix_switch.c b/drivers/net/mscc_eswitch/felix_switch.c > index 67b2879e8585..bd40c3b8b1bb 100644 > --- a/drivers/net/mscc_eswitch/felix_switch.c > +++ b/drivers/net/mscc_eswitch/felix_switch.c > @@ -213,12 +213,12 @@ static void felix_start_pcs(struct udevice *dev, int port, > bool autoneg = true; > > if (phy->phy_id == PHY_FIXED_ID || > - phy->interface == PHY_INTERFACE_MODE_SGMII_2500) > + phy->interface == PHY_INTERFACE_MODE_2500BASEX) > autoneg = false; > > switch (phy->interface) { > case PHY_INTERFACE_MODE_SGMII: > - case PHY_INTERFACE_MODE_SGMII_2500: > + case PHY_INTERFACE_MODE_2500BASEX: > case PHY_INTERFACE_MODE_QSGMII: > felix_init_sgmii(imdio, port, autoneg); > break; > diff --git a/drivers/net/pfe_eth/pfe_mdio.c b/drivers/net/pfe_eth/pfe_mdio.c > index 3228b8df49d4..ae5b6fc2800a 100644 > --- a/drivers/net/pfe_eth/pfe_mdio.c > +++ b/drivers/net/pfe_eth/pfe_mdio.c > @@ -161,7 +161,7 @@ static void pfe_configure_serdes(struct pfe_eth_dev *priv) > int value, sgmii_2500 = 0; > struct gemac_s *gem = priv->gem; > > - if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) > + if (gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX) > sgmii_2500 = 1; > > > @@ -220,7 +220,7 @@ int pfe_phy_configure(struct pfe_eth_dev *priv, int dev_id, int phy_id) > > /* Configure SGMII PCS */ > if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII || > - gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) { > + gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX) { > out_be32(&scfg->mdioselcr, 0x00000000); > pfe_configure_serdes(priv); > } > diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c > index 66d1d9856825..83075f78c981 100644 > --- a/drivers/net/phy/aquantia.c > +++ b/drivers/net/phy/aquantia.c > @@ -308,7 +308,7 @@ struct { > } aquantia_syscfg[PHY_INTERFACE_MODE_COUNT] = { > [PHY_INTERFACE_MODE_SGMII] = {0x04b, AQUANTIA_VND1_GSYSCFG_1G, > AQUANTIA_VND1_GSTART_RATE_1G}, > - [PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G, > + [PHY_INTERFACE_MODE_2500BASEX] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G, > AQUANTIA_VND1_GSTART_RATE_2_5G}, > [PHY_INTERFACE_MODE_10GBASER] = {0x100, AQUANTIA_VND1_GSYSCFG_10G, > AQUANTIA_VND1_GSTART_RATE_10G}, > @@ -522,7 +522,7 @@ int aquantia_config(struct phy_device *phydev) > phy_write(phydev, MDIO_MMD_PHYXS, > AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1); > break; > - case PHY_INTERFACE_MODE_SGMII_2500: > + case PHY_INTERFACE_MODE_2500BASEX: > /* 2.5GBASE-T mode */ > phydev->advertising = SUPPORTED_1000baseT_Full; > phydev->supported = phydev->advertising; > -- > 2.25.1 > Reviewed-by: Ramon Fried <rfried.dev@gmail.com> ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/4] net: enetc: remove support for "xgmii" phy-mode 2021-09-18 12:32 [PATCH 0/4] phy-mode cleanup Vladimir Oltean 2021-09-18 12:32 ` [PATCH 1/4] net: replace the "xfi" phy-mode with "10gbase-r" Vladimir Oltean 2021-09-18 12:32 ` [PATCH 2/4] net: freescale: replace usage of phy-mode = "sgmii-2500" with "2500base-x" Vladimir Oltean @ 2021-09-18 12:32 ` Vladimir Oltean 2021-09-28 13:30 ` Ramon Fried 2021-09-18 12:32 ` [PATCH 4/4] net: dsa: felix: remove " Vladimir Oltean 3 siblings, 1 reply; 9+ messages in thread From: Vladimir Oltean @ 2021-09-18 12:32 UTC (permalink / raw) To: u-boot Cc: Joe Hershberger, Ramon Fried, Priyanka Jain, Madalin Bucur, Ioana Ciornei, Camelia Groza, Scott Wood, Pali Rohár, Marcin Wojtas, Stefan Chulski The enetc driver runs only on NXP LS1028A, which most definitely does not support the parallel 10G interface, just USXGMII, and that only up to 2.5Gbps (toned down from 10 Gbps via symbol replication). Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> --- drivers/net/fsl_enetc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index 045527dcf7d9..f56f9e7a129b 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -226,7 +226,6 @@ static void enetc_setup_mac_iface(struct udevice *dev, case PHY_INTERFACE_MODE_RGMII_TXID: enetc_init_rgmii(dev, phydev); break; - case PHY_INTERFACE_MODE_XGMII: case PHY_INTERFACE_MODE_USXGMII: case PHY_INTERFACE_MODE_10GBASER: /* set ifmode to (US)XGMII */ @@ -294,7 +293,6 @@ static void enetc_start_pcs(struct udevice *dev) case PHY_INTERFACE_MODE_2500BASEX: enetc_init_sgmii(dev); break; - case PHY_INTERFACE_MODE_XGMII: case PHY_INTERFACE_MODE_USXGMII: case PHY_INTERFACE_MODE_10GBASER: enetc_init_sxgmii(dev); -- 2.25.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 3/4] net: enetc: remove support for "xgmii" phy-mode 2021-09-18 12:32 ` [PATCH 3/4] net: enetc: remove support for "xgmii" phy-mode Vladimir Oltean @ 2021-09-28 13:30 ` Ramon Fried 0 siblings, 0 replies; 9+ messages in thread From: Ramon Fried @ 2021-09-28 13:30 UTC (permalink / raw) To: Vladimir Oltean Cc: U-Boot Mailing List, Joe Hershberger, Priyanka Jain, Madalin Bucur, Ioana Ciornei, Camelia Groza, Scott Wood, Pali Rohár, Marcin Wojtas, Stefan Chulski On Sat, Sep 18, 2021 at 3:34 PM Vladimir Oltean <vladimir.oltean@nxp.com> wrote: > > The enetc driver runs only on NXP LS1028A, which most definitely does > not support the parallel 10G interface, just USXGMII, and that only up > to 2.5Gbps (toned down from 10 Gbps via symbol replication). > > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> > --- > drivers/net/fsl_enetc.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c > index 045527dcf7d9..f56f9e7a129b 100644 > --- a/drivers/net/fsl_enetc.c > +++ b/drivers/net/fsl_enetc.c > @@ -226,7 +226,6 @@ static void enetc_setup_mac_iface(struct udevice *dev, > case PHY_INTERFACE_MODE_RGMII_TXID: > enetc_init_rgmii(dev, phydev); > break; > - case PHY_INTERFACE_MODE_XGMII: > case PHY_INTERFACE_MODE_USXGMII: > case PHY_INTERFACE_MODE_10GBASER: > /* set ifmode to (US)XGMII */ > @@ -294,7 +293,6 @@ static void enetc_start_pcs(struct udevice *dev) > case PHY_INTERFACE_MODE_2500BASEX: > enetc_init_sgmii(dev); > break; > - case PHY_INTERFACE_MODE_XGMII: > case PHY_INTERFACE_MODE_USXGMII: > case PHY_INTERFACE_MODE_10GBASER: > enetc_init_sxgmii(dev); > -- > 2.25.1 > Reviewed-by: Ramon Fried <rfried.dev@gmail.com> ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 4/4] net: dsa: felix: remove "xgmii" phy-mode 2021-09-18 12:32 [PATCH 0/4] phy-mode cleanup Vladimir Oltean ` (2 preceding siblings ...) 2021-09-18 12:32 ` [PATCH 3/4] net: enetc: remove support for "xgmii" phy-mode Vladimir Oltean @ 2021-09-18 12:32 ` Vladimir Oltean 2021-09-28 13:30 ` Ramon Fried 3 siblings, 1 reply; 9+ messages in thread From: Vladimir Oltean @ 2021-09-18 12:32 UTC (permalink / raw) To: u-boot Cc: Joe Hershberger, Ramon Fried, Priyanka Jain, Madalin Bucur, Ioana Ciornei, Camelia Groza, Scott Wood, Pali Rohár, Marcin Wojtas, Stefan Chulski The felix driver runs only on NXP LS1028A, which most definitely does not support the parallel 10G interface, just USXGMII, and that only up to 2.5Gbps (toned down from 10 Gbps via symbol replication). Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> --- drivers/net/mscc_eswitch/felix_switch.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/net/mscc_eswitch/felix_switch.c b/drivers/net/mscc_eswitch/felix_switch.c index bd40c3b8b1bb..47ac45b354da 100644 --- a/drivers/net/mscc_eswitch/felix_switch.c +++ b/drivers/net/mscc_eswitch/felix_switch.c @@ -222,7 +222,6 @@ static void felix_start_pcs(struct udevice *dev, int port, case PHY_INTERFACE_MODE_QSGMII: felix_init_sgmii(imdio, port, autoneg); break; - case PHY_INTERFACE_MODE_XGMII: case PHY_INTERFACE_MODE_10GBASER: case PHY_INTERFACE_MODE_USXGMII: if (felix_init_sxgmii(imdio, port)) -- 2.25.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 4/4] net: dsa: felix: remove "xgmii" phy-mode 2021-09-18 12:32 ` [PATCH 4/4] net: dsa: felix: remove " Vladimir Oltean @ 2021-09-28 13:30 ` Ramon Fried 0 siblings, 0 replies; 9+ messages in thread From: Ramon Fried @ 2021-09-28 13:30 UTC (permalink / raw) To: Vladimir Oltean Cc: U-Boot Mailing List, Joe Hershberger, Priyanka Jain, Madalin Bucur, Ioana Ciornei, Camelia Groza, Scott Wood, Pali Rohár, Marcin Wojtas, Stefan Chulski On Sat, Sep 18, 2021 at 3:34 PM Vladimir Oltean <vladimir.oltean@nxp.com> wrote: > > The felix driver runs only on NXP LS1028A, which most definitely does > not support the parallel 10G interface, just USXGMII, and that only up > to 2.5Gbps (toned down from 10 Gbps via symbol replication). > > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> > --- > drivers/net/mscc_eswitch/felix_switch.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/net/mscc_eswitch/felix_switch.c b/drivers/net/mscc_eswitch/felix_switch.c > index bd40c3b8b1bb..47ac45b354da 100644 > --- a/drivers/net/mscc_eswitch/felix_switch.c > +++ b/drivers/net/mscc_eswitch/felix_switch.c > @@ -222,7 +222,6 @@ static void felix_start_pcs(struct udevice *dev, int port, > case PHY_INTERFACE_MODE_QSGMII: > felix_init_sgmii(imdio, port, autoneg); > break; > - case PHY_INTERFACE_MODE_XGMII: > case PHY_INTERFACE_MODE_10GBASER: > case PHY_INTERFACE_MODE_USXGMII: > if (felix_init_sxgmii(imdio, port)) > -- > 2.25.1 > Reviewed-by: Ramon Fried <rfried.dev@gmail.com> ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-09-28 13:30 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-09-18 12:32 [PATCH 0/4] phy-mode cleanup Vladimir Oltean 2021-09-18 12:32 ` [PATCH 1/4] net: replace the "xfi" phy-mode with "10gbase-r" Vladimir Oltean 2021-09-28 13:28 ` Ramon Fried 2021-09-18 12:32 ` [PATCH 2/4] net: freescale: replace usage of phy-mode = "sgmii-2500" with "2500base-x" Vladimir Oltean 2021-09-28 13:29 ` Ramon Fried 2021-09-18 12:32 ` [PATCH 3/4] net: enetc: remove support for "xgmii" phy-mode Vladimir Oltean 2021-09-28 13:30 ` Ramon Fried 2021-09-18 12:32 ` [PATCH 4/4] net: dsa: felix: remove " Vladimir Oltean 2021-09-28 13:30 ` Ramon Fried
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).