* [PATCH V2 0/9] Rockchip: Improve Support for RK3566 Devices
@ 2023-02-13 22:27 Chris Morgan
2023-02-13 22:27 ` [PATCH V2 1/9] gpio: gpio-rockchip: parse gpio-ranges for bank id Chris Morgan
` (8 more replies)
0 siblings, 9 replies; 33+ messages in thread
From: Chris Morgan @ 2023-02-13 22:27 UTC (permalink / raw)
To: u-boot
Cc: heiko, sjg, philipp.tomsich, kever.yang, chenjh, pgwipeout,
heiko.stuebner, Chris Morgan
From: Chris Morgan <macromorgan@hotmail.com>
This series is to lay the groundwork to improve support for the RK3566
based devices. This syncs the devicetrees with upstream Linux and adds
support for the pin controller of the rk356x series.
Future patches will be submitted that builds on top of this to support
devices such as the Anbernic RG353 and RG503 which are based on the
RK3566.
Changes Since V1:
- Updated GPIO to parse bank ID from new property of "gpio-ranges"
which should be included in upstream Linux soon.
- Updated name of u-boot.dtsi file for the rk3568-evb1-v10.
- Updated MAINTAINERS file for evb-rk3568 board.
- Updated rockchip documentation for build instructions for
rk3568 boards.
- Removed links to patches co-authored by Peter Geis and instead
included him in the tags.
Chris Morgan (9):
gpio: gpio-rockchip: parse gpio-ranges for bank id
dts: rockchip: px30: add gpio-ranges property to gpio nodes
rockchip: vop2: Add vop2 dt-binding from Linux
arm64: dts: rockchip: Sync rk356x from Linux main
rockchip: rk3568: add boot device detection
rockchip: rk3568: enable automatic power savings
gpio/rockchip: rk_gpio support v2 gpio controller
arm64: dts: rockchip: add gpio-ranges property to gpio nodes
evb1-v10-rk3568: Update MAINTAINERS and documentation
arch/arm/dts/Makefile | 2 +-
arch/arm/dts/px30.dtsi | 4 +
arch/arm/dts/rk3568-evb.dts | 79 --
...-boot.dtsi => rk3568-evb1-v10-u-boot.dtsi} | 0
arch/arm/dts/rk3568-evb1-v10.dts | 692 ++++++++++++++++++
arch/arm/dts/rk3568.dtsi | 122 +++
arch/arm/dts/rk356x.dtsi | 187 ++++-
arch/arm/include/asm/arch-rockchip/gpio.h | 38 +
arch/arm/mach-rockchip/rk3568/rk3568.c | 31 +
board/rockchip/evb_rk3568/MAINTAINERS | 12 +-
...68_defconfig => evb1-v10-rk3568_defconfig} | 4 +-
doc/board/rockchip/rockchip.rst | 10 +
drivers/gpio/rk_gpio.c | 69 +-
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rk3568.c | 453 ++++++++++++
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 12 +-
include/dt-bindings/soc/rockchip,vop2.h | 14 +
17 files changed, 1613 insertions(+), 117 deletions(-)
delete mode 100644 arch/arm/dts/rk3568-evb.dts
rename arch/arm/dts/{rk3568-evb-u-boot.dtsi => rk3568-evb1-v10-u-boot.dtsi} (100%)
create mode 100644 arch/arm/dts/rk3568-evb1-v10.dts
rename configs/{evb-rk3568_defconfig => evb1-v10-rk3568_defconfig} (94%)
create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c
create mode 100644 include/dt-bindings/soc/rockchip,vop2.h
--
2.34.1
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH V2 1/9] gpio: gpio-rockchip: parse gpio-ranges for bank id
2023-02-13 22:27 [PATCH V2 0/9] Rockchip: Improve Support for RK3566 Devices Chris Morgan
@ 2023-02-13 22:27 ` Chris Morgan
2023-02-22 7:44 ` Kever Yang
` (2 more replies)
2023-02-13 22:27 ` [PATCH V2 2/9] dts: rockchip: px30: add gpio-ranges property to gpio nodes Chris Morgan
` (7 subsequent siblings)
8 siblings, 3 replies; 33+ messages in thread
From: Chris Morgan @ 2023-02-13 22:27 UTC (permalink / raw)
To: u-boot
Cc: heiko, sjg, philipp.tomsich, kever.yang, chenjh, pgwipeout,
heiko.stuebner, Chris Morgan
From: Chris Morgan <macromorgan@hotmail.com>
Use the new devicetree property of gpio-ranges to determine the GPIO
bank ID. Preserve the "old" way of doing things too, so that boards
can be migrated and tested gradually (I only have a 3566 and 3326 to
test).
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
drivers/gpio/rk_gpio.c | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index 68f30157a9..98a79b5f4d 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -142,6 +142,7 @@ static int rockchip_gpio_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct rockchip_gpio_priv *priv = dev_get_priv(dev);
+ struct ofnode_phandle_args args;
char *end;
int ret;
@@ -150,9 +151,22 @@ static int rockchip_gpio_probe(struct udevice *dev)
if (ret)
return ret;
- uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
- end = strrchr(dev->name, '@');
- priv->bank = trailing_strtoln(dev->name, end);
+ /*
+ * If "gpio-ranges" is present in the devicetree use it to parse
+ * the GPIO bank ID, otherwise use the legacy method.
+ */
+ ret = ofnode_parse_phandle_with_args(dev_ofnode(dev),
+ "gpio-ranges", NULL, 3,
+ 0, &args);
+ if (!ret || ret != -ENOENT) {
+ uc_priv->gpio_count = args.args[2];
+ priv->bank = args.args[1] / args.args[2];
+ } else {
+ uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
+ end = strrchr(dev->name, '@');
+ priv->bank = trailing_strtoln(dev->name, end);
+ }
+
priv->name[0] = 'A' + priv->bank;
uc_priv->bank_name = priv->name;
--
2.34.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH V2 2/9] dts: rockchip: px30: add gpio-ranges property to gpio nodes
2023-02-13 22:27 [PATCH V2 0/9] Rockchip: Improve Support for RK3566 Devices Chris Morgan
2023-02-13 22:27 ` [PATCH V2 1/9] gpio: gpio-rockchip: parse gpio-ranges for bank id Chris Morgan
@ 2023-02-13 22:27 ` Chris Morgan
2023-02-22 7:44 ` Kever Yang
2023-02-13 22:27 ` [PATCH V2 3/9] rockchip: vop2: Add vop2 dt-binding from Linux Chris Morgan
` (6 subsequent siblings)
8 siblings, 1 reply; 33+ messages in thread
From: Chris Morgan @ 2023-02-13 22:27 UTC (permalink / raw)
To: u-boot
Cc: heiko, sjg, philipp.tomsich, kever.yang, chenjh, pgwipeout,
heiko.stuebner, Chris Morgan
From: Chris Morgan <macromorgan@hotmail.com>
Add the gpio-ranges property to each GPIO node for use in deriving
the correct bank ID. Note that invoking "gpio status -a" no longer
causes the board to hit a "Synchronous Abort".
Fixes: 537b1a277479 ("rockchip: add px30 devicetrees")
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm/dts/px30.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
index bfa3580429..3152bf107d 100644
--- a/arch/arm/dts/px30.dtsi
+++ b/arch/arm/dts/px30.dtsi
@@ -1366,6 +1366,7 @@
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmucru PCLK_GPIO0_PMU>;
gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
interrupt-controller;
@@ -1378,6 +1379,7 @@
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>;
gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 32>;
#gpio-cells = <2>;
interrupt-controller;
@@ -1390,6 +1392,7 @@
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>;
gpio-controller;
+ gpio-ranges = <&pinctrl 0 64 32>;
#gpio-cells = <2>;
interrupt-controller;
@@ -1402,6 +1405,7 @@
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>;
gpio-controller;
+ gpio-ranges = <&pinctrl 0 96 32>;
#gpio-cells = <2>;
interrupt-controller;
--
2.34.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH V2 3/9] rockchip: vop2: Add vop2 dt-binding from Linux
2023-02-13 22:27 [PATCH V2 0/9] Rockchip: Improve Support for RK3566 Devices Chris Morgan
2023-02-13 22:27 ` [PATCH V2 1/9] gpio: gpio-rockchip: parse gpio-ranges for bank id Chris Morgan
2023-02-13 22:27 ` [PATCH V2 2/9] dts: rockchip: px30: add gpio-ranges property to gpio nodes Chris Morgan
@ 2023-02-13 22:27 ` Chris Morgan
2023-02-13 22:27 ` [PATCH V2 4/9] arm64: dts: rockchip: Sync rk356x from Linux main Chris Morgan
` (5 subsequent siblings)
8 siblings, 0 replies; 33+ messages in thread
From: Chris Morgan @ 2023-02-13 22:27 UTC (permalink / raw)
To: u-boot
Cc: heiko, sjg, philipp.tomsich, kever.yang, chenjh, pgwipeout,
heiko.stuebner, Chris Morgan
From: Chris Morgan <macromorgan@hotmail.com>
In order to support Rockchip devices with the VOP2, import the VOP2
dt-bindings from Linux.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
include/dt-bindings/soc/rockchip,vop2.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100644 include/dt-bindings/soc/rockchip,vop2.h
diff --git a/include/dt-bindings/soc/rockchip,vop2.h b/include/dt-bindings/soc/rockchip,vop2.h
new file mode 100644
index 0000000000..6e66a802b9
--- /dev/null
+++ b/include/dt-bindings/soc/rockchip,vop2.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+
+#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H
+#define __DT_BINDINGS_ROCKCHIP_VOP2_H
+
+#define ROCKCHIP_VOP2_EP_RGB0 1
+#define ROCKCHIP_VOP2_EP_HDMI0 2
+#define ROCKCHIP_VOP2_EP_EDP0 3
+#define ROCKCHIP_VOP2_EP_MIPI0 4
+#define ROCKCHIP_VOP2_EP_LVDS0 5
+#define ROCKCHIP_VOP2_EP_MIPI1 6
+#define ROCKCHIP_VOP2_EP_LVDS1 7
+
+#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH V2 4/9] arm64: dts: rockchip: Sync rk356x from Linux main
2023-02-13 22:27 [PATCH V2 0/9] Rockchip: Improve Support for RK3566 Devices Chris Morgan
` (2 preceding siblings ...)
2023-02-13 22:27 ` [PATCH V2 3/9] rockchip: vop2: Add vop2 dt-binding from Linux Chris Morgan
@ 2023-02-13 22:27 ` Chris Morgan
2023-02-15 18:44 ` Jonas Karlman
2023-02-13 22:27 ` [PATCH V2 5/9] rockchip: rk3568: add boot device detection Chris Morgan
` (4 subsequent siblings)
8 siblings, 1 reply; 33+ messages in thread
From: Chris Morgan @ 2023-02-13 22:27 UTC (permalink / raw)
To: u-boot
Cc: heiko, sjg, philipp.tomsich, kever.yang, chenjh, pgwipeout,
heiko.stuebner, Chris Morgan
From: Chris Morgan <macromorgan@hotmail.com>
Sync rk3566 and rk3568 from the mainline Linux kernel (6.2-rc2 as of
this writing).
Note that this will rename the rk3568-evb to rk3568-evb1-v10.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm/dts/Makefile | 2 +-
arch/arm/dts/rk3568-evb.dts | 79 --
...-boot.dtsi => rk3568-evb1-v10-u-boot.dtsi} | 0
arch/arm/dts/rk3568-evb1-v10.dts | 692 ++++++++++++++++++
arch/arm/dts/rk3568.dtsi | 122 +++
arch/arm/dts/rk356x.dtsi | 182 ++++-
...68_defconfig => evb1-v10-rk3568_defconfig} | 4 +-
7 files changed, 985 insertions(+), 96 deletions(-)
delete mode 100644 arch/arm/dts/rk3568-evb.dts
rename arch/arm/dts/{rk3568-evb-u-boot.dtsi => rk3568-evb1-v10-u-boot.dtsi} (100%)
create mode 100644 arch/arm/dts/rk3568-evb1-v10.dts
rename configs/{evb-rk3568_defconfig => evb1-v10-rk3568_defconfig} (94%)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9d647b9639..56e0543bd2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -165,7 +165,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399pro-rock-pi-n10.dtb
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
- rk3568-evb.dtb
+ rk3568-evb1-v10.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
diff --git a/arch/arm/dts/rk3568-evb.dts b/arch/arm/dts/rk3568-evb.dts
deleted file mode 100644
index 6978655709..0000000000
--- a/arch/arm/dts/rk3568-evb.dts
+++ /dev/null
@@ -1,79 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rk3568.dtsi"
-
-/ {
- model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
- compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
-
- chosen: chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- dc_12v: dc-12v {
- compatible = "regulator-fixed";
- regulator-name = "dc_12v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc3v3_sys: vcc3v3-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc3v3_lcd0_n: vcc3v3-lcd0-n {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_lcd0_n";
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_lcd1_n: vcc3v3-lcd1-n {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_lcd1_n";
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&sdhci {
- bus-width = <8>;
- max-frequency = <200000000>;
- non-removable;
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
diff --git a/arch/arm/dts/rk3568-evb-u-boot.dtsi b/arch/arm/dts/rk3568-evb1-v10-u-boot.dtsi
similarity index 100%
rename from arch/arm/dts/rk3568-evb-u-boot.dtsi
rename to arch/arm/dts/rk3568-evb1-v10-u-boot.dtsi
diff --git a/arch/arm/dts/rk3568-evb1-v10.dts b/arch/arm/dts/rk3568-evb1-v10.dts
new file mode 100644
index 0000000000..674792567f
--- /dev/null
+++ b/arch/arm/dts/rk3568-evb1-v10.dts
@@ -0,0 +1,692 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+ model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
+ compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_work: led-0 {
+ gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_BLUE>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_work_en>;
+ };
+ };
+
+ rk809-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "Analog RK809";
+ simple-audio-card,mclk-fs = <256>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&rk809>;
+ };
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_usb_host: vcc5v0-usb-host {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_host_en>;
+ regulator-name = "vcc5v0_usb_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_usb_otg: vcc5v0-usb-otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
+ regulator-name = "vcc5v0_usb_otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc3v3_lcd0_n: vcc3v3-lcd0-n {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_lcd0_n";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vcc3v3_sys>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc3v3_lcd0_n_en>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_lcd1_n: vcc3v3-lcd1-n {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_lcd1_n";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vcc3v3_sys>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc3v3_lcd1_n_en>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&combphy0 {
+ status = "okay";
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac0 {
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+ assigned-clock-rates = <0>, <125000000>;
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy0>;
+ phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus>;
+ status = "okay";
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+ assigned-clock-rates = <0>, <125000000>;
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_rgmii_bus>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ avdd-0v9-supply = <&vdda0v9_image>;
+ avdd-1v8-supply = <&vcca1v8_image>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+ #clock-cells = <1>;
+ clock-names = "mclk";
+ clocks = <&cru I2S1_MCLKOUT_TX>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+ rockchip,system-power-controller;
+ #sound-dai-cells = <0>;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+
+ codec {
+ mic-in-differential;
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ touchscreen0: goodix@14 {
+ compatible = "goodix,gt1151";
+ reg = <0x14>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB5 IRQ_TYPE_EDGE_FALLING>;
+ AVDD28-supply = <&vcc3v3_lcd0_n>;
+ irq-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touch_int &touch_rst>;
+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+ VDDIO-supply = <&vcc3v3_lcd0_n>;
+ };
+};
+
+&i2s0_8ch {
+ status = "okay";
+};
+
+&i2s1_8ch {
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+&mdio0 {
+ rgmii_phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ display {
+ vcc3v3_lcd0_n_en: vcc3v3_lcd0_n_en {
+ rockchip,pins = <0 RK_PC7 0 &pcfg_pull_none>;
+ };
+ vcc3v3_lcd1_n_en: vcc3v3_lcd1_n_en {
+ rockchip,pins = <0 RK_PC5 0 &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ led_work_en: led_work_en {
+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins =
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ touchscreen {
+ touch_int: touch_int {
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ touch_rst: touch_rst {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb_host_en: vcc5v0_usb_host_en {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ extcon = <&usb2phy0>;
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_usb_otg>;
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb2phy1_host {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi
index 2bdf8c7e97..ba67b58f05 100644
--- a/arch/arm/dts/rk3568.dtsi
+++ b/arch/arm/dts/rk3568.dtsi
@@ -42,6 +42,128 @@
reg = <0x0 0xfe190200 0x0 0x20>;
};
+ pcie30_phy_grf: syscon@fdcb8000 {
+ compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
+ reg = <0x0 0xfdcb8000 0x0 0x10000>;
+ };
+
+ pcie30phy: phy@fe8c0000 {
+ compatible = "rockchip,rk3568-pcie3-phy";
+ reg = <0x0 0xfe8c0000 0x0 0x20000>;
+ #phy-cells = <0>;
+ clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
+ <&cru PCLK_PCIE30PHY>;
+ clock-names = "refclk_m", "refclk_n", "pclk";
+ resets = <&cru SRST_PCIE30PHY>;
+ reset-names = "phy";
+ rockchip,phy-grf = <&pcie30_phy_grf>;
+ status = "disabled";
+ };
+
+ pcie3x1: pcie@fe270000 {
+ compatible = "rockchip,rk3568-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xf>;
+ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
+ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
+ <&cru CLK_PCIE30X1_AUX_NDFT>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk", "aux";
+ device_type = "pci";
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
+ <0 0 0 2 &pcie3x1_intc 1>,
+ <0 0 0 3 &pcie3x1_intc 2>,
+ <0 0 0 4 &pcie3x1_intc 3>;
+ linux,pci-domain = <1>;
+ num-ib-windows = <6>;
+ num-ob-windows = <2>;
+ max-link-speed = <3>;
+ msi-map = <0x0 &gic 0x1000 0x1000>;
+ num-lanes = <1>;
+ phys = <&pcie30phy>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3568_PD_PIPE>;
+ reg = <0x3 0xc0400000 0x0 0x00400000>,
+ <0x0 0xfe270000 0x0 0x00010000>,
+ <0x3 0x7f000000 0x0 0x01000000>;
+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
+ <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
+ reg-names = "dbi", "apb", "config";
+ resets = <&cru SRST_PCIE30X1_POWERUP>;
+ reset-names = "pipe";
+ /* bifurcation; lane1 when using 1+1 */
+ status = "disabled";
+
+ pcie3x1_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+ pcie3x2: pcie@fe280000 {
+ compatible = "rockchip,rk3568-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xf>;
+ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
+ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
+ <&cru CLK_PCIE30X2_AUX_NDFT>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk", "aux";
+ device_type = "pci";
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
+ <0 0 0 2 &pcie3x2_intc 1>,
+ <0 0 0 3 &pcie3x2_intc 2>,
+ <0 0 0 4 &pcie3x2_intc 3>;
+ linux,pci-domain = <2>;
+ num-ib-windows = <6>;
+ num-ob-windows = <2>;
+ max-link-speed = <3>;
+ msi-map = <0x0 &gic 0x2000 0x1000>;
+ num-lanes = <2>;
+ phys = <&pcie30phy>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3568_PD_PIPE>;
+ reg = <0x3 0xc0800000 0x0 0x00400000>,
+ <0x0 0xfe280000 0x0 0x00010000>,
+ <0x3 0xbf000000 0x0 0x01000000>;
+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
+ <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
+ reg-names = "dbi", "apb", "config";
+ resets = <&cru SRST_PCIE30X2_POWERUP>;
+ reset-names = "pipe";
+ /* bifurcation; lane0 when using 1+1 */
+ status = "disabled";
+
+ pcie3x2_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
gmac0: ethernet@fe2a0000 {
compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe2a0000 0x0 0x10000>;
diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi
index 319981c3e9..5706c3e24f 100644
--- a/arch/arm/dts/rk356x.dtsi
+++ b/arch/arm/dts/rk356x.dtsi
@@ -592,6 +592,46 @@
status = "disabled";
};
+ vpu: video-codec@fdea0400 {
+ compatible = "rockchip,rk3568-vpu";
+ reg = <0x0 0xfdea0000 0x0 0x800>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vdpu_mmu>;
+ power-domains = <&power RK3568_PD_VPU>;
+ };
+
+ vdpu_mmu: iommu@fdea0800 {
+ compatible = "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdea0800 0x0 0x40>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "aclk", "iface";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ power-domains = <&power RK3568_PD_VPU>;
+ #iommu-cells = <0>;
+ };
+
+ vepu: video-codec@fdee0000 {
+ compatible = "rockchip,rk3568-vepu";
+ reg = <0x0 0xfdee0000 0x0 0x800>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vepu_mmu>;
+ power-domains = <&power RK3568_PD_RGA>;
+ };
+
+ vepu_mmu: iommu@fdee0800 {
+ compatible = "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdee0800 0x0 0x40>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3568_PD_RGA>;
+ #iommu-cells = <0>;
+ };
+
sdmmc2: mmc@fe000000 {
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe000000 0x0 0x4000>;
@@ -699,6 +739,62 @@
status = "disabled";
};
+ dsi0: dsi@fe060000 {
+ compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x00 0xfe060000 0x00 0x10000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "pclk", "hclk";
+ clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
+ phy-names = "dphy";
+ phys = <&dsi_dphy0>;
+ power-domains = <&power RK3568_PD_VO>;
+ reset-names = "apb";
+ resets = <&cru SRST_P_DSITX_0>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi0_in: port@0 {
+ reg = <0>;
+ };
+
+ dsi0_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ dsi1: dsi@fe070000 {
+ compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x0 0xfe070000 0x0 0x10000>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "pclk", "hclk";
+ clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
+ phy-names = "dphy";
+ phys = <&dsi_dphy1>;
+ power-domains = <&power RK3568_PD_VO>;
+ reset-names = "apb";
+ resets = <&cru SRST_P_DSITX_1>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi1_in: port@0 {
+ reg = <0>;
+ };
+
+ dsi1_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
hdmi: hdmi@fe0a0000 {
compatible = "rockchip,rk3568-dw-hdmi";
reg = <0x0 0xfe0a0000 0x0 0x20000>;
@@ -953,20 +1049,6 @@
status = "disabled";
};
- spdif: spdif@fe460000 {
- compatible = "rockchip,rk3568-spdif";
- reg = <0x0 0xfe460000 0x0 0x1000>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "mclk", "hclk";
- clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
- dmas = <&dmac1 1>;
- dma-names = "tx";
- pinctrl-names = "default";
- pinctrl-0 = <&spdifm0_tx>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
i2s0_8ch: i2s@fe400000 {
compatible = "rockchip,rk3568-i2s-tdm";
reg = <0x0 0xfe400000 0x0 0x1000>;
@@ -1009,6 +1091,28 @@
status = "disabled";
};
+ i2s2_2ch: i2s@fe420000 {
+ compatible = "rockchip,rk3568-i2s-tdm";
+ reg = <0x0 0xfe420000 0x0 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
+ assigned-clock-rates = <1188000000>;
+ clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
+ dmas = <&dmac1 4>, <&dmac1 5>;
+ dma-names = "tx", "rx";
+ resets = <&cru SRST_M_I2S2_2CH>;
+ reset-names = "m";
+ rockchip,grf = <&grf>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s2m0_sclktx
+ &i2s2m0_lrcktx
+ &i2s2m0_sdi
+ &i2s2m0_sdo>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
i2s3_2ch: i2s@fe430000 {
compatible = "rockchip,rk3568-i2s-tdm";
reg = <0x0 0xfe430000 0x0 0x1000>;
@@ -1046,6 +1150,20 @@
status = "disabled";
};
+ spdif: spdif@fe460000 {
+ compatible = "rockchip,rk3568-spdif";
+ reg = <0x0 0xfe460000 0x0 0x1000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "mclk", "hclk";
+ clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
+ dmas = <&dmac1 1>;
+ dma-names = "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdifm0_tx>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
dmac0: dma-controller@fe530000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xfe530000 0x0 0x4000>;
@@ -1594,6 +1712,42 @@
status = "disabled";
};
+ csi_dphy: phy@fe870000 {
+ compatible = "rockchip,rk3568-csi-dphy";
+ reg = <0x0 0xfe870000 0x0 0x10000>;
+ clocks = <&cru PCLK_MIPICSIPHY>;
+ clock-names = "pclk";
+ #phy-cells = <0>;
+ resets = <&cru SRST_P_MIPICSIPHY>;
+ reset-names = "apb";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
+ dsi_dphy0: mipi-dphy@fe850000 {
+ compatible = "rockchip,rk3568-dsi-dphy";
+ reg = <0x0 0xfe850000 0x0 0x10000>;
+ clock-names = "ref", "pclk";
+ clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
+ #phy-cells = <0>;
+ power-domains = <&power RK3568_PD_VO>;
+ reset-names = "apb";
+ resets = <&cru SRST_P_MIPIDSIPHY0>;
+ status = "disabled";
+ };
+
+ dsi_dphy1: mipi-dphy@fe860000 {
+ compatible = "rockchip,rk3568-dsi-dphy";
+ reg = <0x0 0xfe860000 0x0 0x10000>;
+ clock-names = "ref", "pclk";
+ clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
+ #phy-cells = <0>;
+ power-domains = <&power RK3568_PD_VO>;
+ reset-names = "apb";
+ resets = <&cru SRST_P_MIPIDSIPHY1>;
+ status = "disabled";
+ };
+
usb2phy0: usb2phy@fe8a0000 {
compatible = "rockchip,rk3568-usb2phy";
reg = <0x0 0xfe8a0000 0x0 0x10000>;
diff --git a/configs/evb-rk3568_defconfig b/configs/evb1-v10-rk3568_defconfig
similarity index 94%
rename from configs/evb-rk3568_defconfig
rename to configs/evb1-v10-rk3568_defconfig
index a76d924d38..7ca1a35246 100644
--- a/configs/evb-rk3568_defconfig
+++ b/configs/evb1-v10-rk3568_defconfig
@@ -6,7 +6,7 @@ CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb1-v10"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
@@ -23,7 +23,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb1-v10.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x20000
--
2.34.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH V2 5/9] rockchip: rk3568: add boot device detection
2023-02-13 22:27 [PATCH V2 0/9] Rockchip: Improve Support for RK3566 Devices Chris Morgan
` (3 preceding siblings ...)
2023-02-13 22:27 ` [PATCH V2 4/9] arm64: dts: rockchip: Sync rk356x from Linux main Chris Morgan
@ 2023-02-13 22:27 ` Chris Morgan
2023-02-15 18:28 ` Jonas Karlman
2023-02-13 22:27 ` [PATCH V2 6/9] rockchip: rk3568: enable automatic power savings Chris Morgan
` (3 subsequent siblings)
8 siblings, 1 reply; 33+ messages in thread
From: Chris Morgan @ 2023-02-13 22:27 UTC (permalink / raw)
To: u-boot
Cc: heiko, sjg, philipp.tomsich, kever.yang, chenjh, pgwipeout,
heiko.stuebner, Chris Morgan
From: Chris Morgan <macromorgan@hotmail.com>
Enable spl to detect which device it was booted from.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm/mach-rockchip/rk3568/rk3568.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
index 22eeb77d41..a2d59abc26 100644
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -7,6 +7,7 @@
#include <dm.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/grf_rk3568.h>
#include <asm/arch-rockchip/hardware.h>
#include <dt-bindings/clock/rk3568-cru.h>
@@ -70,6 +71,12 @@ static struct mm_region rk3568_mem_map[] = {
}
};
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe310000",
+ [BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0",
+ [BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000",
+};
+
struct mm_region *mem_map = rk3568_mem_map;
void board_debug_uart_init(void)
--
2.34.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH V2 6/9] rockchip: rk3568: enable automatic power savings
2023-02-13 22:27 [PATCH V2 0/9] Rockchip: Improve Support for RK3566 Devices Chris Morgan
` (4 preceding siblings ...)
2023-02-13 22:27 ` [PATCH V2 5/9] rockchip: rk3568: add boot device detection Chris Morgan
@ 2023-02-13 22:27 ` Chris Morgan
2023-02-22 7:34 ` Kever Yang
2023-02-13 22:27 ` [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller Chris Morgan
` (2 subsequent siblings)
8 siblings, 1 reply; 33+ messages in thread
From: Chris Morgan @ 2023-02-13 22:27 UTC (permalink / raw)
To: u-boot
Cc: heiko, sjg, philipp.tomsich, kever.yang, chenjh, pgwipeout,
heiko.stuebner, Chris Morgan
From: Chris Morgan <macromorgan@hotmail.com>
It enables automatic clock gating on idle, disables the eDP phy by
default, and sets the core pvtpll ring length. It is reported this
lowers the temperature on at least one SoC by 7C.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm/mach-rockchip/rk3568/rk3568.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
index a2d59abc26..4a08820a09 100644
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -24,6 +24,16 @@
#define SGRF_SOC_CON4 0x10
#define EMMC_HPROT_SECURE_CTRL 0x03
#define SDMMC0_HPROT_SECURE_CTRL 0x01
+
+#define PMU_BASE_ADDR 0xfdd90000
+#define PMU_NOC_AUTO_CON0 (0x70)
+#define PMU_NOC_AUTO_CON1 (0x74)
+#define EDP_PHY_GRF_BASE 0xfdcb0000
+#define EDP_PHY_GRF_CON0 (EDP_PHY_GRF_BASE + 0x00)
+#define EDP_PHY_GRF_CON10 (EDP_PHY_GRF_BASE + 0x28)
+#define CPU_GRF_BASE 0xfdc30000
+#define GRF_CORE_PVTPLL_CON0 (0x10)
+
/* PMU_GRF_GPIO0D_IOMUX_L */
enum {
GPIO0D1_SHIFT = 4,
@@ -98,6 +108,20 @@ void board_debug_uart_init(void)
int arch_cpu_init(void)
{
#ifdef CONFIG_SPL_BUILD
+ /*
+ * When perform idle operation, corresponding clock can
+ * be opened or gated automatically.
+ */
+ writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
+ writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
+
+ /* Disable eDP phy by default */
+ writel(0x00070007, EDP_PHY_GRF_CON10);
+ writel(0x0ff10ff1, EDP_PHY_GRF_CON0);
+
+ /* Set core pvtpll ring length */
+ writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0);
+
/* Set the emmc sdmmc0 to secure */
rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11
| SDMMC0_HPROT_SECURE_CTRL << 4));
--
2.34.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller
2023-02-13 22:27 [PATCH V2 0/9] Rockchip: Improve Support for RK3566 Devices Chris Morgan
` (5 preceding siblings ...)
2023-02-13 22:27 ` [PATCH V2 6/9] rockchip: rk3568: enable automatic power savings Chris Morgan
@ 2023-02-13 22:27 ` Chris Morgan
2023-02-16 11:19 ` FUKAUMI Naoki
` (4 more replies)
2023-02-13 22:27 ` [PATCH V2 8/9] arm64: dts: rockchip: add gpio-ranges property to gpio nodes Chris Morgan
2023-02-13 22:27 ` [PATCH V2 9/9] evb1-v10-rk3568: Update MAINTAINERS and documentation Chris Morgan
8 siblings, 5 replies; 33+ messages in thread
From: Chris Morgan @ 2023-02-13 22:27 UTC (permalink / raw)
To: u-boot
Cc: heiko, sjg, philipp.tomsich, kever.yang, chenjh, pgwipeout,
heiko.stuebner, Chris Morgan
From: Chris Morgan <macromorgan@hotmail.com>
Add support for the newer GPIO controller used by the rk356x series,
as well as the pinctrl device for the rk356x series. The GPIOv2
controller has a write enable bit for some registers which differs
from the older versions of the GPIO controller.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm/include/asm/arch-rockchip/gpio.h | 38 ++
drivers/gpio/rk_gpio.c | 49 +-
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rk3568.c | 453 ++++++++++++++++++
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 12 +-
5 files changed, 540 insertions(+), 13 deletions(-)
create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c
diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h
index 1aaec5faec..15f5de321b 100644
--- a/arch/arm/include/asm/arch-rockchip/gpio.h
+++ b/arch/arm/include/asm/arch-rockchip/gpio.h
@@ -6,6 +6,7 @@
#ifndef _ASM_ARCH_GPIO_H
#define _ASM_ARCH_GPIO_H
+#if !defined(CONFIG_ROCKCHIP_RK3568)
struct rockchip_gpio_regs {
u32 swport_dr;
u32 swport_ddr;
@@ -22,7 +23,44 @@ struct rockchip_gpio_regs {
u32 reserved1[(0x60 - 0x54) / 4];
u32 ls_sync;
};
+
check_member(rockchip_gpio_regs, ls_sync, 0x60);
+#else
+struct rockchip_gpio_regs {
+ u32 swport_dr_l; /* ADDRESS OFFSET: 0x0000 */
+ u32 swport_dr_h; /* ADDRESS OFFSET: 0x0004 */
+ u32 swport_ddr_l; /* ADDRESS OFFSET: 0x0008 */
+ u32 swport_ddr_h; /* ADDRESS OFFSET: 0x000c */
+ u32 int_en_l; /* ADDRESS OFFSET: 0x0010 */
+ u32 int_en_h; /* ADDRESS OFFSET: 0x0014 */
+ u32 int_mask_l; /* ADDRESS OFFSET: 0x0018 */
+ u32 int_mask_h; /* ADDRESS OFFSET: 0x001c */
+ u32 int_type_l; /* ADDRESS OFFSET: 0x0020 */
+ u32 int_type_h; /* ADDRESS OFFSET: 0x0024 */
+ u32 int_polarity_l; /* ADDRESS OFFSET: 0x0028 */
+ u32 int_polarity_h; /* ADDRESS OFFSET: 0x002c */
+ u32 int_bothedge_l; /* ADDRESS OFFSET: 0x0030 */
+ u32 int_bothedge_h; /* ADDRESS OFFSET: 0x0034 */
+ u32 debounce_l; /* ADDRESS OFFSET: 0x0038 */
+ u32 debounce_h; /* ADDRESS OFFSET: 0x003c */
+ u32 dbclk_div_en_l; /* ADDRESS OFFSET: 0x0040 */
+ u32 dbclk_div_en_h; /* ADDRESS OFFSET: 0x0044 */
+ u32 dbclk_div_con; /* ADDRESS OFFSET: 0x0048 */
+ u32 reserved004c; /* ADDRESS OFFSET: 0x004c */
+ u32 int_status; /* ADDRESS OFFSET: 0x0050 */
+ u32 reserved0054; /* ADDRESS OFFSET: 0x0054 */
+ u32 int_rawstatus; /* ADDRESS OFFSET: 0x0058 */
+ u32 reserved005c; /* ADDRESS OFFSET: 0x005c */
+ u32 port_eoi_l; /* ADDRESS OFFSET: 0x0060 */
+ u32 port_eoi_h; /* ADDRESS OFFSET: 0x0064 */
+ u32 reserved0068[2]; /* ADDRESS OFFSET: 0x0068 */
+ u32 ext_port; /* ADDRESS OFFSET: 0x0070 */
+ u32 reserved0074; /* ADDRESS OFFSET: 0x0074 */
+ u32 ver_id; /* ADDRESS OFFSET: 0x0078 */
+};
+
+check_member(rockchip_gpio_regs, ver_id, 0x0078);
+#endif
enum gpio_pu_pd {
GPIO_PULL_NORMAL = 0,
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index 98a79b5f4d..e2653be058 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -2,12 +2,15 @@
/*
* (C) Copyright 2015 Google, Inc
*
- * (C) Copyright 2008-2014 Rockchip Electronics
+ * (C) Copyright 2008-2023 Rockchip Electronics
* Peter, Software Engineering, <superpeter.cai@gmail.com>.
+ * Jianqun Xu, Software Engineering, <jay.xu@rock-chips.com>.
*/
#include <common.h>
#include <dm.h>
+#include <dm/of_access.h>
+#include <dm/device_compat.h>
#include <syscon.h>
#include <linux/errno.h>
#include <asm/gpio.h>
@@ -23,6 +26,35 @@ enum {
#define OFFSET_TO_BIT(bit) (1UL << (bit))
+/*
+ * Newer Rockchip devices have additional registers that must be
+ * accounted for.
+ */
+#if defined(CONFIG_ROCKCHIP_RK3568)
+#define GPIO_VER 2
+#define REG_L(R) (R##_l)
+#define REG_H(R) (R##_h)
+#define READ_REG(REG) ((readl(REG_L(REG)) & 0xFFFF) | \
+ ((readl(REG_H(REG)) & 0xFFFF) << 16))
+#define WRITE_REG(REG, VAL) \
+{\
+ writel(((VAL) & 0xFFFF) | 0xFFFF0000, REG_L(REG)); \
+ writel((((VAL) & 0xFFFF0000) >> 16) | 0xFFFF0000, REG_H(REG));\
+}
+#define CLRBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) & ~(MASK))
+#define SETBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) | (MASK))
+#define CLRSETBITS_LE32(REG, MASK, VAL) WRITE_REG(REG, \
+ (READ_REG(REG) & ~(MASK)) | (VAL))
+
+#else
+#define GPIO_VER 1
+#define READ_REG(REG) readl(REG)
+#define WRITE_REG(REG, VAL) writel(VAL, REG)
+#define CLRBITS_LE32(REG, MASK) clrbits_le32(REG, MASK)
+#define SETBITS_LE32(REG, MASK) setbits_le32(REG, MASK)
+#define CLRSETBITS_LE32(REG, MASK, VAL) clrsetbits_le32(REG, MASK, VAL)
+#endif
+
struct rockchip_gpio_priv {
struct rockchip_gpio_regs *regs;
struct udevice *pinctrl;
@@ -35,7 +68,7 @@ static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset)
struct rockchip_gpio_priv *priv = dev_get_priv(dev);
struct rockchip_gpio_regs *regs = priv->regs;
- clrbits_le32(®s->swport_ddr, OFFSET_TO_BIT(offset));
+ CLRBITS_LE32(®s->swport_ddr, OFFSET_TO_BIT(offset));
return 0;
}
@@ -47,8 +80,8 @@ static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset,
struct rockchip_gpio_regs *regs = priv->regs;
int mask = OFFSET_TO_BIT(offset);
- clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0);
- setbits_le32(®s->swport_ddr, mask);
+ CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0);
+ SETBITS_LE32(®s->swport_ddr, mask);
return 0;
}
@@ -68,7 +101,7 @@ static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
struct rockchip_gpio_regs *regs = priv->regs;
int mask = OFFSET_TO_BIT(offset);
- clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0);
+ CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0);
return 0;
}
@@ -86,14 +119,14 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
if (ret)
return ret;
- is_output = readl(®s->swport_ddr) & OFFSET_TO_BIT(offset);
+ is_output = READ_REG(®s->swport_ddr) & OFFSET_TO_BIT(offset);
return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
#endif
}
/* Simple SPL interface to GPIOs */
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && (GPIO_VER == 1)
enum {
PULL_NONE_1V8 = 0,
@@ -143,7 +176,7 @@ static int rockchip_gpio_probe(struct udevice *dev)
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct rockchip_gpio_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args args;
- char *end;
+ char *end = NULL;
int ret;
priv->regs = dev_read_addr_ptr(dev);
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index 9884355473..90461ae881 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -14,5 +14,6 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o
obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
new file mode 100644
index 0000000000..dce1c1e7ee
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
@@ -0,0 +1,453 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#include "pinctrl-rockchip.h"
+
+static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
+ /* CAN0 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)),
+ /* CAN0 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)),
+ /* CAN1 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)),
+ /* CAN1 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)),
+ /* CAN2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)),
+ /* CAN2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)),
+ /* EDPDP_HPDIN IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)),
+ /* EDPDP_HPDIN IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)),
+ /* GMAC1 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 0)),
+ /* GMAC1 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PA7, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 1)),
+ /* HDMITX IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PD1, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 0)),
+ /* HDMITX IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO0, RK_PC7, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 1)),
+ /* I2C2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO0, RK_PB6, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 0)),
+ /* I2C2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PB4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 1)),
+ /* I2C3 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO1, RK_PA0, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(0, 0, 0)),
+ /* I2C3 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(0, 0, 1)),
+ /* I2C4 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PB2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(2, 2, 0)),
+ /* I2C4 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)),
+ /* I2C5 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)),
+ /* I2C5 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)),
+ /* PWM4 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)),
+ /* PWM4 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)),
+ /* PWM5 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)),
+ /* PWM5 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)),
+ /* PWM6 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)),
+ /* PWM6 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)),
+ /* PWM7 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)),
+ /* PWM7 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)),
+ /* PWM8 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)),
+ /* PWM8 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)),
+ /* PWM9 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)),
+ /* PWM9 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)),
+ /* PWM10 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)),
+ /* PWM10 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)),
+ /* PWM11 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)),
+ /* PWM11 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)),
+ /* PWM12 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)),
+ /* PWM12 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)),
+ /* PWM13 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)),
+ /* PWM13 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)),
+ /* PWM14 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)),
+ /* PWM14 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)),
+ /* PWM15 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)),
+ /* PWM15 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)),
+ /* SDMMC2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)),
+ /* SDMMC2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)),
+ /* SPI0 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)),
+ /* SPI0 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PD3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(0, 0, 1)),
+ /* SPI1 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PB5, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 0)),
+ /* SPI1 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PC3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 1)),
+ /* SPI2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(4, 4, 0)),
+ /* SPI2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(4, 4, 1)),
+ /* SPI3 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)),
+ /* SPI3 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)),
+ /* UART1 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)),
+ /* UART1 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)),
+ /* UART2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)),
+ /* UART2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)),
+ /* UART3 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)),
+ /* UART3 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(12, 12, 1)),
+ /* UART4 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(14, 14, 0)),
+ /* UART4 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(14, 14, 1)),
+ /* UART5 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PA2, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(0, 0, 0)),
+ /* UART5 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PC2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(0, 0, 1)),
+ /* UART6 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PA4, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 0)),
+ /* UART6 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)),
+ /* UART7 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)),
+ /* UART7 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)),
+ /* UART7 IO mux selection M2 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)),
+ /* UART8 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)),
+ /* UART8 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)),
+ /* UART9 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)),
+ /* UART9 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 1)),
+ /* UART9 IO mux selection M2 */
+ MR_TOPGRF(RK_GPIO4, RK_PA4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 2)),
+ /* I2S1 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO1, RK_PA2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(11, 10, 0)),
+ /* I2S1 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(11, 10, 1)),
+ /* I2S1 IO mux selection M2 */
+ MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(11, 10, 2)),
+ /* I2S2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(12, 12, 0)),
+ /* I2S2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)),
+ /* I2S3 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)),
+ /* I2S3 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)),
+ /* PDM IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)),
+ /* PDM IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)),
+ /* PCIE20 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)),
+ /* PCIE20 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)),
+ /* PCIE20 IO mux selection M2 */
+ MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)),
+ /* PCIE30X1 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO0, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(5, 4, 0)),
+ /* PCIE30X1 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PD2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 1)),
+ /* PCIE30X1 IO mux selection M2 */
+ MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 2)),
+ /* PCIE30X2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO0, RK_PA6, RK_FUNC_2, 0x0314, RK_GENMASK_VAL(7, 6, 0)),
+ /* PCIE30X2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 1)),
+ /* PCIE30X2 IO mux selection M2 */
+ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 2)),
+};
+
+static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask;
+ u8 bit;
+ u32 data;
+
+ debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
+
+ if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ regmap = priv->regmap_pmu;
+ else
+ regmap = priv->regmap_base;
+
+ reg = bank->iomux[iomux_num].offset;
+ if ((pin % 8) >= 4)
+ reg += 0x4;
+ bit = (pin % 4) * 4;
+ mask = 0xf;
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+#define RK3568_PULL_PMU_OFFSET 0x20
+#define RK3568_PULL_GRF_OFFSET 0x80
+#define RK3568_PULL_BITS_PER_PIN 2
+#define RK3568_PULL_PINS_PER_REG 8
+#define RK3568_PULL_BANK_STRIDE 0x10
+
+static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *info = bank->priv;
+
+ if (bank->bank_num == 0) {
+ *regmap = info->regmap_pmu;
+ *reg = RK3568_PULL_PMU_OFFSET;
+ *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
+ } else {
+ *regmap = info->regmap_base;
+ *reg = RK3568_PULL_GRF_OFFSET;
+ *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
+ }
+
+ *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
+ *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
+ *bit *= RK3568_PULL_BITS_PER_PIN;
+}
+
+#define RK3568_DRV_PMU_OFFSET 0x70
+#define RK3568_DRV_GRF_OFFSET 0x200
+#define RK3568_DRV_BITS_PER_PIN 8
+#define RK3568_DRV_PINS_PER_REG 2
+#define RK3568_DRV_BANK_STRIDE 0x40
+
+static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *info = bank->priv;
+
+ /* The first 32 pins of the first bank are located in PMU */
+ if (bank->bank_num == 0) {
+ *regmap = info->regmap_pmu;
+ *reg = RK3568_DRV_PMU_OFFSET;
+ } else {
+ *regmap = info->regmap_base;
+ *reg = RK3568_DRV_GRF_OFFSET;
+ *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
+ }
+
+ *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
+ *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
+ *bit *= RK3568_DRV_BITS_PER_PIN;
+}
+
+#define RK3568_SCHMITT_BITS_PER_PIN 2
+#define RK3568_SCHMITT_PINS_PER_REG 8
+#define RK3568_SCHMITT_BANK_STRIDE 0x10
+#define RK3568_SCHMITT_GRF_OFFSET 0xc0
+#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
+
+static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *info = bank->priv;
+
+ if (bank->bank_num == 0) {
+ *regmap = info->regmap_pmu;
+ *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
+ } else {
+ *regmap = info->regmap_base;
+ *reg = RK3568_SCHMITT_GRF_OFFSET;
+ *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
+ }
+
+ *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
+ *bit *= RK3568_SCHMITT_BITS_PER_PIN;
+
+ return 0;
+}
+
+static int rk3568_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit, type;
+ u32 data;
+
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+ return -EOPNOTSUPP;
+
+ rk3568_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ type = bank->pull_type[pin_num / 8];
+ ret = rockchip_translate_pull_value(type, pull);
+ if (ret < 0) {
+ debug("unsupported pull setting %d\n", pull);
+ return ret;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+static int rk3568_set_drive(struct rockchip_pin_bank *bank,
+ int pin_num, int strength)
+{
+ struct regmap *regmap;
+ int reg;
+ u32 data;
+ u8 bit;
+ int drv = (1 << (strength + 1)) - 1;
+ int ret = 0;
+
+ rk3568_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (drv << bit);
+
+ ret = regmap_write(regmap, reg, data);
+ if (ret)
+ return ret;
+
+ if (bank->bank_num == 1 && pin_num == 21)
+ reg = 0x0840;
+ else if (bank->bank_num == 2 && pin_num == 2)
+ reg = 0x0844;
+ else if (bank->bank_num == 2 && pin_num == 8)
+ reg = 0x0848;
+ else if (bank->bank_num == 3 && pin_num == 0)
+ reg = 0x084c;
+ else if (bank->bank_num == 3 && pin_num == 6)
+ reg = 0x0850;
+ else if (bank->bank_num == 4 && pin_num == 0)
+ reg = 0x0854;
+ else
+ return 0;
+
+ data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16;
+ data |= drv;
+
+ return regmap_write(regmap, reg, data);
+}
+
+static int rk3568_set_schmitt(struct rockchip_pin_bank *bank,
+ int pin_num, int enable)
+{
+ struct regmap *regmap;
+ int reg;
+ u32 data;
+ u8 bit;
+
+ rk3568_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (enable << bit);
+
+ return regmap_write(regmap, reg, data);
+}
+
+static struct rockchip_pin_bank rk3568_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
+ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
+ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
+ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT),
+};
+
+static const struct rockchip_pin_ctrl rk3568_pin_ctrl = {
+ .pin_banks = rk3568_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
+ .nr_pins = 160,
+ .grf_mux_offset = 0x0,
+ .pmu_mux_offset = 0x0,
+ .iomux_routes = rk3568_mux_route_data,
+ .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
+ .set_mux = rk3568_set_mux,
+ .set_pull = rk3568_set_pull,
+ .set_drive = rk3568_set_drive,
+ .set_schmitt = rk3568_set_schmitt,
+};
+
+static const struct udevice_id rk3568_pinctrl_ids[] = {
+ {
+ .compatible = "rockchip,rk3568-pinctrl",
+ .data = (ulong)&rk3568_pin_ctrl
+ },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_rk3568) = {
+ .name = "rockchip_rk3568_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = rk3568_pinctrl_ids,
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
+ .ops = &rockchip_pinctrl_ops,
+#if !IS_ENABLED(CONFIG_OF_PLATDATA)
+ .bind = dm_scan_fdt_dev,
+#endif
+ .probe = rockchip_pinctrl_probe,
+};
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
index d9d61fdb72..1481c1e51c 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
@@ -433,7 +433,7 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
int prop_len, param;
const u32 *data;
ofnode node;
-#ifdef CONFIG_OF_LIVE
+#if CONFIG_IS_ENABLED(OF_LIVE)
const struct device_node *np;
struct property *pp;
#else
@@ -473,7 +473,7 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
node = ofnode_get_by_phandle(conf);
if (!ofnode_valid(node))
return -ENODEV;
-#ifdef CONFIG_OF_LIVE
+#if CONFIG_IS_ENABLED(OF_LIVE)
np = ofnode_to_np(node);
for (pp = np->properties; pp; pp = pp->next) {
prop_name = pp->name;
@@ -548,13 +548,15 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d
/* preset iomux offset value, set new start value */
if (iom->offset >= 0) {
- if (iom->type & IOMUX_SOURCE_PMU)
+ if ((iom->type & IOMUX_SOURCE_PMU) || \
+ (iom->type & IOMUX_L_SOURCE_PMU))
pmu_offs = iom->offset;
else
grf_offs = iom->offset;
} else { /* set current iomux offset */
- iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
- pmu_offs : grf_offs;
+ iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
+ (iom->type & IOMUX_L_SOURCE_PMU)) ?
+ pmu_offs : grf_offs;
}
/* preset drv offset value, set new start value */
--
2.34.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH V2 8/9] arm64: dts: rockchip: add gpio-ranges property to gpio nodes
2023-02-13 22:27 [PATCH V2 0/9] Rockchip: Improve Support for RK3566 Devices Chris Morgan
` (6 preceding siblings ...)
2023-02-13 22:27 ` [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller Chris Morgan
@ 2023-02-13 22:27 ` Chris Morgan
2023-02-22 7:47 ` Kever Yang
2023-02-23 21:12 ` Vasily Khoruzhick
2023-02-13 22:27 ` [PATCH V2 9/9] evb1-v10-rk3568: Update MAINTAINERS and documentation Chris Morgan
8 siblings, 2 replies; 33+ messages in thread
From: Chris Morgan @ 2023-02-13 22:27 UTC (permalink / raw)
To: u-boot
Cc: heiko, sjg, philipp.tomsich, kever.yang, chenjh, pgwipeout,
heiko.stuebner, Chris Morgan
From: Chris Morgan <macromorgan@hotmail.com>
Add gpio-ranges property to GPIO nodes so that the bank ID can
be correctly derived for each GPIO bank.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm/dts/rk356x.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi
index 5706c3e24f..6492ace0de 100644
--- a/arch/arm/dts/rk356x.dtsi
+++ b/arch/arm/dts/rk356x.dtsi
@@ -1806,6 +1806,7 @@
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -1817,6 +1818,7 @@
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -1828,6 +1830,7 @@
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
gpio-controller;
+ gpio-ranges = <&pinctrl 0 64 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -1839,6 +1842,7 @@
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
gpio-controller;
+ gpio-ranges = <&pinctrl 0 96 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -1850,6 +1854,7 @@
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
gpio-controller;
+ gpio-ranges = <&pinctrl 0 128 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
--
2.34.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH V2 9/9] evb1-v10-rk3568: Update MAINTAINERS and documentation
2023-02-13 22:27 [PATCH V2 0/9] Rockchip: Improve Support for RK3566 Devices Chris Morgan
` (7 preceding siblings ...)
2023-02-13 22:27 ` [PATCH V2 8/9] arm64: dts: rockchip: add gpio-ranges property to gpio nodes Chris Morgan
@ 2023-02-13 22:27 ` Chris Morgan
2023-02-22 7:48 ` Kever Yang
8 siblings, 1 reply; 33+ messages in thread
From: Chris Morgan @ 2023-02-13 22:27 UTC (permalink / raw)
To: u-boot
Cc: heiko, sjg, philipp.tomsich, kever.yang, chenjh, pgwipeout,
heiko.stuebner, Chris Morgan
From: Chris Morgan <macromorgan@hotmail.com>
Update the MAINTAINERS file to include the devicetree for the
rk3568-evb1-v10 board.
Also update Rockchip board docs to include information on building
RK3568 based devices.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
board/rockchip/evb_rk3568/MAINTAINERS | 12 +++++++-----
doc/board/rockchip/rockchip.rst | 10 ++++++++++
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS
index b6ea498d2b..f959e8862b 100644
--- a/board/rockchip/evb_rk3568/MAINTAINERS
+++ b/board/rockchip/evb_rk3568/MAINTAINERS
@@ -1,6 +1,8 @@
EVB-RK3568
-M: Joseph Chen <chenjh@rock-chips.com>
-S: Maintained
-F: board/rockchip/evb_rk3568
-F: include/configs/evb_rk3568.h
-F: configs/evb-rk3568_defconfig
+M: Joseph Chen <chenjh@rock-chips.com>
+S: Maintained
+F: arch/arm/dts/rk3568-evb1-v10-u-boot.dtsi
+F: arch/arm/dts/rk3568-evb1-v10.dts
+F: board/rockchip/evb_rk3568
+F: configs/evb1-v10-rk3568_defconfig
+F: include/configs/evb_rk3568.h
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 28c837a382..02e6e82927 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -86,6 +86,8 @@ List of mainline supported Rockchip boards:
- Radxa ROCK Pi 4 (rock-pi-4-rk3399)
- Rockchip Evb-RK3399 (evb_rk3399)
- Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399)
+* rk3568
+ - Rockchip EVB-RK3568 (evb1-v10-rk3568)
* rv1108
- Rockchip Evb-rv1108 (evb-rv1108)
- Elgin-R1 (elgin-rv1108)
@@ -167,6 +169,14 @@ To build rk3399 boards:
make evb-rk3399_defconfig
make CROSS_COMPILE=aarch64-linux-gnu-
+To build rk3568 boards:
+
+.. code-block:: bash
+
+ export BL31=../arm-trusted-firmware/build/rk3568/release/bl31/bl31.elf
+ make evb1-v10-rk3568_defconfig
+ make CROSS_COMPILE=aarch64-linux-gnu-
+
Flashing
--------
--
2.34.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH V2 5/9] rockchip: rk3568: add boot device detection
2023-02-13 22:27 ` [PATCH V2 5/9] rockchip: rk3568: add boot device detection Chris Morgan
@ 2023-02-15 18:28 ` Jonas Karlman
2023-02-22 7:45 ` Kever Yang
0 siblings, 1 reply; 33+ messages in thread
From: Jonas Karlman @ 2023-02-15 18:28 UTC (permalink / raw)
To: Chris Morgan, u-boot
Cc: heiko, sjg, philipp.tomsich, kever.yang, chenjh, pgwipeout,
heiko.stuebner, Chris Morgan
Hi Chris,
On 2023-02-13 23:27, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Enable spl to detect which device it was booted from.
>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> ---
> arch/arm/mach-rockchip/rk3568/rk3568.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
> index 22eeb77d41..a2d59abc26 100644
> --- a/arch/arm/mach-rockchip/rk3568/rk3568.c
> +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
> @@ -7,6 +7,7 @@
> #include <dm.h>
> #include <asm/armv8/mmu.h>
> #include <asm/io.h>
> +#include <asm/arch-rockchip/bootrom.h>
> #include <asm/arch-rockchip/grf_rk3568.h>
> #include <asm/arch-rockchip/hardware.h>
> #include <dt-bindings/clock/rk3568-cru.h>
> @@ -70,6 +71,12 @@ static struct mm_region rk3568_mem_map[] = {
> }
> };
>
> +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
> + [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe310000",
This should be mmc@@fe310000.
Regards,
Jonas
> + [BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0",
> + [BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000",
> +};
> +
> struct mm_region *mem_map = rk3568_mem_map;
>
> void board_debug_uart_init(void)
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 4/9] arm64: dts: rockchip: Sync rk356x from Linux main
2023-02-13 22:27 ` [PATCH V2 4/9] arm64: dts: rockchip: Sync rk356x from Linux main Chris Morgan
@ 2023-02-15 18:44 ` Jonas Karlman
2023-02-22 7:32 ` Kever Yang
0 siblings, 1 reply; 33+ messages in thread
From: Jonas Karlman @ 2023-02-15 18:44 UTC (permalink / raw)
To: Chris Morgan, u-boot
Cc: heiko, sjg, philipp.tomsich, kever.yang, chenjh, pgwipeout,
heiko.stuebner, Chris Morgan
On 2023-02-13 23:27, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Sync rk3566 and rk3568 from the mainline Linux kernel (6.2-rc2 as of
> this writing).
>
> Note that this will rename the rk3568-evb to rk3568-evb1-v10.
Is the rename and sync of evb-rk3568 necessary for your use case?
I tend to abuse the evb variants as "minimal" soc defconfig. They
usually contain minimal needed to boot any board following the reference
design from sd or emmc.
Using the current evb-rk3568_defconfig and rk3568-evb.dts I can boot,
load atf and start linux on all my rk3566/rk3568 boards. Not sure that
will continue to be possible after these changes.
Regards,
Jonas
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> ---
> arch/arm/dts/Makefile | 2 +-
> arch/arm/dts/rk3568-evb.dts | 79 --
> ...-boot.dtsi => rk3568-evb1-v10-u-boot.dtsi} | 0
> arch/arm/dts/rk3568-evb1-v10.dts | 692 ++++++++++++++++++
> arch/arm/dts/rk3568.dtsi | 122 +++
> arch/arm/dts/rk356x.dtsi | 182 ++++-
> ...68_defconfig => evb1-v10-rk3568_defconfig} | 4 +-
> 7 files changed, 985 insertions(+), 96 deletions(-)
> delete mode 100644 arch/arm/dts/rk3568-evb.dts
> rename arch/arm/dts/{rk3568-evb-u-boot.dtsi => rk3568-evb1-v10-u-boot.dtsi} (100%)
> create mode 100644 arch/arm/dts/rk3568-evb1-v10.dts
> rename configs/{evb-rk3568_defconfig => evb1-v10-rk3568_defconfig} (94%)
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 9d647b9639..56e0543bd2 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -165,7 +165,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
> rk3399pro-rock-pi-n10.dtb
>
> dtb-$(CONFIG_ROCKCHIP_RK3568) += \
> - rk3568-evb.dtb
> + rk3568-evb1-v10.dtb
>
> dtb-$(CONFIG_ROCKCHIP_RV1108) += \
> rv1108-elgin-r1.dtb \
> diff --git a/arch/arm/dts/rk3568-evb.dts b/arch/arm/dts/rk3568-evb.dts
> deleted file mode 100644
> index 6978655709..0000000000
> --- a/arch/arm/dts/rk3568-evb.dts
> +++ /dev/null
> @@ -1,79 +0,0 @@
> -// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> -/*
> - * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
> - *
> - */
> -
> -/dts-v1/;
> -#include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/pinctrl/rockchip.h>
> -#include "rk3568.dtsi"
> -
> -/ {
> - model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
> - compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
> -
> - chosen: chosen {
> - stdout-path = "serial2:1500000n8";
> - };
> -
> - dc_12v: dc-12v {
> - compatible = "regulator-fixed";
> - regulator-name = "dc_12v";
> - regulator-always-on;
> - regulator-boot-on;
> - regulator-min-microvolt = <12000000>;
> - regulator-max-microvolt = <12000000>;
> - };
> -
> - vcc3v3_sys: vcc3v3-sys {
> - compatible = "regulator-fixed";
> - regulator-name = "vcc3v3_sys";
> - regulator-always-on;
> - regulator-boot-on;
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - vin-supply = <&dc_12v>;
> - };
> -
> - vcc5v0_sys: vcc5v0-sys {
> - compatible = "regulator-fixed";
> - regulator-name = "vcc5v0_sys";
> - regulator-always-on;
> - regulator-boot-on;
> - regulator-min-microvolt = <5000000>;
> - regulator-max-microvolt = <5000000>;
> - vin-supply = <&dc_12v>;
> - };
> -
> - vcc3v3_lcd0_n: vcc3v3-lcd0-n {
> - compatible = "regulator-fixed";
> - regulator-name = "vcc3v3_lcd0_n";
> - regulator-boot-on;
> -
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - vcc3v3_lcd1_n: vcc3v3-lcd1-n {
> - compatible = "regulator-fixed";
> - regulator-name = "vcc3v3_lcd1_n";
> - regulator-boot-on;
> -
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -};
> -
> -&sdhci {
> - bus-width = <8>;
> - max-frequency = <200000000>;
> - non-removable;
> - status = "okay";
> -};
> -
> -&uart2 {
> - status = "okay";
> -};
> diff --git a/arch/arm/dts/rk3568-evb-u-boot.dtsi b/arch/arm/dts/rk3568-evb1-v10-u-boot.dtsi
> similarity index 100%
> rename from arch/arm/dts/rk3568-evb-u-boot.dtsi
> rename to arch/arm/dts/rk3568-evb1-v10-u-boot.dtsi
> diff --git a/arch/arm/dts/rk3568-evb1-v10.dts b/arch/arm/dts/rk3568-evb1-v10.dts
> new file mode 100644
> index 0000000000..674792567f
> --- /dev/null
> +++ b/arch/arm/dts/rk3568-evb1-v10.dts
> @@ -0,0 +1,692 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
> + *
> + */
> +
> +/dts-v1/;
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/soc/rockchip,vop2.h>
> +#include "rk3568.dtsi"
> +
> +/ {
> + model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
> + compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
> +
> + aliases {
> + ethernet0 = &gmac0;
> + ethernet1 = &gmac1;
> + mmc0 = &sdmmc0;
> + mmc1 = &sdhci;
> + };
> +
> + chosen: chosen {
> + stdout-path = "serial2:1500000n8";
> + };
> +
> + dc_12v: dc-12v {
> + compatible = "regulator-fixed";
> + regulator-name = "dc_12v";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <12000000>;
> + regulator-max-microvolt = <12000000>;
> + };
> +
> + hdmi-con {
> + compatible = "hdmi-connector";
> + type = "a";
> +
> + port {
> + hdmi_con_in: endpoint {
> + remote-endpoint = <&hdmi_out_con>;
> + };
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + led_work: led-0 {
> + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
> + function = LED_FUNCTION_HEARTBEAT;
> + color = <LED_COLOR_ID_BLUE>;
> + linux,default-trigger = "heartbeat";
> + pinctrl-names = "default";
> + pinctrl-0 = <&led_work_en>;
> + };
> + };
> +
> + rk809-sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,name = "Analog RK809";
> + simple-audio-card,mclk-fs = <256>;
> +
> + simple-audio-card,cpu {
> + sound-dai = <&i2s1_8ch>;
> + };
> + simple-audio-card,codec {
> + sound-dai = <&rk809>;
> + };
> + };
> +
> + vcc3v3_sys: vcc3v3-sys {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3_sys";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + vin-supply = <&dc_12v>;
> + };
> +
> + vcc5v0_sys: vcc5v0-sys {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc5v0_sys";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + vin-supply = <&dc_12v>;
> + };
> +
> + vcc5v0_usb: vcc5v0-usb {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc5v0_usb";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + vin-supply = <&dc_12v>;
> + };
> +
> + vcc5v0_usb_host: vcc5v0-usb-host {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&vcc5v0_usb_host_en>;
> + regulator-name = "vcc5v0_usb_host";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + vin-supply = <&vcc5v0_usb>;
> + };
> +
> + vcc5v0_usb_otg: vcc5v0-usb-otg {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&vcc5v0_usb_otg_en>;
> + regulator-name = "vcc5v0_usb_otg";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + vin-supply = <&vcc5v0_usb>;
> + };
> +
> + vcc3v3_lcd0_n: vcc3v3-lcd0-n {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3_lcd0_n";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + enable-active-high;
> + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
> + vin-supply = <&vcc3v3_sys>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&vcc3v3_lcd0_n_en>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vcc3v3_lcd1_n: vcc3v3-lcd1-n {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3_lcd1_n";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + enable-active-high;
> + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
> + vin-supply = <&vcc3v3_sys>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&vcc3v3_lcd1_n_en>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +};
> +
> +&combphy0 {
> + status = "okay";
> +};
> +
> +&combphy1 {
> + status = "okay";
> +};
> +
> +&cpu0 {
> + cpu-supply = <&vdd_cpu>;
> +};
> +
> +&cpu1 {
> + cpu-supply = <&vdd_cpu>;
> +};
> +
> +&cpu2 {
> + cpu-supply = <&vdd_cpu>;
> +};
> +
> +&cpu3 {
> + cpu-supply = <&vdd_cpu>;
> +};
> +
> +&gmac0 {
> + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
> + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
> + assigned-clock-rates = <0>, <125000000>;
> + clock_in_out = "output";
> + phy-handle = <&rgmii_phy0>;
> + phy-mode = "rgmii-id";
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac0_miim
> + &gmac0_tx_bus2
> + &gmac0_rx_bus2
> + &gmac0_rgmii_clk
> + &gmac0_rgmii_bus>;
> + status = "okay";
> +};
> +
> +&gmac1 {
> + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
> + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
> + assigned-clock-rates = <0>, <125000000>;
> + clock_in_out = "output";
> + phy-handle = <&rgmii_phy1>;
> + phy-mode = "rgmii-id";
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac1m1_miim
> + &gmac1m1_tx_bus2
> + &gmac1m1_rx_bus2
> + &gmac1m1_rgmii_clk
> + &gmac1m1_rgmii_bus>;
> + status = "okay";
> +};
> +
> +&gpu {
> + mali-supply = <&vdd_gpu>;
> + status = "okay";
> +};
> +
> +&hdmi {
> + avdd-0v9-supply = <&vdda0v9_image>;
> + avdd-1v8-supply = <&vcca1v8_image>;
> + status = "okay";
> +};
> +
> +&hdmi_in {
> + hdmi_in_vp0: endpoint {
> + remote-endpoint = <&vp0_out_hdmi>;
> + };
> +};
> +
> +&hdmi_out {
> + hdmi_out_con: endpoint {
> + remote-endpoint = <&hdmi_con_in>;
> + };
> +};
> +
> +&hdmi_sound {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + status = "okay";
> +
> + vdd_cpu: regulator@1c {
> + compatible = "tcs,tcs4525";
> + reg = <0x1c>;
> + fcs,suspend-voltage-selector = <1>;
> + regulator-name = "vdd_cpu";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1150000>;
> + regulator-ramp-delay = <2300>;
> + vin-supply = <&vcc5v0_sys>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + rk809: pmic@20 {
> + compatible = "rockchip,rk809";
> + reg = <0x20>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
> + assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
> + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
> + #clock-cells = <1>;
> + clock-names = "mclk";
> + clocks = <&cru I2S1_MCLKOUT_TX>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
> + rockchip,system-power-controller;
> + #sound-dai-cells = <0>;
> + vcc1-supply = <&vcc3v3_sys>;
> + vcc2-supply = <&vcc3v3_sys>;
> + vcc3-supply = <&vcc3v3_sys>;
> + vcc4-supply = <&vcc3v3_sys>;
> + vcc5-supply = <&vcc3v3_sys>;
> + vcc6-supply = <&vcc3v3_sys>;
> + vcc7-supply = <&vcc3v3_sys>;
> + vcc8-supply = <&vcc3v3_sys>;
> + vcc9-supply = <&vcc3v3_sys>;
> + wakeup-source;
> +
> + regulators {
> + vdd_logic: DCDC_REG1 {
> + regulator-name = "vdd_logic";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-init-microvolt = <900000>;
> + regulator-initial-mode = <0x2>;
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-ramp-delay = <6001>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vdd_gpu: DCDC_REG2 {
> + regulator-name = "vdd_gpu";
> + regulator-always-on;
> + regulator-init-microvolt = <900000>;
> + regulator-initial-mode = <0x2>;
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-ramp-delay = <6001>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vcc_ddr: DCDC_REG3 {
> + regulator-name = "vcc_ddr";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-initial-mode = <0x2>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + };
> + };
> +
> + vdd_npu: DCDC_REG4 {
> + regulator-name = "vdd_npu";
> + regulator-init-microvolt = <900000>;
> + regulator-initial-mode = <0x2>;
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-ramp-delay = <6001>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vcc_1v8: DCDC_REG5 {
> + regulator-name = "vcc_1v8";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vdda0v9_image: LDO_REG1 {
> + regulator-name = "vdda0v9_image";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vdda_0v9: LDO_REG2 {
> + regulator-name = "vdda_0v9";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vdda0v9_pmu: LDO_REG3 {
> + regulator-name = "vdda0v9_pmu";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <900000>;
> + };
> + };
> +
> + vccio_acodec: LDO_REG4 {
> + regulator-name = "vccio_acodec";
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vccio_sd: LDO_REG5 {
> + regulator-name = "vccio_sd";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vcc3v3_pmu: LDO_REG6 {
> + regulator-name = "vcc3v3_pmu";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <3300000>;
> + };
> + };
> +
> + vcca_1v8: LDO_REG7 {
> + regulator-name = "vcca_1v8";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vcca1v8_pmu: LDO_REG8 {
> + regulator-name = "vcca1v8_pmu";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <1800000>;
> + };
> + };
> +
> + vcca1v8_image: LDO_REG9 {
> + regulator-name = "vcca1v8_image";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vcc_3v3: SWITCH_REG1 {
> + regulator-name = "vcc_3v3";
> + regulator-always-on;
> + regulator-boot-on;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vcc3v3_sd: SWITCH_REG2 {
> + regulator-name = "vcc3v3_sd";
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> + };
> +
> + codec {
> + mic-in-differential;
> + };
> + };
> +};
> +
> +&i2c1 {
> + status = "okay";
> +
> + touchscreen0: goodix@14 {
> + compatible = "goodix,gt1151";
> + reg = <0x14>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <RK_PB5 IRQ_TYPE_EDGE_FALLING>;
> + AVDD28-supply = <&vcc3v3_lcd0_n>;
> + irq-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&touch_int &touch_rst>;
> + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
> + VDDIO-supply = <&vcc3v3_lcd0_n>;
> + };
> +};
> +
> +&i2s0_8ch {
> + status = "okay";
> +};
> +
> +&i2s1_8ch {
> + rockchip,trcm-sync-tx-only;
> + status = "okay";
> +};
> +
> +&mdio0 {
> + rgmii_phy0: ethernet-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0x0>;
> + reset-assert-us = <20000>;
> + reset-deassert-us = <100000>;
> + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
> + };
> +};
> +
> +&mdio1 {
> + rgmii_phy1: ethernet-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0x0>;
> + reset-assert-us = <20000>;
> + reset-deassert-us = <100000>;
> + reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
> + };
> +};
> +
> +&pinctrl {
> + display {
> + vcc3v3_lcd0_n_en: vcc3v3_lcd0_n_en {
> + rockchip,pins = <0 RK_PC7 0 &pcfg_pull_none>;
> + };
> + vcc3v3_lcd1_n_en: vcc3v3_lcd1_n_en {
> + rockchip,pins = <0 RK_PC5 0 &pcfg_pull_none>;
> + };
> + };
> +
> + leds {
> + led_work_en: led_work_en {
> + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + pmic {
> + pmic_int: pmic_int {
> + rockchip,pins =
> + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
> + };
> + };
> +
> + touchscreen {
> + touch_int: touch_int {
> + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
> + };
> + touch_rst: touch_rst {
> + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + usb {
> + vcc5v0_usb_host_en: vcc5v0_usb_host_en {
> + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
> + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +};
> +
> +&pmu_io_domains {
> + pmuio1-supply = <&vcc3v3_pmu>;
> + pmuio2-supply = <&vcc3v3_pmu>;
> + vccio1-supply = <&vccio_acodec>;
> + vccio2-supply = <&vcc_1v8>;
> + vccio3-supply = <&vccio_sd>;
> + vccio4-supply = <&vcc_1v8>;
> + vccio5-supply = <&vcc_3v3>;
> + vccio6-supply = <&vcc_1v8>;
> + vccio7-supply = <&vcc_3v3>;
> + status = "okay";
> +};
> +
> +&saradc {
> + vref-supply = <&vcca_1v8>;
> + status = "okay";
> +};
> +
> +&sdhci {
> + bus-width = <8>;
> + max-frequency = <200000000>;
> + non-removable;
> + pinctrl-names = "default";
> + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
> + status = "okay";
> +};
> +
> +&sdmmc0 {
> + bus-width = <4>;
> + cap-sd-highspeed;
> + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
> + disable-wp;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
> + sd-uhs-sdr104;
> + vmmc-supply = <&vcc3v3_sd>;
> + vqmmc-supply = <&vccio_sd>;
> + status = "okay";
> +};
> +
> +&tsadc {
> + rockchip,hw-tshut-mode = <1>;
> + rockchip,hw-tshut-polarity = <0>;
> + status = "okay";
> +};
> +
> +&uart2 {
> + status = "okay";
> +};
> +
> +&usb_host0_ehci {
> + status = "okay";
> +};
> +
> +&usb_host0_ohci {
> + status = "okay";
> +};
> +
> +&usb_host0_xhci {
> + extcon = <&usb2phy0>;
> + status = "okay";
> +};
> +
> +&usb_host1_ehci {
> + status = "okay";
> +};
> +
> +&usb_host1_ohci {
> + status = "okay";
> +};
> +
> +&usb_host1_xhci {
> + status = "okay";
> +};
> +
> +&usb2phy0 {
> + status = "okay";
> +};
> +
> +&usb2phy0_host {
> + phy-supply = <&vcc5v0_usb_host>;
> + status = "okay";
> +};
> +
> +&usb2phy0_otg {
> + phy-supply = <&vcc5v0_usb_otg>;
> + status = "okay";
> +};
> +
> +&usb2phy1 {
> + status = "okay";
> +};
> +
> +&usb2phy1_host {
> + phy-supply = <&vcc5v0_usb_host>;
> + status = "okay";
> +};
> +
> +&usb2phy1_otg {
> + phy-supply = <&vcc5v0_usb_host>;
> + status = "okay";
> +};
> +
> +&vop {
> + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
> + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
> + status = "okay";
> +};
> +
> +&vop_mmu {
> + status = "okay";
> +};
> +
> +&vp0 {
> + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
> + reg = <ROCKCHIP_VOP2_EP_HDMI0>;
> + remote-endpoint = <&hdmi_in_vp0>;
> + };
> +};
> diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi
> index 2bdf8c7e97..ba67b58f05 100644
> --- a/arch/arm/dts/rk3568.dtsi
> +++ b/arch/arm/dts/rk3568.dtsi
> @@ -42,6 +42,128 @@
> reg = <0x0 0xfe190200 0x0 0x20>;
> };
>
> + pcie30_phy_grf: syscon@fdcb8000 {
> + compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
> + reg = <0x0 0xfdcb8000 0x0 0x10000>;
> + };
> +
> + pcie30phy: phy@fe8c0000 {
> + compatible = "rockchip,rk3568-pcie3-phy";
> + reg = <0x0 0xfe8c0000 0x0 0x20000>;
> + #phy-cells = <0>;
> + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
> + <&cru PCLK_PCIE30PHY>;
> + clock-names = "refclk_m", "refclk_n", "pclk";
> + resets = <&cru SRST_PCIE30PHY>;
> + reset-names = "phy";
> + rockchip,phy-grf = <&pcie30_phy_grf>;
> + status = "disabled";
> + };
> +
> + pcie3x1: pcie@fe270000 {
> + compatible = "rockchip,rk3568-pcie";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x0 0xf>;
> + clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
> + <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
> + <&cru CLK_PCIE30X1_AUX_NDFT>;
> + clock-names = "aclk_mst", "aclk_slv",
> + "aclk_dbi", "pclk", "aux";
> + device_type = "pci";
> + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "sys", "pmc", "msg", "legacy", "err";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
> + <0 0 0 2 &pcie3x1_intc 1>,
> + <0 0 0 3 &pcie3x1_intc 2>,
> + <0 0 0 4 &pcie3x1_intc 3>;
> + linux,pci-domain = <1>;
> + num-ib-windows = <6>;
> + num-ob-windows = <2>;
> + max-link-speed = <3>;
> + msi-map = <0x0 &gic 0x1000 0x1000>;
> + num-lanes = <1>;
> + phys = <&pcie30phy>;
> + phy-names = "pcie-phy";
> + power-domains = <&power RK3568_PD_PIPE>;
> + reg = <0x3 0xc0400000 0x0 0x00400000>,
> + <0x0 0xfe270000 0x0 0x00010000>,
> + <0x3 0x7f000000 0x0 0x01000000>;
> + ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
> + <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
> + reg-names = "dbi", "apb", "config";
> + resets = <&cru SRST_PCIE30X1_POWERUP>;
> + reset-names = "pipe";
> + /* bifurcation; lane1 when using 1+1 */
> + status = "disabled";
> +
> + pcie3x1_intc: legacy-interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
> + };
> + };
> +
> + pcie3x2: pcie@fe280000 {
> + compatible = "rockchip,rk3568-pcie";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x0 0xf>;
> + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
> + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
> + <&cru CLK_PCIE30X2_AUX_NDFT>;
> + clock-names = "aclk_mst", "aclk_slv",
> + "aclk_dbi", "pclk", "aux";
> + device_type = "pci";
> + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "sys", "pmc", "msg", "legacy", "err";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
> + <0 0 0 2 &pcie3x2_intc 1>,
> + <0 0 0 3 &pcie3x2_intc 2>,
> + <0 0 0 4 &pcie3x2_intc 3>;
> + linux,pci-domain = <2>;
> + num-ib-windows = <6>;
> + num-ob-windows = <2>;
> + max-link-speed = <3>;
> + msi-map = <0x0 &gic 0x2000 0x1000>;
> + num-lanes = <2>;
> + phys = <&pcie30phy>;
> + phy-names = "pcie-phy";
> + power-domains = <&power RK3568_PD_PIPE>;
> + reg = <0x3 0xc0800000 0x0 0x00400000>,
> + <0x0 0xfe280000 0x0 0x00010000>,
> + <0x3 0xbf000000 0x0 0x01000000>;
> + ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
> + <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
> + reg-names = "dbi", "apb", "config";
> + resets = <&cru SRST_PCIE30X2_POWERUP>;
> + reset-names = "pipe";
> + /* bifurcation; lane0 when using 1+1 */
> + status = "disabled";
> +
> + pcie3x2_intc: legacy-interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
> + };
> + };
> +
> gmac0: ethernet@fe2a0000 {
> compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
> reg = <0x0 0xfe2a0000 0x0 0x10000>;
> diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi
> index 319981c3e9..5706c3e24f 100644
> --- a/arch/arm/dts/rk356x.dtsi
> +++ b/arch/arm/dts/rk356x.dtsi
> @@ -592,6 +592,46 @@
> status = "disabled";
> };
>
> + vpu: video-codec@fdea0400 {
> + compatible = "rockchip,rk3568-vpu";
> + reg = <0x0 0xfdea0000 0x0 0x800>;
> + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
> + clock-names = "aclk", "hclk";
> + iommus = <&vdpu_mmu>;
> + power-domains = <&power RK3568_PD_VPU>;
> + };
> +
> + vdpu_mmu: iommu@fdea0800 {
> + compatible = "rockchip,rk3568-iommu";
> + reg = <0x0 0xfdea0800 0x0 0x40>;
> + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "aclk", "iface";
> + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
> + power-domains = <&power RK3568_PD_VPU>;
> + #iommu-cells = <0>;
> + };
> +
> + vepu: video-codec@fdee0000 {
> + compatible = "rockchip,rk3568-vepu";
> + reg = <0x0 0xfdee0000 0x0 0x800>;
> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
> + clock-names = "aclk", "hclk";
> + iommus = <&vepu_mmu>;
> + power-domains = <&power RK3568_PD_RGA>;
> + };
> +
> + vepu_mmu: iommu@fdee0800 {
> + compatible = "rockchip,rk3568-iommu";
> + reg = <0x0 0xfdee0800 0x0 0x40>;
> + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
> + clock-names = "aclk", "iface";
> + power-domains = <&power RK3568_PD_RGA>;
> + #iommu-cells = <0>;
> + };
> +
> sdmmc2: mmc@fe000000 {
> compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
> reg = <0x0 0xfe000000 0x0 0x4000>;
> @@ -699,6 +739,62 @@
> status = "disabled";
> };
>
> + dsi0: dsi@fe060000 {
> + compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
> + reg = <0x00 0xfe060000 0x00 0x10000>;
> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "pclk", "hclk";
> + clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
> + phy-names = "dphy";
> + phys = <&dsi_dphy0>;
> + power-domains = <&power RK3568_PD_VO>;
> + reset-names = "apb";
> + resets = <&cru SRST_P_DSITX_0>;
> + rockchip,grf = <&grf>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dsi0_in: port@0 {
> + reg = <0>;
> + };
> +
> + dsi0_out: port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> + dsi1: dsi@fe070000 {
> + compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
> + reg = <0x0 0xfe070000 0x0 0x10000>;
> + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "pclk", "hclk";
> + clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
> + phy-names = "dphy";
> + phys = <&dsi_dphy1>;
> + power-domains = <&power RK3568_PD_VO>;
> + reset-names = "apb";
> + resets = <&cru SRST_P_DSITX_1>;
> + rockchip,grf = <&grf>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dsi1_in: port@0 {
> + reg = <0>;
> + };
> +
> + dsi1_out: port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> hdmi: hdmi@fe0a0000 {
> compatible = "rockchip,rk3568-dw-hdmi";
> reg = <0x0 0xfe0a0000 0x0 0x20000>;
> @@ -953,20 +1049,6 @@
> status = "disabled";
> };
>
> - spdif: spdif@fe460000 {
> - compatible = "rockchip,rk3568-spdif";
> - reg = <0x0 0xfe460000 0x0 0x1000>;
> - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> - clock-names = "mclk", "hclk";
> - clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
> - dmas = <&dmac1 1>;
> - dma-names = "tx";
> - pinctrl-names = "default";
> - pinctrl-0 = <&spdifm0_tx>;
> - #sound-dai-cells = <0>;
> - status = "disabled";
> - };
> -
> i2s0_8ch: i2s@fe400000 {
> compatible = "rockchip,rk3568-i2s-tdm";
> reg = <0x0 0xfe400000 0x0 0x1000>;
> @@ -1009,6 +1091,28 @@
> status = "disabled";
> };
>
> + i2s2_2ch: i2s@fe420000 {
> + compatible = "rockchip,rk3568-i2s-tdm";
> + reg = <0x0 0xfe420000 0x0 0x1000>;
> + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
> + assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
> + assigned-clock-rates = <1188000000>;
> + clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
> + clock-names = "mclk_tx", "mclk_rx", "hclk";
> + dmas = <&dmac1 4>, <&dmac1 5>;
> + dma-names = "tx", "rx";
> + resets = <&cru SRST_M_I2S2_2CH>;
> + reset-names = "m";
> + rockchip,grf = <&grf>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2s2m0_sclktx
> + &i2s2m0_lrcktx
> + &i2s2m0_sdi
> + &i2s2m0_sdo>;
> + #sound-dai-cells = <0>;
> + status = "disabled";
> + };
> +
> i2s3_2ch: i2s@fe430000 {
> compatible = "rockchip,rk3568-i2s-tdm";
> reg = <0x0 0xfe430000 0x0 0x1000>;
> @@ -1046,6 +1150,20 @@
> status = "disabled";
> };
>
> + spdif: spdif@fe460000 {
> + compatible = "rockchip,rk3568-spdif";
> + reg = <0x0 0xfe460000 0x0 0x1000>;
> + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "mclk", "hclk";
> + clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
> + dmas = <&dmac1 1>;
> + dma-names = "tx";
> + pinctrl-names = "default";
> + pinctrl-0 = <&spdifm0_tx>;
> + #sound-dai-cells = <0>;
> + status = "disabled";
> + };
> +
> dmac0: dma-controller@fe530000 {
> compatible = "arm,pl330", "arm,primecell";
> reg = <0x0 0xfe530000 0x0 0x4000>;
> @@ -1594,6 +1712,42 @@
> status = "disabled";
> };
>
> + csi_dphy: phy@fe870000 {
> + compatible = "rockchip,rk3568-csi-dphy";
> + reg = <0x0 0xfe870000 0x0 0x10000>;
> + clocks = <&cru PCLK_MIPICSIPHY>;
> + clock-names = "pclk";
> + #phy-cells = <0>;
> + resets = <&cru SRST_P_MIPICSIPHY>;
> + reset-names = "apb";
> + rockchip,grf = <&grf>;
> + status = "disabled";
> + };
> +
> + dsi_dphy0: mipi-dphy@fe850000 {
> + compatible = "rockchip,rk3568-dsi-dphy";
> + reg = <0x0 0xfe850000 0x0 0x10000>;
> + clock-names = "ref", "pclk";
> + clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
> + #phy-cells = <0>;
> + power-domains = <&power RK3568_PD_VO>;
> + reset-names = "apb";
> + resets = <&cru SRST_P_MIPIDSIPHY0>;
> + status = "disabled";
> + };
> +
> + dsi_dphy1: mipi-dphy@fe860000 {
> + compatible = "rockchip,rk3568-dsi-dphy";
> + reg = <0x0 0xfe860000 0x0 0x10000>;
> + clock-names = "ref", "pclk";
> + clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
> + #phy-cells = <0>;
> + power-domains = <&power RK3568_PD_VO>;
> + reset-names = "apb";
> + resets = <&cru SRST_P_MIPIDSIPHY1>;
> + status = "disabled";
> + };
> +
> usb2phy0: usb2phy@fe8a0000 {
> compatible = "rockchip,rk3568-usb2phy";
> reg = <0x0 0xfe8a0000 0x0 0x10000>;
> diff --git a/configs/evb-rk3568_defconfig b/configs/evb1-v10-rk3568_defconfig
> similarity index 94%
> rename from configs/evb-rk3568_defconfig
> rename to configs/evb1-v10-rk3568_defconfig
> index a76d924d38..7ca1a35246 100644
> --- a/configs/evb-rk3568_defconfig
> +++ b/configs/evb1-v10-rk3568_defconfig
> @@ -6,7 +6,7 @@ CONFIG_TEXT_BASE=0x00a00000
> CONFIG_SPL_LIBCOMMON_SUPPORT=y
> CONFIG_SPL_LIBGENERIC_SUPPORT=y
> CONFIG_NR_DRAM_BANKS=2
> -CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
> +CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb1-v10"
> CONFIG_ROCKCHIP_RK3568=y
> CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
> CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
> @@ -23,7 +23,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
> CONFIG_FIT=y
> CONFIG_FIT_VERBOSE=y
> CONFIG_SPL_LOAD_FIT=y
> -CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb1-v10.dtb"
> # CONFIG_DISPLAY_CPUINFO is not set
> CONFIG_DISPLAY_BOARDINFO_LATE=y
> CONFIG_SPL_MAX_SIZE=0x20000
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller
2023-02-13 22:27 ` [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller Chris Morgan
@ 2023-02-16 11:19 ` FUKAUMI Naoki
2023-02-22 7:49 ` Kever Yang
` (3 subsequent siblings)
4 siblings, 0 replies; 33+ messages in thread
From: FUKAUMI Naoki @ 2023-02-16 11:19 UTC (permalink / raw)
To: Chris Morgan, u-boot
Cc: heiko, sjg, philipp.tomsich, kever.yang, chenjh, pgwipeout,
heiko.stuebner, Chris Morgan
hi,
On 2/14/23 07:27, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Add support for the newer GPIO controller used by the rk356x series,
> as well as the pinctrl device for the rk356x series. The GPIOv2
> controller has a write enable bit for some registers which differs
> from the older versions of the GPIO controller.
>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> ---
> arch/arm/include/asm/arch-rockchip/gpio.h | 38 ++
> drivers/gpio/rk_gpio.c | 49 +-
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl-rk3568.c | 453 ++++++++++++++++++
> .../pinctrl/rockchip/pinctrl-rockchip-core.c | 12 +-
> 5 files changed, 540 insertions(+), 13 deletions(-)
> create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c
>
> diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h
> index 1aaec5faec..15f5de321b 100644
> --- a/arch/arm/include/asm/arch-rockchip/gpio.h
> +++ b/arch/arm/include/asm/arch-rockchip/gpio.h
> @@ -6,6 +6,7 @@
> #ifndef _ASM_ARCH_GPIO_H
> #define _ASM_ARCH_GPIO_H
>
> +#if !defined(CONFIG_ROCKCHIP_RK3568)
> struct rockchip_gpio_regs {
> u32 swport_dr;
> u32 swport_ddr;
> @@ -22,7 +23,44 @@ struct rockchip_gpio_regs {
> u32 reserved1[(0x60 - 0x54) / 4];
> u32 ls_sync;
> };
> +
> check_member(rockchip_gpio_regs, ls_sync, 0x60);
> +#else
> +struct rockchip_gpio_regs {
> + u32 swport_dr_l; /* ADDRESS OFFSET: 0x0000 */
> + u32 swport_dr_h; /* ADDRESS OFFSET: 0x0004 */
> + u32 swport_ddr_l; /* ADDRESS OFFSET: 0x0008 */
> + u32 swport_ddr_h; /* ADDRESS OFFSET: 0x000c */
> + u32 int_en_l; /* ADDRESS OFFSET: 0x0010 */
> + u32 int_en_h; /* ADDRESS OFFSET: 0x0014 */
> + u32 int_mask_l; /* ADDRESS OFFSET: 0x0018 */
> + u32 int_mask_h; /* ADDRESS OFFSET: 0x001c */
> + u32 int_type_l; /* ADDRESS OFFSET: 0x0020 */
> + u32 int_type_h; /* ADDRESS OFFSET: 0x0024 */
> + u32 int_polarity_l; /* ADDRESS OFFSET: 0x0028 */
> + u32 int_polarity_h; /* ADDRESS OFFSET: 0x002c */
> + u32 int_bothedge_l; /* ADDRESS OFFSET: 0x0030 */
> + u32 int_bothedge_h; /* ADDRESS OFFSET: 0x0034 */
> + u32 debounce_l; /* ADDRESS OFFSET: 0x0038 */
> + u32 debounce_h; /* ADDRESS OFFSET: 0x003c */
> + u32 dbclk_div_en_l; /* ADDRESS OFFSET: 0x0040 */
> + u32 dbclk_div_en_h; /* ADDRESS OFFSET: 0x0044 */
> + u32 dbclk_div_con; /* ADDRESS OFFSET: 0x0048 */
> + u32 reserved004c; /* ADDRESS OFFSET: 0x004c */
> + u32 int_status; /* ADDRESS OFFSET: 0x0050 */
> + u32 reserved0054; /* ADDRESS OFFSET: 0x0054 */
> + u32 int_rawstatus; /* ADDRESS OFFSET: 0x0058 */
> + u32 reserved005c; /* ADDRESS OFFSET: 0x005c */
> + u32 port_eoi_l; /* ADDRESS OFFSET: 0x0060 */
> + u32 port_eoi_h; /* ADDRESS OFFSET: 0x0064 */
> + u32 reserved0068[2]; /* ADDRESS OFFSET: 0x0068 */
> + u32 ext_port; /* ADDRESS OFFSET: 0x0070 */
> + u32 reserved0074; /* ADDRESS OFFSET: 0x0074 */
> + u32 ver_id; /* ADDRESS OFFSET: 0x0078 */
> +};
> +
> +check_member(rockchip_gpio_regs, ver_id, 0x0078);
> +#endif
>
> enum gpio_pu_pd {
> GPIO_PULL_NORMAL = 0,
> diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
> index 98a79b5f4d..e2653be058 100644
> --- a/drivers/gpio/rk_gpio.c
> +++ b/drivers/gpio/rk_gpio.c
> @@ -2,12 +2,15 @@
> /*
> * (C) Copyright 2015 Google, Inc
> *
> - * (C) Copyright 2008-2014 Rockchip Electronics
> + * (C) Copyright 2008-2023 Rockchip Electronics
> * Peter, Software Engineering, <superpeter.cai@gmail.com>.
> + * Jianqun Xu, Software Engineering, <jay.xu@rock-chips.com>.
> */
>
> #include <common.h>
> #include <dm.h>
> +#include <dm/of_access.h>
> +#include <dm/device_compat.h>
> #include <syscon.h>
> #include <linux/errno.h>
> #include <asm/gpio.h>
> @@ -23,6 +26,35 @@ enum {
>
> #define OFFSET_TO_BIT(bit) (1UL << (bit))
>
> +/*
> + * Newer Rockchip devices have additional registers that must be
> + * accounted for.
> + */
> +#if defined(CONFIG_ROCKCHIP_RK3568)
> +#define GPIO_VER 2
> +#define REG_L(R) (R##_l)
> +#define REG_H(R) (R##_h)
> +#define READ_REG(REG) ((readl(REG_L(REG)) & 0xFFFF) | \
> + ((readl(REG_H(REG)) & 0xFFFF) << 16))
> +#define WRITE_REG(REG, VAL) \
> +{\
> + writel(((VAL) & 0xFFFF) | 0xFFFF0000, REG_L(REG)); \
> + writel((((VAL) & 0xFFFF0000) >> 16) | 0xFFFF0000, REG_H(REG));\
> +}
> +#define CLRBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) & ~(MASK))
> +#define SETBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) | (MASK))
> +#define CLRSETBITS_LE32(REG, MASK, VAL) WRITE_REG(REG, \
> + (READ_REG(REG) & ~(MASK)) | (VAL))
> +
> +#else
> +#define GPIO_VER 1
> +#define READ_REG(REG) readl(REG)
> +#define WRITE_REG(REG, VAL) writel(VAL, REG)
> +#define CLRBITS_LE32(REG, MASK) clrbits_le32(REG, MASK)
> +#define SETBITS_LE32(REG, MASK) setbits_le32(REG, MASK)
> +#define CLRSETBITS_LE32(REG, MASK, VAL) clrsetbits_le32(REG, MASK, VAL)
> +#endif
> +
> struct rockchip_gpio_priv {
> struct rockchip_gpio_regs *regs;
> struct udevice *pinctrl;
> @@ -35,7 +68,7 @@ static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset)
> struct rockchip_gpio_priv *priv = dev_get_priv(dev);
> struct rockchip_gpio_regs *regs = priv->regs;
>
> - clrbits_le32(®s->swport_ddr, OFFSET_TO_BIT(offset));
> + CLRBITS_LE32(®s->swport_ddr, OFFSET_TO_BIT(offset));
>
> return 0;
> }
> @@ -47,8 +80,8 @@ static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset,
> struct rockchip_gpio_regs *regs = priv->regs;
> int mask = OFFSET_TO_BIT(offset);
>
> - clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0);
> - setbits_le32(®s->swport_ddr, mask);
> + CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0);
> + SETBITS_LE32(®s->swport_ddr, mask);
>
> return 0;
> }
> @@ -68,7 +101,7 @@ static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
> struct rockchip_gpio_regs *regs = priv->regs;
> int mask = OFFSET_TO_BIT(offset);
>
> - clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0);
> + CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0);
>
> return 0;
> }
> @@ -86,14 +119,14 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
> ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
> if (ret)
> return ret;
> - is_output = readl(®s->swport_ddr) & OFFSET_TO_BIT(offset);
> + is_output = READ_REG(®s->swport_ddr) & OFFSET_TO_BIT(offset);
>
> return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
> #endif
> }
>
> /* Simple SPL interface to GPIOs */
> -#ifdef CONFIG_SPL_BUILD
> +#if defined(CONFIG_SPL_BUILD) && (GPIO_VER == 1)
>
> enum {
> PULL_NONE_1V8 = 0,
> @@ -143,7 +176,7 @@ static int rockchip_gpio_probe(struct udevice *dev)
> struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> struct rockchip_gpio_priv *priv = dev_get_priv(dev);
> struct ofnode_phandle_args args;
> - char *end;
> + char *end = NULL;
> int ret;
>
> priv->regs = dev_read_addr_ptr(dev);
> diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
> index 9884355473..90461ae881 100644
> --- a/drivers/pinctrl/rockchip/Makefile
> +++ b/drivers/pinctrl/rockchip/Makefile
> @@ -14,5 +14,6 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o
> obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
> obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
> +obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
> obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
> obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o
> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
> new file mode 100644
> index 0000000000..dce1c1e7ee
> --- /dev/null
> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
> @@ -0,0 +1,453 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2020 Rockchip Electronics Co., Ltd
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <dm/pinctrl.h>
> +#include <regmap.h>
> +#include <syscon.h>
+#include <dt-bindings/pinctrl/rockchip.h>
--
FUKAUMI Naoki
> +
> +#include "pinctrl-rockchip.h"
> +
> +static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
> + /* CAN0 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)),
> + /* CAN0 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)),
> + /* CAN1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)),
> + /* CAN1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)),
> + /* CAN2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)),
> + /* CAN2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)),
> + /* EDPDP_HPDIN IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)),
> + /* EDPDP_HPDIN IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)),
> + /* GMAC1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 0)),
> + /* GMAC1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PA7, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 1)),
> + /* HDMITX IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PD1, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 0)),
> + /* HDMITX IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO0, RK_PC7, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 1)),
> + /* I2C2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PB6, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 0)),
> + /* I2C2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PB4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 1)),
> + /* I2C3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA0, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(0, 0, 0)),
> + /* I2C3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(0, 0, 1)),
> + /* I2C4 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PB2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(2, 2, 0)),
> + /* I2C4 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)),
> + /* I2C5 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)),
> + /* I2C5 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)),
> + /* PWM4 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)),
> + /* PWM4 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)),
> + /* PWM5 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)),
> + /* PWM5 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)),
> + /* PWM6 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)),
> + /* PWM6 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)),
> + /* PWM7 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)),
> + /* PWM7 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)),
> + /* PWM8 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)),
> + /* PWM8 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)),
> + /* PWM9 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)),
> + /* PWM9 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)),
> + /* PWM10 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)),
> + /* PWM10 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)),
> + /* PWM11 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)),
> + /* PWM11 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)),
> + /* PWM12 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)),
> + /* PWM12 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)),
> + /* PWM13 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)),
> + /* PWM13 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)),
> + /* PWM14 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)),
> + /* PWM14 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)),
> + /* PWM15 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)),
> + /* PWM15 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)),
> + /* SDMMC2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)),
> + /* SDMMC2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)),
> + /* SPI0 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)),
> + /* SPI0 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(0, 0, 1)),
> + /* SPI1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PB5, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 0)),
> + /* SPI1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 1)),
> + /* SPI2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(4, 4, 0)),
> + /* SPI2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(4, 4, 1)),
> + /* SPI3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)),
> + /* SPI3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)),
> + /* UART1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)),
> + /* UART1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)),
> + /* UART2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)),
> + /* UART2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)),
> + /* UART3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)),
> + /* UART3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(12, 12, 1)),
> + /* UART4 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(14, 14, 0)),
> + /* UART4 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(14, 14, 1)),
> + /* UART5 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PA2, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(0, 0, 0)),
> + /* UART5 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(0, 0, 1)),
> + /* UART6 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PA4, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 0)),
> + /* UART6 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)),
> + /* UART7 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)),
> + /* UART7 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)),
> + /* UART7 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)),
> + /* UART8 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)),
> + /* UART8 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)),
> + /* UART9 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)),
> + /* UART9 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 1)),
> + /* UART9 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO4, RK_PA4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 2)),
> + /* I2S1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(11, 10, 0)),
> + /* I2S1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(11, 10, 1)),
> + /* I2S1 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(11, 10, 2)),
> + /* I2S2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(12, 12, 0)),
> + /* I2S2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)),
> + /* I2S3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)),
> + /* I2S3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)),
> + /* PDM IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)),
> + /* PDM IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)),
> + /* PCIE20 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)),
> + /* PCIE20 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)),
> + /* PCIE20 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)),
> + /* PCIE30X1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(5, 4, 0)),
> + /* PCIE30X1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 1)),
> + /* PCIE30X1 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 2)),
> + /* PCIE30X2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PA6, RK_FUNC_2, 0x0314, RK_GENMASK_VAL(7, 6, 0)),
> + /* PCIE30X2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 1)),
> + /* PCIE30X2 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 2)),
> +};
> +
> +static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int iomux_num = (pin / 8);
> + struct regmap *regmap;
> + int reg, ret, mask;
> + u8 bit;
> + u32 data;
> +
> + debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
> +
> + if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
> + regmap = priv->regmap_pmu;
> + else
> + regmap = priv->regmap_base;
> +
> + reg = bank->iomux[iomux_num].offset;
> + if ((pin % 8) >= 4)
> + reg += 0x4;
> + bit = (pin % 4) * 4;
> + mask = 0xf;
> +
> + data = (mask << (bit + 16));
> + data |= (mux & mask) << bit;
> + ret = regmap_write(regmap, reg, data);
> +
> + return ret;
> +}
> +
> +#define RK3568_PULL_PMU_OFFSET 0x20
> +#define RK3568_PULL_GRF_OFFSET 0x80
> +#define RK3568_PULL_BITS_PER_PIN 2
> +#define RK3568_PULL_PINS_PER_REG 8
> +#define RK3568_PULL_BANK_STRIDE 0x10
> +
> +static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *info = bank->priv;
> +
> + if (bank->bank_num == 0) {
> + *regmap = info->regmap_pmu;
> + *reg = RK3568_PULL_PMU_OFFSET;
> + *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
> + } else {
> + *regmap = info->regmap_base;
> + *reg = RK3568_PULL_GRF_OFFSET;
> + *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
> + *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
> + *bit *= RK3568_PULL_BITS_PER_PIN;
> +}
> +
> +#define RK3568_DRV_PMU_OFFSET 0x70
> +#define RK3568_DRV_GRF_OFFSET 0x200
> +#define RK3568_DRV_BITS_PER_PIN 8
> +#define RK3568_DRV_PINS_PER_REG 2
> +#define RK3568_DRV_BANK_STRIDE 0x40
> +
> +static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *info = bank->priv;
> +
> + /* The first 32 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = info->regmap_pmu;
> + *reg = RK3568_DRV_PMU_OFFSET;
> + } else {
> + *regmap = info->regmap_base;
> + *reg = RK3568_DRV_GRF_OFFSET;
> + *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
> + *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
> + *bit *= RK3568_DRV_BITS_PER_PIN;
> +}
> +
> +#define RK3568_SCHMITT_BITS_PER_PIN 2
> +#define RK3568_SCHMITT_PINS_PER_REG 8
> +#define RK3568_SCHMITT_BANK_STRIDE 0x10
> +#define RK3568_SCHMITT_GRF_OFFSET 0xc0
> +#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
> +
> +static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *info = bank->priv;
> +
> + if (bank->bank_num == 0) {
> + *regmap = info->regmap_pmu;
> + *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
> + } else {
> + *regmap = info->regmap_base;
> + *reg = RK3568_SCHMITT_GRF_OFFSET;
> + *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
> + *bit *= RK3568_SCHMITT_BITS_PER_PIN;
> +
> + return 0;
> +}
> +
> +static int rk3568_set_pull(struct rockchip_pin_bank *bank,
> + int pin_num, int pull)
> +{
> + struct regmap *regmap;
> + int reg, ret;
> + u8 bit, type;
> + u32 data;
> +
> + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
> + return -EOPNOTSUPP;
> +
> + rk3568_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> + type = bank->pull_type[pin_num / 8];
> + ret = rockchip_translate_pull_value(type, pull);
> + if (ret < 0) {
> + debug("unsupported pull setting %d\n", pull);
> + return ret;
> + }
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
> +
> + data |= (ret << bit);
> + ret = regmap_write(regmap, reg, data);
> +
> + return ret;
> +}
> +
> +static int rk3568_set_drive(struct rockchip_pin_bank *bank,
> + int pin_num, int strength)
> +{
> + struct regmap *regmap;
> + int reg;
> + u32 data;
> + u8 bit;
> + int drv = (1 << (strength + 1)) - 1;
> + int ret = 0;
> +
> + rk3568_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16);
> + data |= (drv << bit);
> +
> + ret = regmap_write(regmap, reg, data);
> + if (ret)
> + return ret;
> +
> + if (bank->bank_num == 1 && pin_num == 21)
> + reg = 0x0840;
> + else if (bank->bank_num == 2 && pin_num == 2)
> + reg = 0x0844;
> + else if (bank->bank_num == 2 && pin_num == 8)
> + reg = 0x0848;
> + else if (bank->bank_num == 3 && pin_num == 0)
> + reg = 0x084c;
> + else if (bank->bank_num == 3 && pin_num == 6)
> + reg = 0x0850;
> + else if (bank->bank_num == 4 && pin_num == 0)
> + reg = 0x0854;
> + else
> + return 0;
> +
> + data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16;
> + data |= drv;
> +
> + return regmap_write(regmap, reg, data);
> +}
> +
> +static int rk3568_set_schmitt(struct rockchip_pin_bank *bank,
> + int pin_num, int enable)
> +{
> + struct regmap *regmap;
> + int reg;
> + u32 data;
> + u8 bit;
> +
> + rk3568_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
> + data |= (enable << bit);
> +
> + return regmap_write(regmap, reg, data);
> +}
> +
> +static struct rockchip_pin_bank rk3568_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
> + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
> + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
> + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> +};
> +
> +static const struct rockchip_pin_ctrl rk3568_pin_ctrl = {
> + .pin_banks = rk3568_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
> + .nr_pins = 160,
> + .grf_mux_offset = 0x0,
> + .pmu_mux_offset = 0x0,
> + .iomux_routes = rk3568_mux_route_data,
> + .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
> + .set_mux = rk3568_set_mux,
> + .set_pull = rk3568_set_pull,
> + .set_drive = rk3568_set_drive,
> + .set_schmitt = rk3568_set_schmitt,
> +};
> +
> +static const struct udevice_id rk3568_pinctrl_ids[] = {
> + {
> + .compatible = "rockchip,rk3568-pinctrl",
> + .data = (ulong)&rk3568_pin_ctrl
> + },
> + { }
> +};
> +
> +U_BOOT_DRIVER(pinctrl_rk3568) = {
> + .name = "rockchip_rk3568_pinctrl",
> + .id = UCLASS_PINCTRL,
> + .of_match = rk3568_pinctrl_ids,
> + .priv_auto = sizeof(struct rockchip_pinctrl_priv),
> + .ops = &rockchip_pinctrl_ops,
> +#if !IS_ENABLED(CONFIG_OF_PLATDATA)
> + .bind = dm_scan_fdt_dev,
> +#endif
> + .probe = rockchip_pinctrl_probe,
> +};
> diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
> index d9d61fdb72..1481c1e51c 100644
> --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
> +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
> @@ -433,7 +433,7 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
> int prop_len, param;
> const u32 *data;
> ofnode node;
> -#ifdef CONFIG_OF_LIVE
> +#if CONFIG_IS_ENABLED(OF_LIVE)
> const struct device_node *np;
> struct property *pp;
> #else
> @@ -473,7 +473,7 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
> node = ofnode_get_by_phandle(conf);
> if (!ofnode_valid(node))
> return -ENODEV;
> -#ifdef CONFIG_OF_LIVE
> +#if CONFIG_IS_ENABLED(OF_LIVE)
> np = ofnode_to_np(node);
> for (pp = np->properties; pp; pp = pp->next) {
> prop_name = pp->name;
> @@ -548,13 +548,15 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d
>
> /* preset iomux offset value, set new start value */
> if (iom->offset >= 0) {
> - if (iom->type & IOMUX_SOURCE_PMU)
> + if ((iom->type & IOMUX_SOURCE_PMU) || \
> + (iom->type & IOMUX_L_SOURCE_PMU))
> pmu_offs = iom->offset;
> else
> grf_offs = iom->offset;
> } else { /* set current iomux offset */
> - iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
> - pmu_offs : grf_offs;
> + iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
> + (iom->type & IOMUX_L_SOURCE_PMU)) ?
> + pmu_offs : grf_offs;
> }
>
> /* preset drv offset value, set new start value */
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 4/9] arm64: dts: rockchip: Sync rk356x from Linux main
2023-02-15 18:44 ` Jonas Karlman
@ 2023-02-22 7:32 ` Kever Yang
0 siblings, 0 replies; 33+ messages in thread
From: Kever Yang @ 2023-02-22 7:32 UTC (permalink / raw)
To: Jonas Karlman, Chris Morgan, u-boot
Cc: heiko, sjg, philipp.tomsich, chenjh, pgwipeout, heiko.stuebner,
Chris Morgan
Hi Chris,
On 2023/2/16 02:44, Jonas Karlman wrote:
> On 2023-02-13 23:27, Chris Morgan wrote:
>> From: Chris Morgan <macromorgan@hotmail.com>
>>
>> Sync rk3566 and rk3568 from the mainline Linux kernel (6.2-rc2 as of
>> this writing).
>>
>> Note that this will rename the rk3568-evb to rk3568-evb1-v10.
> Is the rename and sync of evb-rk3568 necessary for your use case?
>
> I tend to abuse the evb variants as "minimal" soc defconfig. They
> usually contain minimal needed to boot any board following the reference
> design from sd or emmc.
>
> Using the current evb-rk3568_defconfig and rk3568-evb.dts I can boot,
> load atf and start linux on all my rk3566/rk3568 boards. Not sure that
> will continue to be possible after these changes.
There are many SBC boards copy the core logic from evb, so the
evb-rk3568 config can
make many boards boot. We can keep evb-rk3568_defconfig before there in
another
rk3568 evb available on the tree.
For others:
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> Regards,
> Jonas
>
>> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
>> ---
>> arch/arm/dts/Makefile | 2 +-
>> arch/arm/dts/rk3568-evb.dts | 79 --
>> ...-boot.dtsi => rk3568-evb1-v10-u-boot.dtsi} | 0
>> arch/arm/dts/rk3568-evb1-v10.dts | 692 ++++++++++++++++++
>> arch/arm/dts/rk3568.dtsi | 122 +++
>> arch/arm/dts/rk356x.dtsi | 182 ++++-
>> ...68_defconfig => evb1-v10-rk3568_defconfig} | 4 +-
>> 7 files changed, 985 insertions(+), 96 deletions(-)
>> delete mode 100644 arch/arm/dts/rk3568-evb.dts
>> rename arch/arm/dts/{rk3568-evb-u-boot.dtsi => rk3568-evb1-v10-u-boot.dtsi} (100%)
>> create mode 100644 arch/arm/dts/rk3568-evb1-v10.dts
>> rename configs/{evb-rk3568_defconfig => evb1-v10-rk3568_defconfig} (94%)
>>
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index 9d647b9639..56e0543bd2 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -165,7 +165,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
>> rk3399pro-rock-pi-n10.dtb
>>
>> dtb-$(CONFIG_ROCKCHIP_RK3568) += \
>> - rk3568-evb.dtb
>> + rk3568-evb1-v10.dtb
>>
>> dtb-$(CONFIG_ROCKCHIP_RV1108) += \
>> rv1108-elgin-r1.dtb \
>> diff --git a/arch/arm/dts/rk3568-evb.dts b/arch/arm/dts/rk3568-evb.dts
>> deleted file mode 100644
>> index 6978655709..0000000000
>> --- a/arch/arm/dts/rk3568-evb.dts
>> +++ /dev/null
>> @@ -1,79 +0,0 @@
>> -// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> -/*
>> - * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
>> - *
>> - */
>> -
>> -/dts-v1/;
>> -#include <dt-bindings/gpio/gpio.h>
>> -#include <dt-bindings/pinctrl/rockchip.h>
>> -#include "rk3568.dtsi"
>> -
>> -/ {
>> - model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
>> - compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
>> -
>> - chosen: chosen {
>> - stdout-path = "serial2:1500000n8";
>> - };
>> -
>> - dc_12v: dc-12v {
>> - compatible = "regulator-fixed";
>> - regulator-name = "dc_12v";
>> - regulator-always-on;
>> - regulator-boot-on;
>> - regulator-min-microvolt = <12000000>;
>> - regulator-max-microvolt = <12000000>;
>> - };
>> -
>> - vcc3v3_sys: vcc3v3-sys {
>> - compatible = "regulator-fixed";
>> - regulator-name = "vcc3v3_sys";
>> - regulator-always-on;
>> - regulator-boot-on;
>> - regulator-min-microvolt = <3300000>;
>> - regulator-max-microvolt = <3300000>;
>> - vin-supply = <&dc_12v>;
>> - };
>> -
>> - vcc5v0_sys: vcc5v0-sys {
>> - compatible = "regulator-fixed";
>> - regulator-name = "vcc5v0_sys";
>> - regulator-always-on;
>> - regulator-boot-on;
>> - regulator-min-microvolt = <5000000>;
>> - regulator-max-microvolt = <5000000>;
>> - vin-supply = <&dc_12v>;
>> - };
>> -
>> - vcc3v3_lcd0_n: vcc3v3-lcd0-n {
>> - compatible = "regulator-fixed";
>> - regulator-name = "vcc3v3_lcd0_n";
>> - regulator-boot-on;
>> -
>> - regulator-state-mem {
>> - regulator-off-in-suspend;
>> - };
>> - };
>> -
>> - vcc3v3_lcd1_n: vcc3v3-lcd1-n {
>> - compatible = "regulator-fixed";
>> - regulator-name = "vcc3v3_lcd1_n";
>> - regulator-boot-on;
>> -
>> - regulator-state-mem {
>> - regulator-off-in-suspend;
>> - };
>> - };
>> -};
>> -
>> -&sdhci {
>> - bus-width = <8>;
>> - max-frequency = <200000000>;
>> - non-removable;
>> - status = "okay";
>> -};
>> -
>> -&uart2 {
>> - status = "okay";
>> -};
>> diff --git a/arch/arm/dts/rk3568-evb-u-boot.dtsi b/arch/arm/dts/rk3568-evb1-v10-u-boot.dtsi
>> similarity index 100%
>> rename from arch/arm/dts/rk3568-evb-u-boot.dtsi
>> rename to arch/arm/dts/rk3568-evb1-v10-u-boot.dtsi
>> diff --git a/arch/arm/dts/rk3568-evb1-v10.dts b/arch/arm/dts/rk3568-evb1-v10.dts
>> new file mode 100644
>> index 0000000000..674792567f
>> --- /dev/null
>> +++ b/arch/arm/dts/rk3568-evb1-v10.dts
>> @@ -0,0 +1,692 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
>> + *
>> + */
>> +
>> +/dts-v1/;
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/leds/common.h>
>> +#include <dt-bindings/pinctrl/rockchip.h>
>> +#include <dt-bindings/soc/rockchip,vop2.h>
>> +#include "rk3568.dtsi"
>> +
>> +/ {
>> + model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
>> + compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
>> +
>> + aliases {
>> + ethernet0 = &gmac0;
>> + ethernet1 = &gmac1;
>> + mmc0 = &sdmmc0;
>> + mmc1 = &sdhci;
>> + };
>> +
>> + chosen: chosen {
>> + stdout-path = "serial2:1500000n8";
>> + };
>> +
>> + dc_12v: dc-12v {
>> + compatible = "regulator-fixed";
>> + regulator-name = "dc_12v";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <12000000>;
>> + regulator-max-microvolt = <12000000>;
>> + };
>> +
>> + hdmi-con {
>> + compatible = "hdmi-connector";
>> + type = "a";
>> +
>> + port {
>> + hdmi_con_in: endpoint {
>> + remote-endpoint = <&hdmi_out_con>;
>> + };
>> + };
>> + };
>> +
>> + leds {
>> + compatible = "gpio-leds";
>> +
>> + led_work: led-0 {
>> + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
>> + function = LED_FUNCTION_HEARTBEAT;
>> + color = <LED_COLOR_ID_BLUE>;
>> + linux,default-trigger = "heartbeat";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&led_work_en>;
>> + };
>> + };
>> +
>> + rk809-sound {
>> + compatible = "simple-audio-card";
>> + simple-audio-card,format = "i2s";
>> + simple-audio-card,name = "Analog RK809";
>> + simple-audio-card,mclk-fs = <256>;
>> +
>> + simple-audio-card,cpu {
>> + sound-dai = <&i2s1_8ch>;
>> + };
>> + simple-audio-card,codec {
>> + sound-dai = <&rk809>;
>> + };
>> + };
>> +
>> + vcc3v3_sys: vcc3v3-sys {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vcc3v3_sys";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + vin-supply = <&dc_12v>;
>> + };
>> +
>> + vcc5v0_sys: vcc5v0-sys {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vcc5v0_sys";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + vin-supply = <&dc_12v>;
>> + };
>> +
>> + vcc5v0_usb: vcc5v0-usb {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vcc5v0_usb";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + vin-supply = <&dc_12v>;
>> + };
>> +
>> + vcc5v0_usb_host: vcc5v0-usb-host {
>> + compatible = "regulator-fixed";
>> + enable-active-high;
>> + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&vcc5v0_usb_host_en>;
>> + regulator-name = "vcc5v0_usb_host";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + vin-supply = <&vcc5v0_usb>;
>> + };
>> +
>> + vcc5v0_usb_otg: vcc5v0-usb-otg {
>> + compatible = "regulator-fixed";
>> + enable-active-high;
>> + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&vcc5v0_usb_otg_en>;
>> + regulator-name = "vcc5v0_usb_otg";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + vin-supply = <&vcc5v0_usb>;
>> + };
>> +
>> + vcc3v3_lcd0_n: vcc3v3-lcd0-n {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vcc3v3_lcd0_n";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + enable-active-high;
>> + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
>> + vin-supply = <&vcc3v3_sys>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&vcc3v3_lcd0_n_en>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vcc3v3_lcd1_n: vcc3v3-lcd1-n {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vcc3v3_lcd1_n";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + enable-active-high;
>> + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
>> + vin-supply = <&vcc3v3_sys>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&vcc3v3_lcd1_n_en>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +};
>> +
>> +&combphy0 {
>> + status = "okay";
>> +};
>> +
>> +&combphy1 {
>> + status = "okay";
>> +};
>> +
>> +&cpu0 {
>> + cpu-supply = <&vdd_cpu>;
>> +};
>> +
>> +&cpu1 {
>> + cpu-supply = <&vdd_cpu>;
>> +};
>> +
>> +&cpu2 {
>> + cpu-supply = <&vdd_cpu>;
>> +};
>> +
>> +&cpu3 {
>> + cpu-supply = <&vdd_cpu>;
>> +};
>> +
>> +&gmac0 {
>> + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
>> + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
>> + assigned-clock-rates = <0>, <125000000>;
>> + clock_in_out = "output";
>> + phy-handle = <&rgmii_phy0>;
>> + phy-mode = "rgmii-id";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&gmac0_miim
>> + &gmac0_tx_bus2
>> + &gmac0_rx_bus2
>> + &gmac0_rgmii_clk
>> + &gmac0_rgmii_bus>;
>> + status = "okay";
>> +};
>> +
>> +&gmac1 {
>> + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
>> + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
>> + assigned-clock-rates = <0>, <125000000>;
>> + clock_in_out = "output";
>> + phy-handle = <&rgmii_phy1>;
>> + phy-mode = "rgmii-id";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&gmac1m1_miim
>> + &gmac1m1_tx_bus2
>> + &gmac1m1_rx_bus2
>> + &gmac1m1_rgmii_clk
>> + &gmac1m1_rgmii_bus>;
>> + status = "okay";
>> +};
>> +
>> +&gpu {
>> + mali-supply = <&vdd_gpu>;
>> + status = "okay";
>> +};
>> +
>> +&hdmi {
>> + avdd-0v9-supply = <&vdda0v9_image>;
>> + avdd-1v8-supply = <&vcca1v8_image>;
>> + status = "okay";
>> +};
>> +
>> +&hdmi_in {
>> + hdmi_in_vp0: endpoint {
>> + remote-endpoint = <&vp0_out_hdmi>;
>> + };
>> +};
>> +
>> +&hdmi_out {
>> + hdmi_out_con: endpoint {
>> + remote-endpoint = <&hdmi_con_in>;
>> + };
>> +};
>> +
>> +&hdmi_sound {
>> + status = "okay";
>> +};
>> +
>> +&i2c0 {
>> + status = "okay";
>> +
>> + vdd_cpu: regulator@1c {
>> + compatible = "tcs,tcs4525";
>> + reg = <0x1c>;
>> + fcs,suspend-voltage-selector = <1>;
>> + regulator-name = "vdd_cpu";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <800000>;
>> + regulator-max-microvolt = <1150000>;
>> + regulator-ramp-delay = <2300>;
>> + vin-supply = <&vcc5v0_sys>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + rk809: pmic@20 {
>> + compatible = "rockchip,rk809";
>> + reg = <0x20>;
>> + interrupt-parent = <&gpio0>;
>> + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
>> + assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
>> + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
>> + #clock-cells = <1>;
>> + clock-names = "mclk";
>> + clocks = <&cru I2S1_MCLKOUT_TX>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
>> + rockchip,system-power-controller;
>> + #sound-dai-cells = <0>;
>> + vcc1-supply = <&vcc3v3_sys>;
>> + vcc2-supply = <&vcc3v3_sys>;
>> + vcc3-supply = <&vcc3v3_sys>;
>> + vcc4-supply = <&vcc3v3_sys>;
>> + vcc5-supply = <&vcc3v3_sys>;
>> + vcc6-supply = <&vcc3v3_sys>;
>> + vcc7-supply = <&vcc3v3_sys>;
>> + vcc8-supply = <&vcc3v3_sys>;
>> + vcc9-supply = <&vcc3v3_sys>;
>> + wakeup-source;
>> +
>> + regulators {
>> + vdd_logic: DCDC_REG1 {
>> + regulator-name = "vdd_logic";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-init-microvolt = <900000>;
>> + regulator-initial-mode = <0x2>;
>> + regulator-min-microvolt = <500000>;
>> + regulator-max-microvolt = <1350000>;
>> + regulator-ramp-delay = <6001>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vdd_gpu: DCDC_REG2 {
>> + regulator-name = "vdd_gpu";
>> + regulator-always-on;
>> + regulator-init-microvolt = <900000>;
>> + regulator-initial-mode = <0x2>;
>> + regulator-min-microvolt = <500000>;
>> + regulator-max-microvolt = <1350000>;
>> + regulator-ramp-delay = <6001>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vcc_ddr: DCDC_REG3 {
>> + regulator-name = "vcc_ddr";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-initial-mode = <0x2>;
>> +
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + };
>> + };
>> +
>> + vdd_npu: DCDC_REG4 {
>> + regulator-name = "vdd_npu";
>> + regulator-init-microvolt = <900000>;
>> + regulator-initial-mode = <0x2>;
>> + regulator-min-microvolt = <500000>;
>> + regulator-max-microvolt = <1350000>;
>> + regulator-ramp-delay = <6001>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vcc_1v8: DCDC_REG5 {
>> + regulator-name = "vcc_1v8";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vdda0v9_image: LDO_REG1 {
>> + regulator-name = "vdda0v9_image";
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <900000>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vdda_0v9: LDO_REG2 {
>> + regulator-name = "vdda_0v9";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <900000>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vdda0v9_pmu: LDO_REG3 {
>> + regulator-name = "vdda0v9_pmu";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <900000>;
>> +
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + regulator-suspend-microvolt = <900000>;
>> + };
>> + };
>> +
>> + vccio_acodec: LDO_REG4 {
>> + regulator-name = "vccio_acodec";
>> + regulator-always-on;
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vccio_sd: LDO_REG5 {
>> + regulator-name = "vccio_sd";
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <3300000>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vcc3v3_pmu: LDO_REG6 {
>> + regulator-name = "vcc3v3_pmu";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> +
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + regulator-suspend-microvolt = <3300000>;
>> + };
>> + };
>> +
>> + vcca_1v8: LDO_REG7 {
>> + regulator-name = "vcca_1v8";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vcca1v8_pmu: LDO_REG8 {
>> + regulator-name = "vcca1v8_pmu";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> +
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + regulator-suspend-microvolt = <1800000>;
>> + };
>> + };
>> +
>> + vcca1v8_image: LDO_REG9 {
>> + regulator-name = "vcca1v8_image";
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vcc_3v3: SWITCH_REG1 {
>> + regulator-name = "vcc_3v3";
>> + regulator-always-on;
>> + regulator-boot-on;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vcc3v3_sd: SWITCH_REG2 {
>> + regulator-name = "vcc3v3_sd";
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> + };
>> +
>> + codec {
>> + mic-in-differential;
>> + };
>> + };
>> +};
>> +
>> +&i2c1 {
>> + status = "okay";
>> +
>> + touchscreen0: goodix@14 {
>> + compatible = "goodix,gt1151";
>> + reg = <0x14>;
>> + interrupt-parent = <&gpio0>;
>> + interrupts = <RK_PB5 IRQ_TYPE_EDGE_FALLING>;
>> + AVDD28-supply = <&vcc3v3_lcd0_n>;
>> + irq-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&touch_int &touch_rst>;
>> + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
>> + VDDIO-supply = <&vcc3v3_lcd0_n>;
>> + };
>> +};
>> +
>> +&i2s0_8ch {
>> + status = "okay";
>> +};
>> +
>> +&i2s1_8ch {
>> + rockchip,trcm-sync-tx-only;
>> + status = "okay";
>> +};
>> +
>> +&mdio0 {
>> + rgmii_phy0: ethernet-phy@0 {
>> + compatible = "ethernet-phy-ieee802.3-c22";
>> + reg = <0x0>;
>> + reset-assert-us = <20000>;
>> + reset-deassert-us = <100000>;
>> + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
>> + };
>> +};
>> +
>> +&mdio1 {
>> + rgmii_phy1: ethernet-phy@0 {
>> + compatible = "ethernet-phy-ieee802.3-c22";
>> + reg = <0x0>;
>> + reset-assert-us = <20000>;
>> + reset-deassert-us = <100000>;
>> + reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
>> + };
>> +};
>> +
>> +&pinctrl {
>> + display {
>> + vcc3v3_lcd0_n_en: vcc3v3_lcd0_n_en {
>> + rockchip,pins = <0 RK_PC7 0 &pcfg_pull_none>;
>> + };
>> + vcc3v3_lcd1_n_en: vcc3v3_lcd1_n_en {
>> + rockchip,pins = <0 RK_PC5 0 &pcfg_pull_none>;
>> + };
>> + };
>> +
>> + leds {
>> + led_work_en: led_work_en {
>> + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
>> + };
>> + };
>> +
>> + pmic {
>> + pmic_int: pmic_int {
>> + rockchip,pins =
>> + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
>> + };
>> + };
>> +
>> + touchscreen {
>> + touch_int: touch_int {
>> + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
>> + };
>> + touch_rst: touch_rst {
>> + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
>> + };
>> + };
>> +
>> + usb {
>> + vcc5v0_usb_host_en: vcc5v0_usb_host_en {
>> + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
>> + };
>> + vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
>> + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
>> + };
>> + };
>> +};
>> +
>> +&pmu_io_domains {
>> + pmuio1-supply = <&vcc3v3_pmu>;
>> + pmuio2-supply = <&vcc3v3_pmu>;
>> + vccio1-supply = <&vccio_acodec>;
>> + vccio2-supply = <&vcc_1v8>;
>> + vccio3-supply = <&vccio_sd>;
>> + vccio4-supply = <&vcc_1v8>;
>> + vccio5-supply = <&vcc_3v3>;
>> + vccio6-supply = <&vcc_1v8>;
>> + vccio7-supply = <&vcc_3v3>;
>> + status = "okay";
>> +};
>> +
>> +&saradc {
>> + vref-supply = <&vcca_1v8>;
>> + status = "okay";
>> +};
>> +
>> +&sdhci {
>> + bus-width = <8>;
>> + max-frequency = <200000000>;
>> + non-removable;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
>> + status = "okay";
>> +};
>> +
>> +&sdmmc0 {
>> + bus-width = <4>;
>> + cap-sd-highspeed;
>> + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
>> + disable-wp;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
>> + sd-uhs-sdr104;
>> + vmmc-supply = <&vcc3v3_sd>;
>> + vqmmc-supply = <&vccio_sd>;
>> + status = "okay";
>> +};
>> +
>> +&tsadc {
>> + rockchip,hw-tshut-mode = <1>;
>> + rockchip,hw-tshut-polarity = <0>;
>> + status = "okay";
>> +};
>> +
>> +&uart2 {
>> + status = "okay";
>> +};
>> +
>> +&usb_host0_ehci {
>> + status = "okay";
>> +};
>> +
>> +&usb_host0_ohci {
>> + status = "okay";
>> +};
>> +
>> +&usb_host0_xhci {
>> + extcon = <&usb2phy0>;
>> + status = "okay";
>> +};
>> +
>> +&usb_host1_ehci {
>> + status = "okay";
>> +};
>> +
>> +&usb_host1_ohci {
>> + status = "okay";
>> +};
>> +
>> +&usb_host1_xhci {
>> + status = "okay";
>> +};
>> +
>> +&usb2phy0 {
>> + status = "okay";
>> +};
>> +
>> +&usb2phy0_host {
>> + phy-supply = <&vcc5v0_usb_host>;
>> + status = "okay";
>> +};
>> +
>> +&usb2phy0_otg {
>> + phy-supply = <&vcc5v0_usb_otg>;
>> + status = "okay";
>> +};
>> +
>> +&usb2phy1 {
>> + status = "okay";
>> +};
>> +
>> +&usb2phy1_host {
>> + phy-supply = <&vcc5v0_usb_host>;
>> + status = "okay";
>> +};
>> +
>> +&usb2phy1_otg {
>> + phy-supply = <&vcc5v0_usb_host>;
>> + status = "okay";
>> +};
>> +
>> +&vop {
>> + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
>> + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
>> + status = "okay";
>> +};
>> +
>> +&vop_mmu {
>> + status = "okay";
>> +};
>> +
>> +&vp0 {
>> + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
>> + reg = <ROCKCHIP_VOP2_EP_HDMI0>;
>> + remote-endpoint = <&hdmi_in_vp0>;
>> + };
>> +};
>> diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi
>> index 2bdf8c7e97..ba67b58f05 100644
>> --- a/arch/arm/dts/rk3568.dtsi
>> +++ b/arch/arm/dts/rk3568.dtsi
>> @@ -42,6 +42,128 @@
>> reg = <0x0 0xfe190200 0x0 0x20>;
>> };
>>
>> + pcie30_phy_grf: syscon@fdcb8000 {
>> + compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
>> + reg = <0x0 0xfdcb8000 0x0 0x10000>;
>> + };
>> +
>> + pcie30phy: phy@fe8c0000 {
>> + compatible = "rockchip,rk3568-pcie3-phy";
>> + reg = <0x0 0xfe8c0000 0x0 0x20000>;
>> + #phy-cells = <0>;
>> + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
>> + <&cru PCLK_PCIE30PHY>;
>> + clock-names = "refclk_m", "refclk_n", "pclk";
>> + resets = <&cru SRST_PCIE30PHY>;
>> + reset-names = "phy";
>> + rockchip,phy-grf = <&pcie30_phy_grf>;
>> + status = "disabled";
>> + };
>> +
>> + pcie3x1: pcie@fe270000 {
>> + compatible = "rockchip,rk3568-pcie";
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + bus-range = <0x0 0xf>;
>> + clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
>> + <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
>> + <&cru CLK_PCIE30X1_AUX_NDFT>;
>> + clock-names = "aclk_mst", "aclk_slv",
>> + "aclk_dbi", "pclk", "aux";
>> + device_type = "pci";
>> + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "sys", "pmc", "msg", "legacy", "err";
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 7>;
>> + interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
>> + <0 0 0 2 &pcie3x1_intc 1>,
>> + <0 0 0 3 &pcie3x1_intc 2>,
>> + <0 0 0 4 &pcie3x1_intc 3>;
>> + linux,pci-domain = <1>;
>> + num-ib-windows = <6>;
>> + num-ob-windows = <2>;
>> + max-link-speed = <3>;
>> + msi-map = <0x0 &gic 0x1000 0x1000>;
>> + num-lanes = <1>;
>> + phys = <&pcie30phy>;
>> + phy-names = "pcie-phy";
>> + power-domains = <&power RK3568_PD_PIPE>;
>> + reg = <0x3 0xc0400000 0x0 0x00400000>,
>> + <0x0 0xfe270000 0x0 0x00010000>,
>> + <0x3 0x7f000000 0x0 0x01000000>;
>> + ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
>> + <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
>> + reg-names = "dbi", "apb", "config";
>> + resets = <&cru SRST_PCIE30X1_POWERUP>;
>> + reset-names = "pipe";
>> + /* bifurcation; lane1 when using 1+1 */
>> + status = "disabled";
>> +
>> + pcie3x1_intc: legacy-interrupt-controller {
>> + interrupt-controller;
>> + #address-cells = <0>;
>> + #interrupt-cells = <1>;
>> + interrupt-parent = <&gic>;
>> + interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
>> + };
>> + };
>> +
>> + pcie3x2: pcie@fe280000 {
>> + compatible = "rockchip,rk3568-pcie";
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + bus-range = <0x0 0xf>;
>> + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
>> + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
>> + <&cru CLK_PCIE30X2_AUX_NDFT>;
>> + clock-names = "aclk_mst", "aclk_slv",
>> + "aclk_dbi", "pclk", "aux";
>> + device_type = "pci";
>> + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "sys", "pmc", "msg", "legacy", "err";
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 7>;
>> + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
>> + <0 0 0 2 &pcie3x2_intc 1>,
>> + <0 0 0 3 &pcie3x2_intc 2>,
>> + <0 0 0 4 &pcie3x2_intc 3>;
>> + linux,pci-domain = <2>;
>> + num-ib-windows = <6>;
>> + num-ob-windows = <2>;
>> + max-link-speed = <3>;
>> + msi-map = <0x0 &gic 0x2000 0x1000>;
>> + num-lanes = <2>;
>> + phys = <&pcie30phy>;
>> + phy-names = "pcie-phy";
>> + power-domains = <&power RK3568_PD_PIPE>;
>> + reg = <0x3 0xc0800000 0x0 0x00400000>,
>> + <0x0 0xfe280000 0x0 0x00010000>,
>> + <0x3 0xbf000000 0x0 0x01000000>;
>> + ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
>> + <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
>> + reg-names = "dbi", "apb", "config";
>> + resets = <&cru SRST_PCIE30X2_POWERUP>;
>> + reset-names = "pipe";
>> + /* bifurcation; lane0 when using 1+1 */
>> + status = "disabled";
>> +
>> + pcie3x2_intc: legacy-interrupt-controller {
>> + interrupt-controller;
>> + #address-cells = <0>;
>> + #interrupt-cells = <1>;
>> + interrupt-parent = <&gic>;
>> + interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
>> + };
>> + };
>> +
>> gmac0: ethernet@fe2a0000 {
>> compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
>> reg = <0x0 0xfe2a0000 0x0 0x10000>;
>> diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi
>> index 319981c3e9..5706c3e24f 100644
>> --- a/arch/arm/dts/rk356x.dtsi
>> +++ b/arch/arm/dts/rk356x.dtsi
>> @@ -592,6 +592,46 @@
>> status = "disabled";
>> };
>>
>> + vpu: video-codec@fdea0400 {
>> + compatible = "rockchip,rk3568-vpu";
>> + reg = <0x0 0xfdea0000 0x0 0x800>;
>> + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
>> + clock-names = "aclk", "hclk";
>> + iommus = <&vdpu_mmu>;
>> + power-domains = <&power RK3568_PD_VPU>;
>> + };
>> +
>> + vdpu_mmu: iommu@fdea0800 {
>> + compatible = "rockchip,rk3568-iommu";
>> + reg = <0x0 0xfdea0800 0x0 0x40>;
>> + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
>> + clock-names = "aclk", "iface";
>> + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
>> + power-domains = <&power RK3568_PD_VPU>;
>> + #iommu-cells = <0>;
>> + };
>> +
>> + vepu: video-codec@fdee0000 {
>> + compatible = "rockchip,rk3568-vepu";
>> + reg = <0x0 0xfdee0000 0x0 0x800>;
>> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
>> + clock-names = "aclk", "hclk";
>> + iommus = <&vepu_mmu>;
>> + power-domains = <&power RK3568_PD_RGA>;
>> + };
>> +
>> + vepu_mmu: iommu@fdee0800 {
>> + compatible = "rockchip,rk3568-iommu";
>> + reg = <0x0 0xfdee0800 0x0 0x40>;
>> + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
>> + clock-names = "aclk", "iface";
>> + power-domains = <&power RK3568_PD_RGA>;
>> + #iommu-cells = <0>;
>> + };
>> +
>> sdmmc2: mmc@fe000000 {
>> compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
>> reg = <0x0 0xfe000000 0x0 0x4000>;
>> @@ -699,6 +739,62 @@
>> status = "disabled";
>> };
>>
>> + dsi0: dsi@fe060000 {
>> + compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
>> + reg = <0x00 0xfe060000 0x00 0x10000>;
>> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
>> + clock-names = "pclk", "hclk";
>> + clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
>> + phy-names = "dphy";
>> + phys = <&dsi_dphy0>;
>> + power-domains = <&power RK3568_PD_VO>;
>> + reset-names = "apb";
>> + resets = <&cru SRST_P_DSITX_0>;
>> + rockchip,grf = <&grf>;
>> + status = "disabled";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + dsi0_in: port@0 {
>> + reg = <0>;
>> + };
>> +
>> + dsi0_out: port@1 {
>> + reg = <1>;
>> + };
>> + };
>> + };
>> +
>> + dsi1: dsi@fe070000 {
>> + compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
>> + reg = <0x0 0xfe070000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
>> + clock-names = "pclk", "hclk";
>> + clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
>> + phy-names = "dphy";
>> + phys = <&dsi_dphy1>;
>> + power-domains = <&power RK3568_PD_VO>;
>> + reset-names = "apb";
>> + resets = <&cru SRST_P_DSITX_1>;
>> + rockchip,grf = <&grf>;
>> + status = "disabled";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + dsi1_in: port@0 {
>> + reg = <0>;
>> + };
>> +
>> + dsi1_out: port@1 {
>> + reg = <1>;
>> + };
>> + };
>> + };
>> +
>> hdmi: hdmi@fe0a0000 {
>> compatible = "rockchip,rk3568-dw-hdmi";
>> reg = <0x0 0xfe0a0000 0x0 0x20000>;
>> @@ -953,20 +1049,6 @@
>> status = "disabled";
>> };
>>
>> - spdif: spdif@fe460000 {
>> - compatible = "rockchip,rk3568-spdif";
>> - reg = <0x0 0xfe460000 0x0 0x1000>;
>> - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
>> - clock-names = "mclk", "hclk";
>> - clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
>> - dmas = <&dmac1 1>;
>> - dma-names = "tx";
>> - pinctrl-names = "default";
>> - pinctrl-0 = <&spdifm0_tx>;
>> - #sound-dai-cells = <0>;
>> - status = "disabled";
>> - };
>> -
>> i2s0_8ch: i2s@fe400000 {
>> compatible = "rockchip,rk3568-i2s-tdm";
>> reg = <0x0 0xfe400000 0x0 0x1000>;
>> @@ -1009,6 +1091,28 @@
>> status = "disabled";
>> };
>>
>> + i2s2_2ch: i2s@fe420000 {
>> + compatible = "rockchip,rk3568-i2s-tdm";
>> + reg = <0x0 0xfe420000 0x0 0x1000>;
>> + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
>> + assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
>> + assigned-clock-rates = <1188000000>;
>> + clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
>> + clock-names = "mclk_tx", "mclk_rx", "hclk";
>> + dmas = <&dmac1 4>, <&dmac1 5>;
>> + dma-names = "tx", "rx";
>> + resets = <&cru SRST_M_I2S2_2CH>;
>> + reset-names = "m";
>> + rockchip,grf = <&grf>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&i2s2m0_sclktx
>> + &i2s2m0_lrcktx
>> + &i2s2m0_sdi
>> + &i2s2m0_sdo>;
>> + #sound-dai-cells = <0>;
>> + status = "disabled";
>> + };
>> +
>> i2s3_2ch: i2s@fe430000 {
>> compatible = "rockchip,rk3568-i2s-tdm";
>> reg = <0x0 0xfe430000 0x0 0x1000>;
>> @@ -1046,6 +1150,20 @@
>> status = "disabled";
>> };
>>
>> + spdif: spdif@fe460000 {
>> + compatible = "rockchip,rk3568-spdif";
>> + reg = <0x0 0xfe460000 0x0 0x1000>;
>> + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
>> + clock-names = "mclk", "hclk";
>> + clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
>> + dmas = <&dmac1 1>;
>> + dma-names = "tx";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&spdifm0_tx>;
>> + #sound-dai-cells = <0>;
>> + status = "disabled";
>> + };
>> +
>> dmac0: dma-controller@fe530000 {
>> compatible = "arm,pl330", "arm,primecell";
>> reg = <0x0 0xfe530000 0x0 0x4000>;
>> @@ -1594,6 +1712,42 @@
>> status = "disabled";
>> };
>>
>> + csi_dphy: phy@fe870000 {
>> + compatible = "rockchip,rk3568-csi-dphy";
>> + reg = <0x0 0xfe870000 0x0 0x10000>;
>> + clocks = <&cru PCLK_MIPICSIPHY>;
>> + clock-names = "pclk";
>> + #phy-cells = <0>;
>> + resets = <&cru SRST_P_MIPICSIPHY>;
>> + reset-names = "apb";
>> + rockchip,grf = <&grf>;
>> + status = "disabled";
>> + };
>> +
>> + dsi_dphy0: mipi-dphy@fe850000 {
>> + compatible = "rockchip,rk3568-dsi-dphy";
>> + reg = <0x0 0xfe850000 0x0 0x10000>;
>> + clock-names = "ref", "pclk";
>> + clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
>> + #phy-cells = <0>;
>> + power-domains = <&power RK3568_PD_VO>;
>> + reset-names = "apb";
>> + resets = <&cru SRST_P_MIPIDSIPHY0>;
>> + status = "disabled";
>> + };
>> +
>> + dsi_dphy1: mipi-dphy@fe860000 {
>> + compatible = "rockchip,rk3568-dsi-dphy";
>> + reg = <0x0 0xfe860000 0x0 0x10000>;
>> + clock-names = "ref", "pclk";
>> + clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
>> + #phy-cells = <0>;
>> + power-domains = <&power RK3568_PD_VO>;
>> + reset-names = "apb";
>> + resets = <&cru SRST_P_MIPIDSIPHY1>;
>> + status = "disabled";
>> + };
>> +
>> usb2phy0: usb2phy@fe8a0000 {
>> compatible = "rockchip,rk3568-usb2phy";
>> reg = <0x0 0xfe8a0000 0x0 0x10000>;
>> diff --git a/configs/evb-rk3568_defconfig b/configs/evb1-v10-rk3568_defconfig
>> similarity index 94%
>> rename from configs/evb-rk3568_defconfig
>> rename to configs/evb1-v10-rk3568_defconfig
>> index a76d924d38..7ca1a35246 100644
>> --- a/configs/evb-rk3568_defconfig
>> +++ b/configs/evb1-v10-rk3568_defconfig
>> @@ -6,7 +6,7 @@ CONFIG_TEXT_BASE=0x00a00000
>> CONFIG_SPL_LIBCOMMON_SUPPORT=y
>> CONFIG_SPL_LIBGENERIC_SUPPORT=y
>> CONFIG_NR_DRAM_BANKS=2
>> -CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
>> +CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb1-v10"
>> CONFIG_ROCKCHIP_RK3568=y
>> CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
>> CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
>> @@ -23,7 +23,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
>> CONFIG_FIT=y
>> CONFIG_FIT_VERBOSE=y
>> CONFIG_SPL_LOAD_FIT=y
>> -CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
>> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb1-v10.dtb"
>> # CONFIG_DISPLAY_CPUINFO is not set
>> CONFIG_DISPLAY_BOARDINFO_LATE=y
>> CONFIG_SPL_MAX_SIZE=0x20000
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 6/9] rockchip: rk3568: enable automatic power savings
2023-02-13 22:27 ` [PATCH V2 6/9] rockchip: rk3568: enable automatic power savings Chris Morgan
@ 2023-02-22 7:34 ` Kever Yang
0 siblings, 0 replies; 33+ messages in thread
From: Kever Yang @ 2023-02-22 7:34 UTC (permalink / raw)
To: Chris Morgan, u-boot
Cc: heiko, sjg, philipp.tomsich, chenjh, pgwipeout, heiko.stuebner,
Chris Morgan
On 2023/2/14 06:27, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> It enables automatic clock gating on idle, disables the eDP phy by
> default, and sets the core pvtpll ring length. It is reported this
> lowers the temperature on at least one SoC by 7C.
>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/mach-rockchip/rk3568/rk3568.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
> index a2d59abc26..4a08820a09 100644
> --- a/arch/arm/mach-rockchip/rk3568/rk3568.c
> +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
> @@ -24,6 +24,16 @@
> #define SGRF_SOC_CON4 0x10
> #define EMMC_HPROT_SECURE_CTRL 0x03
> #define SDMMC0_HPROT_SECURE_CTRL 0x01
> +
> +#define PMU_BASE_ADDR 0xfdd90000
> +#define PMU_NOC_AUTO_CON0 (0x70)
> +#define PMU_NOC_AUTO_CON1 (0x74)
> +#define EDP_PHY_GRF_BASE 0xfdcb0000
> +#define EDP_PHY_GRF_CON0 (EDP_PHY_GRF_BASE + 0x00)
> +#define EDP_PHY_GRF_CON10 (EDP_PHY_GRF_BASE + 0x28)
> +#define CPU_GRF_BASE 0xfdc30000
> +#define GRF_CORE_PVTPLL_CON0 (0x10)
> +
> /* PMU_GRF_GPIO0D_IOMUX_L */
> enum {
> GPIO0D1_SHIFT = 4,
> @@ -98,6 +108,20 @@ void board_debug_uart_init(void)
> int arch_cpu_init(void)
> {
> #ifdef CONFIG_SPL_BUILD
> + /*
> + * When perform idle operation, corresponding clock can
> + * be opened or gated automatically.
> + */
> + writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
> + writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
> +
> + /* Disable eDP phy by default */
> + writel(0x00070007, EDP_PHY_GRF_CON10);
> + writel(0x0ff10ff1, EDP_PHY_GRF_CON0);
> +
> + /* Set core pvtpll ring length */
> + writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0);
> +
> /* Set the emmc sdmmc0 to secure */
> rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11
> | SDMMC0_HPROT_SECURE_CTRL << 4));
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 1/9] gpio: gpio-rockchip: parse gpio-ranges for bank id
2023-02-13 22:27 ` [PATCH V2 1/9] gpio: gpio-rockchip: parse gpio-ranges for bank id Chris Morgan
@ 2023-02-22 7:44 ` Kever Yang
2023-02-22 10:59 ` Johan Jonker
2023-02-23 8:59 ` Linus Walleij
2 siblings, 0 replies; 33+ messages in thread
From: Kever Yang @ 2023-02-22 7:44 UTC (permalink / raw)
To: Chris Morgan, u-boot
Cc: heiko, sjg, philipp.tomsich, chenjh, pgwipeout, heiko.stuebner,
Chris Morgan
On 2023/2/14 06:27, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Use the new devicetree property of gpio-ranges to determine the GPIO
> bank ID. Preserve the "old" way of doing things too, so that boards
> can be migrated and tested gradually (I only have a 3566 and 3326 to
> test).
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> drivers/gpio/rk_gpio.c | 20 +++++++++++++++++---
> 1 file changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
> index 68f30157a9..98a79b5f4d 100644
> --- a/drivers/gpio/rk_gpio.c
> +++ b/drivers/gpio/rk_gpio.c
> @@ -142,6 +142,7 @@ static int rockchip_gpio_probe(struct udevice *dev)
> {
> struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> struct rockchip_gpio_priv *priv = dev_get_priv(dev);
> + struct ofnode_phandle_args args;
> char *end;
> int ret;
>
> @@ -150,9 +151,22 @@ static int rockchip_gpio_probe(struct udevice *dev)
> if (ret)
> return ret;
>
> - uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
> - end = strrchr(dev->name, '@');
> - priv->bank = trailing_strtoln(dev->name, end);
> + /*
> + * If "gpio-ranges" is present in the devicetree use it to parse
> + * the GPIO bank ID, otherwise use the legacy method.
> + */
> + ret = ofnode_parse_phandle_with_args(dev_ofnode(dev),
> + "gpio-ranges", NULL, 3,
> + 0, &args);
> + if (!ret || ret != -ENOENT) {
> + uc_priv->gpio_count = args.args[2];
> + priv->bank = args.args[1] / args.args[2];
> + } else {
> + uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
> + end = strrchr(dev->name, '@');
> + priv->bank = trailing_strtoln(dev->name, end);
> + }
> +
> priv->name[0] = 'A' + priv->bank;
> uc_priv->bank_name = priv->name;
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 2/9] dts: rockchip: px30: add gpio-ranges property to gpio nodes
2023-02-13 22:27 ` [PATCH V2 2/9] dts: rockchip: px30: add gpio-ranges property to gpio nodes Chris Morgan
@ 2023-02-22 7:44 ` Kever Yang
0 siblings, 0 replies; 33+ messages in thread
From: Kever Yang @ 2023-02-22 7:44 UTC (permalink / raw)
To: Chris Morgan, u-boot
Cc: heiko, sjg, philipp.tomsich, chenjh, pgwipeout, heiko.stuebner,
Chris Morgan
On 2023/2/14 06:27, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Add the gpio-ranges property to each GPIO node for use in deriving
> the correct bank ID. Note that invoking "gpio status -a" no longer
> causes the board to hit a "Synchronous Abort".
>
> Fixes: 537b1a277479 ("rockchip: add px30 devicetrees")
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/dts/px30.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
> index bfa3580429..3152bf107d 100644
> --- a/arch/arm/dts/px30.dtsi
> +++ b/arch/arm/dts/px30.dtsi
> @@ -1366,6 +1366,7 @@
> interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&pmucru PCLK_GPIO0_PMU>;
> gpio-controller;
> + gpio-ranges = <&pinctrl 0 0 32>;
> #gpio-cells = <2>;
>
> interrupt-controller;
> @@ -1378,6 +1379,7 @@
> interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru PCLK_GPIO1>;
> gpio-controller;
> + gpio-ranges = <&pinctrl 0 32 32>;
> #gpio-cells = <2>;
>
> interrupt-controller;
> @@ -1390,6 +1392,7 @@
> interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru PCLK_GPIO2>;
> gpio-controller;
> + gpio-ranges = <&pinctrl 0 64 32>;
> #gpio-cells = <2>;
>
> interrupt-controller;
> @@ -1402,6 +1405,7 @@
> interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru PCLK_GPIO3>;
> gpio-controller;
> + gpio-ranges = <&pinctrl 0 96 32>;
> #gpio-cells = <2>;
>
> interrupt-controller;
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 5/9] rockchip: rk3568: add boot device detection
2023-02-15 18:28 ` Jonas Karlman
@ 2023-02-22 7:45 ` Kever Yang
0 siblings, 0 replies; 33+ messages in thread
From: Kever Yang @ 2023-02-22 7:45 UTC (permalink / raw)
To: Jonas Karlman, Chris Morgan, u-boot
Cc: heiko, sjg, philipp.tomsich, chenjh, pgwipeout, heiko.stuebner,
Chris Morgan
On 2023/2/16 02:28, Jonas Karlman wrote:
> Hi Chris,
>
> On 2023-02-13 23:27, Chris Morgan wrote:
>> From: Chris Morgan <macromorgan@hotmail.com>
>>
>> Enable spl to detect which device it was booted from.
>>
>> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
>> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
>> ---
>> arch/arm/mach-rockchip/rk3568/rk3568.c | 7 +++++++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
>> index 22eeb77d41..a2d59abc26 100644
>> --- a/arch/arm/mach-rockchip/rk3568/rk3568.c
>> +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
>> @@ -7,6 +7,7 @@
>> #include <dm.h>
>> #include <asm/armv8/mmu.h>
>> #include <asm/io.h>
>> +#include <asm/arch-rockchip/bootrom.h>
>> #include <asm/arch-rockchip/grf_rk3568.h>
>> #include <asm/arch-rockchip/hardware.h>
>> #include <dt-bindings/clock/rk3568-cru.h>
>> @@ -70,6 +71,12 @@ static struct mm_region rk3568_mem_map[] = {
>> }
>> };
>>
>> +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
>> + [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe310000",
> This should be mmc@@fe310000.
With this update.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
>
> Regards,
> Jonas
>
>> + [BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0",
>> + [BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000",
>> +};
>> +
>> struct mm_region *mem_map = rk3568_mem_map;
>>
>> void board_debug_uart_init(void)
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 8/9] arm64: dts: rockchip: add gpio-ranges property to gpio nodes
2023-02-13 22:27 ` [PATCH V2 8/9] arm64: dts: rockchip: add gpio-ranges property to gpio nodes Chris Morgan
@ 2023-02-22 7:47 ` Kever Yang
2023-02-23 21:12 ` Vasily Khoruzhick
1 sibling, 0 replies; 33+ messages in thread
From: Kever Yang @ 2023-02-22 7:47 UTC (permalink / raw)
To: Chris Morgan, u-boot
Cc: heiko, sjg, philipp.tomsich, chenjh, pgwipeout, heiko.stuebner,
Chris Morgan
On 2023/2/14 06:27, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Add gpio-ranges property to GPIO nodes so that the bank ID can
> be correctly derived for each GPIO bank.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/dts/rk356x.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi
> index 5706c3e24f..6492ace0de 100644
> --- a/arch/arm/dts/rk356x.dtsi
> +++ b/arch/arm/dts/rk356x.dtsi
> @@ -1806,6 +1806,7 @@
> interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
> gpio-controller;
> + gpio-ranges = <&pinctrl 0 0 32>;
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> @@ -1817,6 +1818,7 @@
> interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
> gpio-controller;
> + gpio-ranges = <&pinctrl 0 32 32>;
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> @@ -1828,6 +1830,7 @@
> interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
> gpio-controller;
> + gpio-ranges = <&pinctrl 0 64 32>;
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> @@ -1839,6 +1842,7 @@
> interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
> gpio-controller;
> + gpio-ranges = <&pinctrl 0 96 32>;
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> @@ -1850,6 +1854,7 @@
> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
> gpio-controller;
> + gpio-ranges = <&pinctrl 0 128 32>;
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 9/9] evb1-v10-rk3568: Update MAINTAINERS and documentation
2023-02-13 22:27 ` [PATCH V2 9/9] evb1-v10-rk3568: Update MAINTAINERS and documentation Chris Morgan
@ 2023-02-22 7:48 ` Kever Yang
0 siblings, 0 replies; 33+ messages in thread
From: Kever Yang @ 2023-02-22 7:48 UTC (permalink / raw)
To: Chris Morgan, u-boot
Cc: heiko, sjg, philipp.tomsich, chenjh, pgwipeout, heiko.stuebner,
Chris Morgan
On 2023/2/14 06:27, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Update the MAINTAINERS file to include the devicetree for the
> rk3568-evb1-v10 board.
>
> Also update Rockchip board docs to include information on building
> RK3568 based devices.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> ---
> board/rockchip/evb_rk3568/MAINTAINERS | 12 +++++++-----
> doc/board/rockchip/rockchip.rst | 10 ++++++++++
> 2 files changed, 17 insertions(+), 5 deletions(-)
>
> diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS
> index b6ea498d2b..f959e8862b 100644
> --- a/board/rockchip/evb_rk3568/MAINTAINERS
> +++ b/board/rockchip/evb_rk3568/MAINTAINERS
> @@ -1,6 +1,8 @@
> EVB-RK3568
> -M: Joseph Chen <chenjh@rock-chips.com>
> -S: Maintained
> -F: board/rockchip/evb_rk3568
> -F: include/configs/evb_rk3568.h
> -F: configs/evb-rk3568_defconfig
> +M: Joseph Chen <chenjh@rock-chips.com>
> +S: Maintained
> +F: arch/arm/dts/rk3568-evb1-v10-u-boot.dtsi
> +F: arch/arm/dts/rk3568-evb1-v10.dts
> +F: board/rockchip/evb_rk3568
> +F: configs/evb1-v10-rk3568_defconfig
> +F: include/configs/evb_rk3568.h
> diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
> index 28c837a382..02e6e82927 100644
> --- a/doc/board/rockchip/rockchip.rst
> +++ b/doc/board/rockchip/rockchip.rst
> @@ -86,6 +86,8 @@ List of mainline supported Rockchip boards:
> - Radxa ROCK Pi 4 (rock-pi-4-rk3399)
> - Rockchip Evb-RK3399 (evb_rk3399)
> - Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399)
> +* rk3568
> + - Rockchip EVB-RK3568 (evb1-v10-rk3568)
> * rv1108
> - Rockchip Evb-rv1108 (evb-rv1108)
> - Elgin-R1 (elgin-rv1108)
> @@ -167,6 +169,14 @@ To build rk3399 boards:
> make evb-rk3399_defconfig
> make CROSS_COMPILE=aarch64-linux-gnu-
>
> +To build rk3568 boards:
> +
> +.. code-block:: bash
> +
> + export BL31=../arm-trusted-firmware/build/rk3568/release/bl31/bl31.elf
> + make evb1-v10-rk3568_defconfig
Keep to use make evb-rk3568_defconfig.
Thanks,
- Kever
> + make CROSS_COMPILE=aarch64-linux-gnu-
> +
> Flashing
> --------
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller
2023-02-13 22:27 ` [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller Chris Morgan
2023-02-16 11:19 ` FUKAUMI Naoki
@ 2023-02-22 7:49 ` Kever Yang
2023-02-22 8:28 ` Kever Yang
` (2 subsequent siblings)
4 siblings, 0 replies; 33+ messages in thread
From: Kever Yang @ 2023-02-22 7:49 UTC (permalink / raw)
To: Chris Morgan, u-boot
Cc: heiko, sjg, philipp.tomsich, chenjh, pgwipeout, heiko.stuebner,
Chris Morgan
On 2023/2/14 06:27, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Add support for the newer GPIO controller used by the rk356x series,
> as well as the pinctrl device for the rk356x series. The GPIOv2
> controller has a write enable bit for some registers which differs
> from the older versions of the GPIO controller.
>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
With FUKAUMI Naoki's comment apply:
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/include/asm/arch-rockchip/gpio.h | 38 ++
> drivers/gpio/rk_gpio.c | 49 +-
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl-rk3568.c | 453 ++++++++++++++++++
> .../pinctrl/rockchip/pinctrl-rockchip-core.c | 12 +-
> 5 files changed, 540 insertions(+), 13 deletions(-)
> create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c
>
> diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h
> index 1aaec5faec..15f5de321b 100644
> --- a/arch/arm/include/asm/arch-rockchip/gpio.h
> +++ b/arch/arm/include/asm/arch-rockchip/gpio.h
> @@ -6,6 +6,7 @@
> #ifndef _ASM_ARCH_GPIO_H
> #define _ASM_ARCH_GPIO_H
>
> +#if !defined(CONFIG_ROCKCHIP_RK3568)
> struct rockchip_gpio_regs {
> u32 swport_dr;
> u32 swport_ddr;
> @@ -22,7 +23,44 @@ struct rockchip_gpio_regs {
> u32 reserved1[(0x60 - 0x54) / 4];
> u32 ls_sync;
> };
> +
> check_member(rockchip_gpio_regs, ls_sync, 0x60);
> +#else
> +struct rockchip_gpio_regs {
> + u32 swport_dr_l; /* ADDRESS OFFSET: 0x0000 */
> + u32 swport_dr_h; /* ADDRESS OFFSET: 0x0004 */
> + u32 swport_ddr_l; /* ADDRESS OFFSET: 0x0008 */
> + u32 swport_ddr_h; /* ADDRESS OFFSET: 0x000c */
> + u32 int_en_l; /* ADDRESS OFFSET: 0x0010 */
> + u32 int_en_h; /* ADDRESS OFFSET: 0x0014 */
> + u32 int_mask_l; /* ADDRESS OFFSET: 0x0018 */
> + u32 int_mask_h; /* ADDRESS OFFSET: 0x001c */
> + u32 int_type_l; /* ADDRESS OFFSET: 0x0020 */
> + u32 int_type_h; /* ADDRESS OFFSET: 0x0024 */
> + u32 int_polarity_l; /* ADDRESS OFFSET: 0x0028 */
> + u32 int_polarity_h; /* ADDRESS OFFSET: 0x002c */
> + u32 int_bothedge_l; /* ADDRESS OFFSET: 0x0030 */
> + u32 int_bothedge_h; /* ADDRESS OFFSET: 0x0034 */
> + u32 debounce_l; /* ADDRESS OFFSET: 0x0038 */
> + u32 debounce_h; /* ADDRESS OFFSET: 0x003c */
> + u32 dbclk_div_en_l; /* ADDRESS OFFSET: 0x0040 */
> + u32 dbclk_div_en_h; /* ADDRESS OFFSET: 0x0044 */
> + u32 dbclk_div_con; /* ADDRESS OFFSET: 0x0048 */
> + u32 reserved004c; /* ADDRESS OFFSET: 0x004c */
> + u32 int_status; /* ADDRESS OFFSET: 0x0050 */
> + u32 reserved0054; /* ADDRESS OFFSET: 0x0054 */
> + u32 int_rawstatus; /* ADDRESS OFFSET: 0x0058 */
> + u32 reserved005c; /* ADDRESS OFFSET: 0x005c */
> + u32 port_eoi_l; /* ADDRESS OFFSET: 0x0060 */
> + u32 port_eoi_h; /* ADDRESS OFFSET: 0x0064 */
> + u32 reserved0068[2]; /* ADDRESS OFFSET: 0x0068 */
> + u32 ext_port; /* ADDRESS OFFSET: 0x0070 */
> + u32 reserved0074; /* ADDRESS OFFSET: 0x0074 */
> + u32 ver_id; /* ADDRESS OFFSET: 0x0078 */
> +};
> +
> +check_member(rockchip_gpio_regs, ver_id, 0x0078);
> +#endif
>
> enum gpio_pu_pd {
> GPIO_PULL_NORMAL = 0,
> diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
> index 98a79b5f4d..e2653be058 100644
> --- a/drivers/gpio/rk_gpio.c
> +++ b/drivers/gpio/rk_gpio.c
> @@ -2,12 +2,15 @@
> /*
> * (C) Copyright 2015 Google, Inc
> *
> - * (C) Copyright 2008-2014 Rockchip Electronics
> + * (C) Copyright 2008-2023 Rockchip Electronics
> * Peter, Software Engineering, <superpeter.cai@gmail.com>.
> + * Jianqun Xu, Software Engineering, <jay.xu@rock-chips.com>.
> */
>
> #include <common.h>
> #include <dm.h>
> +#include <dm/of_access.h>
> +#include <dm/device_compat.h>
> #include <syscon.h>
> #include <linux/errno.h>
> #include <asm/gpio.h>
> @@ -23,6 +26,35 @@ enum {
>
> #define OFFSET_TO_BIT(bit) (1UL << (bit))
>
> +/*
> + * Newer Rockchip devices have additional registers that must be
> + * accounted for.
> + */
> +#if defined(CONFIG_ROCKCHIP_RK3568)
> +#define GPIO_VER 2
> +#define REG_L(R) (R##_l)
> +#define REG_H(R) (R##_h)
> +#define READ_REG(REG) ((readl(REG_L(REG)) & 0xFFFF) | \
> + ((readl(REG_H(REG)) & 0xFFFF) << 16))
> +#define WRITE_REG(REG, VAL) \
> +{\
> + writel(((VAL) & 0xFFFF) | 0xFFFF0000, REG_L(REG)); \
> + writel((((VAL) & 0xFFFF0000) >> 16) | 0xFFFF0000, REG_H(REG));\
> +}
> +#define CLRBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) & ~(MASK))
> +#define SETBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) | (MASK))
> +#define CLRSETBITS_LE32(REG, MASK, VAL) WRITE_REG(REG, \
> + (READ_REG(REG) & ~(MASK)) | (VAL))
> +
> +#else
> +#define GPIO_VER 1
> +#define READ_REG(REG) readl(REG)
> +#define WRITE_REG(REG, VAL) writel(VAL, REG)
> +#define CLRBITS_LE32(REG, MASK) clrbits_le32(REG, MASK)
> +#define SETBITS_LE32(REG, MASK) setbits_le32(REG, MASK)
> +#define CLRSETBITS_LE32(REG, MASK, VAL) clrsetbits_le32(REG, MASK, VAL)
> +#endif
> +
> struct rockchip_gpio_priv {
> struct rockchip_gpio_regs *regs;
> struct udevice *pinctrl;
> @@ -35,7 +68,7 @@ static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset)
> struct rockchip_gpio_priv *priv = dev_get_priv(dev);
> struct rockchip_gpio_regs *regs = priv->regs;
>
> - clrbits_le32(®s->swport_ddr, OFFSET_TO_BIT(offset));
> + CLRBITS_LE32(®s->swport_ddr, OFFSET_TO_BIT(offset));
>
> return 0;
> }
> @@ -47,8 +80,8 @@ static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset,
> struct rockchip_gpio_regs *regs = priv->regs;
> int mask = OFFSET_TO_BIT(offset);
>
> - clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0);
> - setbits_le32(®s->swport_ddr, mask);
> + CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0);
> + SETBITS_LE32(®s->swport_ddr, mask);
>
> return 0;
> }
> @@ -68,7 +101,7 @@ static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
> struct rockchip_gpio_regs *regs = priv->regs;
> int mask = OFFSET_TO_BIT(offset);
>
> - clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0);
> + CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0);
>
> return 0;
> }
> @@ -86,14 +119,14 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
> ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
> if (ret)
> return ret;
> - is_output = readl(®s->swport_ddr) & OFFSET_TO_BIT(offset);
> + is_output = READ_REG(®s->swport_ddr) & OFFSET_TO_BIT(offset);
>
> return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
> #endif
> }
>
> /* Simple SPL interface to GPIOs */
> -#ifdef CONFIG_SPL_BUILD
> +#if defined(CONFIG_SPL_BUILD) && (GPIO_VER == 1)
>
> enum {
> PULL_NONE_1V8 = 0,
> @@ -143,7 +176,7 @@ static int rockchip_gpio_probe(struct udevice *dev)
> struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> struct rockchip_gpio_priv *priv = dev_get_priv(dev);
> struct ofnode_phandle_args args;
> - char *end;
> + char *end = NULL;
> int ret;
>
> priv->regs = dev_read_addr_ptr(dev);
> diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
> index 9884355473..90461ae881 100644
> --- a/drivers/pinctrl/rockchip/Makefile
> +++ b/drivers/pinctrl/rockchip/Makefile
> @@ -14,5 +14,6 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o
> obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
> obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
> +obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
> obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
> obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o
> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
> new file mode 100644
> index 0000000000..dce1c1e7ee
> --- /dev/null
> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
> @@ -0,0 +1,453 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2020 Rockchip Electronics Co., Ltd
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <dm/pinctrl.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +
> +#include "pinctrl-rockchip.h"
> +
> +static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
> + /* CAN0 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)),
> + /* CAN0 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)),
> + /* CAN1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)),
> + /* CAN1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)),
> + /* CAN2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)),
> + /* CAN2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)),
> + /* EDPDP_HPDIN IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)),
> + /* EDPDP_HPDIN IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)),
> + /* GMAC1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 0)),
> + /* GMAC1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PA7, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 1)),
> + /* HDMITX IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PD1, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 0)),
> + /* HDMITX IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO0, RK_PC7, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 1)),
> + /* I2C2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PB6, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 0)),
> + /* I2C2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PB4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 1)),
> + /* I2C3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA0, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(0, 0, 0)),
> + /* I2C3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(0, 0, 1)),
> + /* I2C4 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PB2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(2, 2, 0)),
> + /* I2C4 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)),
> + /* I2C5 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)),
> + /* I2C5 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)),
> + /* PWM4 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)),
> + /* PWM4 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)),
> + /* PWM5 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)),
> + /* PWM5 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)),
> + /* PWM6 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)),
> + /* PWM6 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)),
> + /* PWM7 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)),
> + /* PWM7 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)),
> + /* PWM8 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)),
> + /* PWM8 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)),
> + /* PWM9 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)),
> + /* PWM9 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)),
> + /* PWM10 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)),
> + /* PWM10 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)),
> + /* PWM11 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)),
> + /* PWM11 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)),
> + /* PWM12 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)),
> + /* PWM12 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)),
> + /* PWM13 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)),
> + /* PWM13 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)),
> + /* PWM14 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)),
> + /* PWM14 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)),
> + /* PWM15 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)),
> + /* PWM15 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)),
> + /* SDMMC2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)),
> + /* SDMMC2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)),
> + /* SPI0 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)),
> + /* SPI0 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(0, 0, 1)),
> + /* SPI1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PB5, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 0)),
> + /* SPI1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 1)),
> + /* SPI2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(4, 4, 0)),
> + /* SPI2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(4, 4, 1)),
> + /* SPI3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)),
> + /* SPI3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)),
> + /* UART1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)),
> + /* UART1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)),
> + /* UART2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)),
> + /* UART2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)),
> + /* UART3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)),
> + /* UART3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(12, 12, 1)),
> + /* UART4 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(14, 14, 0)),
> + /* UART4 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(14, 14, 1)),
> + /* UART5 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PA2, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(0, 0, 0)),
> + /* UART5 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(0, 0, 1)),
> + /* UART6 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PA4, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 0)),
> + /* UART6 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)),
> + /* UART7 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)),
> + /* UART7 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)),
> + /* UART7 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)),
> + /* UART8 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)),
> + /* UART8 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)),
> + /* UART9 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)),
> + /* UART9 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 1)),
> + /* UART9 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO4, RK_PA4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 2)),
> + /* I2S1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(11, 10, 0)),
> + /* I2S1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(11, 10, 1)),
> + /* I2S1 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(11, 10, 2)),
> + /* I2S2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(12, 12, 0)),
> + /* I2S2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)),
> + /* I2S3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)),
> + /* I2S3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)),
> + /* PDM IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)),
> + /* PDM IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)),
> + /* PCIE20 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)),
> + /* PCIE20 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)),
> + /* PCIE20 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)),
> + /* PCIE30X1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(5, 4, 0)),
> + /* PCIE30X1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 1)),
> + /* PCIE30X1 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 2)),
> + /* PCIE30X2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PA6, RK_FUNC_2, 0x0314, RK_GENMASK_VAL(7, 6, 0)),
> + /* PCIE30X2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 1)),
> + /* PCIE30X2 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 2)),
> +};
> +
> +static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int iomux_num = (pin / 8);
> + struct regmap *regmap;
> + int reg, ret, mask;
> + u8 bit;
> + u32 data;
> +
> + debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
> +
> + if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
> + regmap = priv->regmap_pmu;
> + else
> + regmap = priv->regmap_base;
> +
> + reg = bank->iomux[iomux_num].offset;
> + if ((pin % 8) >= 4)
> + reg += 0x4;
> + bit = (pin % 4) * 4;
> + mask = 0xf;
> +
> + data = (mask << (bit + 16));
> + data |= (mux & mask) << bit;
> + ret = regmap_write(regmap, reg, data);
> +
> + return ret;
> +}
> +
> +#define RK3568_PULL_PMU_OFFSET 0x20
> +#define RK3568_PULL_GRF_OFFSET 0x80
> +#define RK3568_PULL_BITS_PER_PIN 2
> +#define RK3568_PULL_PINS_PER_REG 8
> +#define RK3568_PULL_BANK_STRIDE 0x10
> +
> +static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *info = bank->priv;
> +
> + if (bank->bank_num == 0) {
> + *regmap = info->regmap_pmu;
> + *reg = RK3568_PULL_PMU_OFFSET;
> + *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
> + } else {
> + *regmap = info->regmap_base;
> + *reg = RK3568_PULL_GRF_OFFSET;
> + *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
> + *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
> + *bit *= RK3568_PULL_BITS_PER_PIN;
> +}
> +
> +#define RK3568_DRV_PMU_OFFSET 0x70
> +#define RK3568_DRV_GRF_OFFSET 0x200
> +#define RK3568_DRV_BITS_PER_PIN 8
> +#define RK3568_DRV_PINS_PER_REG 2
> +#define RK3568_DRV_BANK_STRIDE 0x40
> +
> +static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *info = bank->priv;
> +
> + /* The first 32 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = info->regmap_pmu;
> + *reg = RK3568_DRV_PMU_OFFSET;
> + } else {
> + *regmap = info->regmap_base;
> + *reg = RK3568_DRV_GRF_OFFSET;
> + *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
> + *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
> + *bit *= RK3568_DRV_BITS_PER_PIN;
> +}
> +
> +#define RK3568_SCHMITT_BITS_PER_PIN 2
> +#define RK3568_SCHMITT_PINS_PER_REG 8
> +#define RK3568_SCHMITT_BANK_STRIDE 0x10
> +#define RK3568_SCHMITT_GRF_OFFSET 0xc0
> +#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
> +
> +static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *info = bank->priv;
> +
> + if (bank->bank_num == 0) {
> + *regmap = info->regmap_pmu;
> + *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
> + } else {
> + *regmap = info->regmap_base;
> + *reg = RK3568_SCHMITT_GRF_OFFSET;
> + *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
> + *bit *= RK3568_SCHMITT_BITS_PER_PIN;
> +
> + return 0;
> +}
> +
> +static int rk3568_set_pull(struct rockchip_pin_bank *bank,
> + int pin_num, int pull)
> +{
> + struct regmap *regmap;
> + int reg, ret;
> + u8 bit, type;
> + u32 data;
> +
> + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
> + return -EOPNOTSUPP;
> +
> + rk3568_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> + type = bank->pull_type[pin_num / 8];
> + ret = rockchip_translate_pull_value(type, pull);
> + if (ret < 0) {
> + debug("unsupported pull setting %d\n", pull);
> + return ret;
> + }
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
> +
> + data |= (ret << bit);
> + ret = regmap_write(regmap, reg, data);
> +
> + return ret;
> +}
> +
> +static int rk3568_set_drive(struct rockchip_pin_bank *bank,
> + int pin_num, int strength)
> +{
> + struct regmap *regmap;
> + int reg;
> + u32 data;
> + u8 bit;
> + int drv = (1 << (strength + 1)) - 1;
> + int ret = 0;
> +
> + rk3568_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16);
> + data |= (drv << bit);
> +
> + ret = regmap_write(regmap, reg, data);
> + if (ret)
> + return ret;
> +
> + if (bank->bank_num == 1 && pin_num == 21)
> + reg = 0x0840;
> + else if (bank->bank_num == 2 && pin_num == 2)
> + reg = 0x0844;
> + else if (bank->bank_num == 2 && pin_num == 8)
> + reg = 0x0848;
> + else if (bank->bank_num == 3 && pin_num == 0)
> + reg = 0x084c;
> + else if (bank->bank_num == 3 && pin_num == 6)
> + reg = 0x0850;
> + else if (bank->bank_num == 4 && pin_num == 0)
> + reg = 0x0854;
> + else
> + return 0;
> +
> + data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16;
> + data |= drv;
> +
> + return regmap_write(regmap, reg, data);
> +}
> +
> +static int rk3568_set_schmitt(struct rockchip_pin_bank *bank,
> + int pin_num, int enable)
> +{
> + struct regmap *regmap;
> + int reg;
> + u32 data;
> + u8 bit;
> +
> + rk3568_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
> + data |= (enable << bit);
> +
> + return regmap_write(regmap, reg, data);
> +}
> +
> +static struct rockchip_pin_bank rk3568_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
> + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
> + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
> + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> +};
> +
> +static const struct rockchip_pin_ctrl rk3568_pin_ctrl = {
> + .pin_banks = rk3568_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
> + .nr_pins = 160,
> + .grf_mux_offset = 0x0,
> + .pmu_mux_offset = 0x0,
> + .iomux_routes = rk3568_mux_route_data,
> + .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
> + .set_mux = rk3568_set_mux,
> + .set_pull = rk3568_set_pull,
> + .set_drive = rk3568_set_drive,
> + .set_schmitt = rk3568_set_schmitt,
> +};
> +
> +static const struct udevice_id rk3568_pinctrl_ids[] = {
> + {
> + .compatible = "rockchip,rk3568-pinctrl",
> + .data = (ulong)&rk3568_pin_ctrl
> + },
> + { }
> +};
> +
> +U_BOOT_DRIVER(pinctrl_rk3568) = {
> + .name = "rockchip_rk3568_pinctrl",
> + .id = UCLASS_PINCTRL,
> + .of_match = rk3568_pinctrl_ids,
> + .priv_auto = sizeof(struct rockchip_pinctrl_priv),
> + .ops = &rockchip_pinctrl_ops,
> +#if !IS_ENABLED(CONFIG_OF_PLATDATA)
> + .bind = dm_scan_fdt_dev,
> +#endif
> + .probe = rockchip_pinctrl_probe,
> +};
> diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
> index d9d61fdb72..1481c1e51c 100644
> --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
> +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
> @@ -433,7 +433,7 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
> int prop_len, param;
> const u32 *data;
> ofnode node;
> -#ifdef CONFIG_OF_LIVE
> +#if CONFIG_IS_ENABLED(OF_LIVE)
> const struct device_node *np;
> struct property *pp;
> #else
> @@ -473,7 +473,7 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
> node = ofnode_get_by_phandle(conf);
> if (!ofnode_valid(node))
> return -ENODEV;
> -#ifdef CONFIG_OF_LIVE
> +#if CONFIG_IS_ENABLED(OF_LIVE)
> np = ofnode_to_np(node);
> for (pp = np->properties; pp; pp = pp->next) {
> prop_name = pp->name;
> @@ -548,13 +548,15 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d
>
> /* preset iomux offset value, set new start value */
> if (iom->offset >= 0) {
> - if (iom->type & IOMUX_SOURCE_PMU)
> + if ((iom->type & IOMUX_SOURCE_PMU) || \
> + (iom->type & IOMUX_L_SOURCE_PMU))
> pmu_offs = iom->offset;
> else
> grf_offs = iom->offset;
> } else { /* set current iomux offset */
> - iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
> - pmu_offs : grf_offs;
> + iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
> + (iom->type & IOMUX_L_SOURCE_PMU)) ?
> + pmu_offs : grf_offs;
> }
>
> /* preset drv offset value, set new start value */
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller
2023-02-13 22:27 ` [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller Chris Morgan
2023-02-16 11:19 ` FUKAUMI Naoki
2023-02-22 7:49 ` Kever Yang
@ 2023-02-22 8:28 ` Kever Yang
2023-02-23 22:14 ` Vasily Khoruzhick
2023-03-01 8:25 ` Eugen Hristev
4 siblings, 0 replies; 33+ messages in thread
From: Kever Yang @ 2023-02-22 8:28 UTC (permalink / raw)
To: Chris Morgan, u-boot
Cc: heiko, sjg, philipp.tomsich, chenjh, pgwipeout, heiko.stuebner,
Chris Morgan
Hi Chris,
For this patch, I have pick below patch instead:
https://patchwork.ozlabs.org/project/uboot/patch/20230217115845.75303-11-jagan@amarulasolutions.com/
For those change other than pinctrl-rk3568.c, please send a new
patch is still available.
Thanks,
- Kever
On 2023/2/14 06:27, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Add support for the newer GPIO controller used by the rk356x series,
> as well as the pinctrl device for the rk356x series. The GPIOv2
> controller has a write enable bit for some registers which differs
> from the older versions of the GPIO controller.
>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> ---
> arch/arm/include/asm/arch-rockchip/gpio.h | 38 ++
> drivers/gpio/rk_gpio.c | 49 +-
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl-rk3568.c | 453 ++++++++++++++++++
> .../pinctrl/rockchip/pinctrl-rockchip-core.c | 12 +-
> 5 files changed, 540 insertions(+), 13 deletions(-)
> create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c
>
> diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h
> index 1aaec5faec..15f5de321b 100644
> --- a/arch/arm/include/asm/arch-rockchip/gpio.h
> +++ b/arch/arm/include/asm/arch-rockchip/gpio.h
> @@ -6,6 +6,7 @@
> #ifndef _ASM_ARCH_GPIO_H
> #define _ASM_ARCH_GPIO_H
>
> +#if !defined(CONFIG_ROCKCHIP_RK3568)
> struct rockchip_gpio_regs {
> u32 swport_dr;
> u32 swport_ddr;
> @@ -22,7 +23,44 @@ struct rockchip_gpio_regs {
> u32 reserved1[(0x60 - 0x54) / 4];
> u32 ls_sync;
> };
> +
> check_member(rockchip_gpio_regs, ls_sync, 0x60);
> +#else
> +struct rockchip_gpio_regs {
> + u32 swport_dr_l; /* ADDRESS OFFSET: 0x0000 */
> + u32 swport_dr_h; /* ADDRESS OFFSET: 0x0004 */
> + u32 swport_ddr_l; /* ADDRESS OFFSET: 0x0008 */
> + u32 swport_ddr_h; /* ADDRESS OFFSET: 0x000c */
> + u32 int_en_l; /* ADDRESS OFFSET: 0x0010 */
> + u32 int_en_h; /* ADDRESS OFFSET: 0x0014 */
> + u32 int_mask_l; /* ADDRESS OFFSET: 0x0018 */
> + u32 int_mask_h; /* ADDRESS OFFSET: 0x001c */
> + u32 int_type_l; /* ADDRESS OFFSET: 0x0020 */
> + u32 int_type_h; /* ADDRESS OFFSET: 0x0024 */
> + u32 int_polarity_l; /* ADDRESS OFFSET: 0x0028 */
> + u32 int_polarity_h; /* ADDRESS OFFSET: 0x002c */
> + u32 int_bothedge_l; /* ADDRESS OFFSET: 0x0030 */
> + u32 int_bothedge_h; /* ADDRESS OFFSET: 0x0034 */
> + u32 debounce_l; /* ADDRESS OFFSET: 0x0038 */
> + u32 debounce_h; /* ADDRESS OFFSET: 0x003c */
> + u32 dbclk_div_en_l; /* ADDRESS OFFSET: 0x0040 */
> + u32 dbclk_div_en_h; /* ADDRESS OFFSET: 0x0044 */
> + u32 dbclk_div_con; /* ADDRESS OFFSET: 0x0048 */
> + u32 reserved004c; /* ADDRESS OFFSET: 0x004c */
> + u32 int_status; /* ADDRESS OFFSET: 0x0050 */
> + u32 reserved0054; /* ADDRESS OFFSET: 0x0054 */
> + u32 int_rawstatus; /* ADDRESS OFFSET: 0x0058 */
> + u32 reserved005c; /* ADDRESS OFFSET: 0x005c */
> + u32 port_eoi_l; /* ADDRESS OFFSET: 0x0060 */
> + u32 port_eoi_h; /* ADDRESS OFFSET: 0x0064 */
> + u32 reserved0068[2]; /* ADDRESS OFFSET: 0x0068 */
> + u32 ext_port; /* ADDRESS OFFSET: 0x0070 */
> + u32 reserved0074; /* ADDRESS OFFSET: 0x0074 */
> + u32 ver_id; /* ADDRESS OFFSET: 0x0078 */
> +};
> +
> +check_member(rockchip_gpio_regs, ver_id, 0x0078);
> +#endif
>
> enum gpio_pu_pd {
> GPIO_PULL_NORMAL = 0,
> diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
> index 98a79b5f4d..e2653be058 100644
> --- a/drivers/gpio/rk_gpio.c
> +++ b/drivers/gpio/rk_gpio.c
> @@ -2,12 +2,15 @@
> /*
> * (C) Copyright 2015 Google, Inc
> *
> - * (C) Copyright 2008-2014 Rockchip Electronics
> + * (C) Copyright 2008-2023 Rockchip Electronics
> * Peter, Software Engineering, <superpeter.cai@gmail.com>.
> + * Jianqun Xu, Software Engineering, <jay.xu@rock-chips.com>.
> */
>
> #include <common.h>
> #include <dm.h>
> +#include <dm/of_access.h>
> +#include <dm/device_compat.h>
> #include <syscon.h>
> #include <linux/errno.h>
> #include <asm/gpio.h>
> @@ -23,6 +26,35 @@ enum {
>
> #define OFFSET_TO_BIT(bit) (1UL << (bit))
>
> +/*
> + * Newer Rockchip devices have additional registers that must be
> + * accounted for.
> + */
> +#if defined(CONFIG_ROCKCHIP_RK3568)
> +#define GPIO_VER 2
> +#define REG_L(R) (R##_l)
> +#define REG_H(R) (R##_h)
> +#define READ_REG(REG) ((readl(REG_L(REG)) & 0xFFFF) | \
> + ((readl(REG_H(REG)) & 0xFFFF) << 16))
> +#define WRITE_REG(REG, VAL) \
> +{\
> + writel(((VAL) & 0xFFFF) | 0xFFFF0000, REG_L(REG)); \
> + writel((((VAL) & 0xFFFF0000) >> 16) | 0xFFFF0000, REG_H(REG));\
> +}
> +#define CLRBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) & ~(MASK))
> +#define SETBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) | (MASK))
> +#define CLRSETBITS_LE32(REG, MASK, VAL) WRITE_REG(REG, \
> + (READ_REG(REG) & ~(MASK)) | (VAL))
> +
> +#else
> +#define GPIO_VER 1
> +#define READ_REG(REG) readl(REG)
> +#define WRITE_REG(REG, VAL) writel(VAL, REG)
> +#define CLRBITS_LE32(REG, MASK) clrbits_le32(REG, MASK)
> +#define SETBITS_LE32(REG, MASK) setbits_le32(REG, MASK)
> +#define CLRSETBITS_LE32(REG, MASK, VAL) clrsetbits_le32(REG, MASK, VAL)
> +#endif
> +
> struct rockchip_gpio_priv {
> struct rockchip_gpio_regs *regs;
> struct udevice *pinctrl;
> @@ -35,7 +68,7 @@ static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset)
> struct rockchip_gpio_priv *priv = dev_get_priv(dev);
> struct rockchip_gpio_regs *regs = priv->regs;
>
> - clrbits_le32(®s->swport_ddr, OFFSET_TO_BIT(offset));
> + CLRBITS_LE32(®s->swport_ddr, OFFSET_TO_BIT(offset));
>
> return 0;
> }
> @@ -47,8 +80,8 @@ static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset,
> struct rockchip_gpio_regs *regs = priv->regs;
> int mask = OFFSET_TO_BIT(offset);
>
> - clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0);
> - setbits_le32(®s->swport_ddr, mask);
> + CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0);
> + SETBITS_LE32(®s->swport_ddr, mask);
>
> return 0;
> }
> @@ -68,7 +101,7 @@ static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
> struct rockchip_gpio_regs *regs = priv->regs;
> int mask = OFFSET_TO_BIT(offset);
>
> - clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0);
> + CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0);
>
> return 0;
> }
> @@ -86,14 +119,14 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
> ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
> if (ret)
> return ret;
> - is_output = readl(®s->swport_ddr) & OFFSET_TO_BIT(offset);
> + is_output = READ_REG(®s->swport_ddr) & OFFSET_TO_BIT(offset);
>
> return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
> #endif
> }
>
> /* Simple SPL interface to GPIOs */
> -#ifdef CONFIG_SPL_BUILD
> +#if defined(CONFIG_SPL_BUILD) && (GPIO_VER == 1)
>
> enum {
> PULL_NONE_1V8 = 0,
> @@ -143,7 +176,7 @@ static int rockchip_gpio_probe(struct udevice *dev)
> struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> struct rockchip_gpio_priv *priv = dev_get_priv(dev);
> struct ofnode_phandle_args args;
> - char *end;
> + char *end = NULL;
> int ret;
>
> priv->regs = dev_read_addr_ptr(dev);
> diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
> index 9884355473..90461ae881 100644
> --- a/drivers/pinctrl/rockchip/Makefile
> +++ b/drivers/pinctrl/rockchip/Makefile
> @@ -14,5 +14,6 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o
> obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
> obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
> +obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
> obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
> obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o
> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
> new file mode 100644
> index 0000000000..dce1c1e7ee
> --- /dev/null
> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
> @@ -0,0 +1,453 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2020 Rockchip Electronics Co., Ltd
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <dm/pinctrl.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +
> +#include "pinctrl-rockchip.h"
> +
> +static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
> + /* CAN0 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)),
> + /* CAN0 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)),
> + /* CAN1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)),
> + /* CAN1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)),
> + /* CAN2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)),
> + /* CAN2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)),
> + /* EDPDP_HPDIN IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)),
> + /* EDPDP_HPDIN IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)),
> + /* GMAC1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 0)),
> + /* GMAC1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PA7, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 1)),
> + /* HDMITX IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PD1, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 0)),
> + /* HDMITX IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO0, RK_PC7, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 1)),
> + /* I2C2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PB6, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 0)),
> + /* I2C2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PB4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 1)),
> + /* I2C3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA0, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(0, 0, 0)),
> + /* I2C3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(0, 0, 1)),
> + /* I2C4 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PB2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(2, 2, 0)),
> + /* I2C4 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)),
> + /* I2C5 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)),
> + /* I2C5 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)),
> + /* PWM4 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)),
> + /* PWM4 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)),
> + /* PWM5 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)),
> + /* PWM5 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)),
> + /* PWM6 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)),
> + /* PWM6 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)),
> + /* PWM7 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)),
> + /* PWM7 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)),
> + /* PWM8 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)),
> + /* PWM8 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)),
> + /* PWM9 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)),
> + /* PWM9 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)),
> + /* PWM10 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)),
> + /* PWM10 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)),
> + /* PWM11 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)),
> + /* PWM11 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)),
> + /* PWM12 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)),
> + /* PWM12 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)),
> + /* PWM13 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)),
> + /* PWM13 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)),
> + /* PWM14 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)),
> + /* PWM14 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)),
> + /* PWM15 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)),
> + /* PWM15 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)),
> + /* SDMMC2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)),
> + /* SDMMC2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)),
> + /* SPI0 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)),
> + /* SPI0 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(0, 0, 1)),
> + /* SPI1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PB5, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 0)),
> + /* SPI1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 1)),
> + /* SPI2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(4, 4, 0)),
> + /* SPI2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(4, 4, 1)),
> + /* SPI3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)),
> + /* SPI3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)),
> + /* UART1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)),
> + /* UART1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)),
> + /* UART2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)),
> + /* UART2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)),
> + /* UART3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)),
> + /* UART3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(12, 12, 1)),
> + /* UART4 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(14, 14, 0)),
> + /* UART4 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(14, 14, 1)),
> + /* UART5 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PA2, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(0, 0, 0)),
> + /* UART5 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(0, 0, 1)),
> + /* UART6 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PA4, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 0)),
> + /* UART6 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)),
> + /* UART7 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)),
> + /* UART7 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)),
> + /* UART7 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)),
> + /* UART8 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)),
> + /* UART8 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)),
> + /* UART9 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)),
> + /* UART9 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 1)),
> + /* UART9 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO4, RK_PA4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 2)),
> + /* I2S1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(11, 10, 0)),
> + /* I2S1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(11, 10, 1)),
> + /* I2S1 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(11, 10, 2)),
> + /* I2S2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(12, 12, 0)),
> + /* I2S2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)),
> + /* I2S3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)),
> + /* I2S3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)),
> + /* PDM IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)),
> + /* PDM IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)),
> + /* PCIE20 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)),
> + /* PCIE20 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)),
> + /* PCIE20 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)),
> + /* PCIE30X1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(5, 4, 0)),
> + /* PCIE30X1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 1)),
> + /* PCIE30X1 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 2)),
> + /* PCIE30X2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PA6, RK_FUNC_2, 0x0314, RK_GENMASK_VAL(7, 6, 0)),
> + /* PCIE30X2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 1)),
> + /* PCIE30X2 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 2)),
> +};
> +
> +static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int iomux_num = (pin / 8);
> + struct regmap *regmap;
> + int reg, ret, mask;
> + u8 bit;
> + u32 data;
> +
> + debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
> +
> + if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
> + regmap = priv->regmap_pmu;
> + else
> + regmap = priv->regmap_base;
> +
> + reg = bank->iomux[iomux_num].offset;
> + if ((pin % 8) >= 4)
> + reg += 0x4;
> + bit = (pin % 4) * 4;
> + mask = 0xf;
> +
> + data = (mask << (bit + 16));
> + data |= (mux & mask) << bit;
> + ret = regmap_write(regmap, reg, data);
> +
> + return ret;
> +}
> +
> +#define RK3568_PULL_PMU_OFFSET 0x20
> +#define RK3568_PULL_GRF_OFFSET 0x80
> +#define RK3568_PULL_BITS_PER_PIN 2
> +#define RK3568_PULL_PINS_PER_REG 8
> +#define RK3568_PULL_BANK_STRIDE 0x10
> +
> +static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *info = bank->priv;
> +
> + if (bank->bank_num == 0) {
> + *regmap = info->regmap_pmu;
> + *reg = RK3568_PULL_PMU_OFFSET;
> + *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
> + } else {
> + *regmap = info->regmap_base;
> + *reg = RK3568_PULL_GRF_OFFSET;
> + *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
> + *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
> + *bit *= RK3568_PULL_BITS_PER_PIN;
> +}
> +
> +#define RK3568_DRV_PMU_OFFSET 0x70
> +#define RK3568_DRV_GRF_OFFSET 0x200
> +#define RK3568_DRV_BITS_PER_PIN 8
> +#define RK3568_DRV_PINS_PER_REG 2
> +#define RK3568_DRV_BANK_STRIDE 0x40
> +
> +static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *info = bank->priv;
> +
> + /* The first 32 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = info->regmap_pmu;
> + *reg = RK3568_DRV_PMU_OFFSET;
> + } else {
> + *regmap = info->regmap_base;
> + *reg = RK3568_DRV_GRF_OFFSET;
> + *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
> + *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
> + *bit *= RK3568_DRV_BITS_PER_PIN;
> +}
> +
> +#define RK3568_SCHMITT_BITS_PER_PIN 2
> +#define RK3568_SCHMITT_PINS_PER_REG 8
> +#define RK3568_SCHMITT_BANK_STRIDE 0x10
> +#define RK3568_SCHMITT_GRF_OFFSET 0xc0
> +#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
> +
> +static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *info = bank->priv;
> +
> + if (bank->bank_num == 0) {
> + *regmap = info->regmap_pmu;
> + *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
> + } else {
> + *regmap = info->regmap_base;
> + *reg = RK3568_SCHMITT_GRF_OFFSET;
> + *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
> + *bit *= RK3568_SCHMITT_BITS_PER_PIN;
> +
> + return 0;
> +}
> +
> +static int rk3568_set_pull(struct rockchip_pin_bank *bank,
> + int pin_num, int pull)
> +{
> + struct regmap *regmap;
> + int reg, ret;
> + u8 bit, type;
> + u32 data;
> +
> + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
> + return -EOPNOTSUPP;
> +
> + rk3568_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> + type = bank->pull_type[pin_num / 8];
> + ret = rockchip_translate_pull_value(type, pull);
> + if (ret < 0) {
> + debug("unsupported pull setting %d\n", pull);
> + return ret;
> + }
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
> +
> + data |= (ret << bit);
> + ret = regmap_write(regmap, reg, data);
> +
> + return ret;
> +}
> +
> +static int rk3568_set_drive(struct rockchip_pin_bank *bank,
> + int pin_num, int strength)
> +{
> + struct regmap *regmap;
> + int reg;
> + u32 data;
> + u8 bit;
> + int drv = (1 << (strength + 1)) - 1;
> + int ret = 0;
> +
> + rk3568_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16);
> + data |= (drv << bit);
> +
> + ret = regmap_write(regmap, reg, data);
> + if (ret)
> + return ret;
> +
> + if (bank->bank_num == 1 && pin_num == 21)
> + reg = 0x0840;
> + else if (bank->bank_num == 2 && pin_num == 2)
> + reg = 0x0844;
> + else if (bank->bank_num == 2 && pin_num == 8)
> + reg = 0x0848;
> + else if (bank->bank_num == 3 && pin_num == 0)
> + reg = 0x084c;
> + else if (bank->bank_num == 3 && pin_num == 6)
> + reg = 0x0850;
> + else if (bank->bank_num == 4 && pin_num == 0)
> + reg = 0x0854;
> + else
> + return 0;
> +
> + data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16;
> + data |= drv;
> +
> + return regmap_write(regmap, reg, data);
> +}
> +
> +static int rk3568_set_schmitt(struct rockchip_pin_bank *bank,
> + int pin_num, int enable)
> +{
> + struct regmap *regmap;
> + int reg;
> + u32 data;
> + u8 bit;
> +
> + rk3568_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
> + data |= (enable << bit);
> +
> + return regmap_write(regmap, reg, data);
> +}
> +
> +static struct rockchip_pin_bank rk3568_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
> + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
> + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
> + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> +};
> +
> +static const struct rockchip_pin_ctrl rk3568_pin_ctrl = {
> + .pin_banks = rk3568_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
> + .nr_pins = 160,
> + .grf_mux_offset = 0x0,
> + .pmu_mux_offset = 0x0,
> + .iomux_routes = rk3568_mux_route_data,
> + .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
> + .set_mux = rk3568_set_mux,
> + .set_pull = rk3568_set_pull,
> + .set_drive = rk3568_set_drive,
> + .set_schmitt = rk3568_set_schmitt,
> +};
> +
> +static const struct udevice_id rk3568_pinctrl_ids[] = {
> + {
> + .compatible = "rockchip,rk3568-pinctrl",
> + .data = (ulong)&rk3568_pin_ctrl
> + },
> + { }
> +};
> +
> +U_BOOT_DRIVER(pinctrl_rk3568) = {
> + .name = "rockchip_rk3568_pinctrl",
> + .id = UCLASS_PINCTRL,
> + .of_match = rk3568_pinctrl_ids,
> + .priv_auto = sizeof(struct rockchip_pinctrl_priv),
> + .ops = &rockchip_pinctrl_ops,
> +#if !IS_ENABLED(CONFIG_OF_PLATDATA)
> + .bind = dm_scan_fdt_dev,
> +#endif
> + .probe = rockchip_pinctrl_probe,
> +};
> diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
> index d9d61fdb72..1481c1e51c 100644
> --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
> +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
> @@ -433,7 +433,7 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
> int prop_len, param;
> const u32 *data;
> ofnode node;
> -#ifdef CONFIG_OF_LIVE
> +#if CONFIG_IS_ENABLED(OF_LIVE)
> const struct device_node *np;
> struct property *pp;
> #else
> @@ -473,7 +473,7 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
> node = ofnode_get_by_phandle(conf);
> if (!ofnode_valid(node))
> return -ENODEV;
> -#ifdef CONFIG_OF_LIVE
> +#if CONFIG_IS_ENABLED(OF_LIVE)
> np = ofnode_to_np(node);
> for (pp = np->properties; pp; pp = pp->next) {
> prop_name = pp->name;
> @@ -548,13 +548,15 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d
>
> /* preset iomux offset value, set new start value */
> if (iom->offset >= 0) {
> - if (iom->type & IOMUX_SOURCE_PMU)
> + if ((iom->type & IOMUX_SOURCE_PMU) || \
> + (iom->type & IOMUX_L_SOURCE_PMU))
> pmu_offs = iom->offset;
> else
> grf_offs = iom->offset;
> } else { /* set current iomux offset */
> - iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
> - pmu_offs : grf_offs;
> + iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
> + (iom->type & IOMUX_L_SOURCE_PMU)) ?
> + pmu_offs : grf_offs;
> }
>
> /* preset drv offset value, set new start value */
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 1/9] gpio: gpio-rockchip: parse gpio-ranges for bank id
2023-02-13 22:27 ` [PATCH V2 1/9] gpio: gpio-rockchip: parse gpio-ranges for bank id Chris Morgan
2023-02-22 7:44 ` Kever Yang
@ 2023-02-22 10:59 ` Johan Jonker
2023-02-23 8:59 ` Linus Walleij
2 siblings, 0 replies; 33+ messages in thread
From: Johan Jonker @ 2023-02-22 10:59 UTC (permalink / raw)
To: kever.yang, Linus Walleij, heiko
Cc: sjg, philipp.tomsich, chenjh, pgwipeout, heiko.stuebner,
Chris Morgan, Chris Morgan, u-boot, Heiko Stuebner,
Bartosz Golaszewski
Hi Kever, Linus Walleij, Heiko,
My Linux proposal has a little different logic (see below) and was "Acked-by", but the merge status is unknown.
https://lore.kernel.org/linux-rockchip/890be9a0-8e82-a8f4-bc15-d5d1597343c2@gmail.com/
Could Linus/Heiko indicate if U-boot already can use this or are there other ideas?
Johan
On 2/13/23 23:27, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Use the new devicetree property of gpio-ranges to determine the GPIO
> bank ID. Preserve the "old" way of doing things too, so that boards
> can be migrated and tested gradually (I only have a 3566 and 3326 to
> test).
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> drivers/gpio/rk_gpio.c | 20 +++++++++++++++++---
> 1 file changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
> index 68f30157a9..98a79b5f4d 100644
> --- a/drivers/gpio/rk_gpio.c
> +++ b/drivers/gpio/rk_gpio.c
> @@ -142,6 +142,7 @@ static int rockchip_gpio_probe(struct udevice *dev)
> {
> struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> struct rockchip_gpio_priv *priv = dev_get_priv(dev);
> + struct ofnode_phandle_args args;
> char *end;
> int ret;
>
> @@ -150,9 +151,22 @@ static int rockchip_gpio_probe(struct udevice *dev)
> if (ret)
> return ret;
>
> - uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
> - end = strrchr(dev->name, '@');
> - priv->bank = trailing_strtoln(dev->name, end);
> + /*
> + * If "gpio-ranges" is present in the devicetree use it to parse
> + * the GPIO bank ID, otherwise use the legacy method.
> + */
> + ret = ofnode_parse_phandle_with_args(dev_ofnode(dev),
> + "gpio-ranges", NULL, 3,
> + 0, &args);
> + if (!ret || ret != -ENOENT) {
> + uc_priv->gpio_count = args.args[2];
> + priv->bank = args.args[1] / args.args[2];
priv->bank = args.args[1] / 32;
args.args[2] The number of pins is not is not constant for every gpio node (see data sheets).
Therefore can't be used as divider to get the bank number.
I used 32 as simple offset method, because of register size.
> + } else {
> + uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
> + end = strrchr(dev->name, '@');
> + priv->bank = trailing_strtoln(dev->name, end);
> + }
> +
> priv->name[0] = 'A' + priv->bank;
> uc_priv->bank_name = priv->name;
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 1/9] gpio: gpio-rockchip: parse gpio-ranges for bank id
2023-02-13 22:27 ` [PATCH V2 1/9] gpio: gpio-rockchip: parse gpio-ranges for bank id Chris Morgan
2023-02-22 7:44 ` Kever Yang
2023-02-22 10:59 ` Johan Jonker
@ 2023-02-23 8:59 ` Linus Walleij
2023-03-02 2:54 ` Kever Yang
2 siblings, 1 reply; 33+ messages in thread
From: Linus Walleij @ 2023-02-23 8:59 UTC (permalink / raw)
To: Chris Morgan
Cc: u-boot, heiko, sjg, philipp.tomsich, kever.yang, chenjh,
pgwipeout, heiko.stuebner, Chris Morgan
On Mon, Feb 13, 2023 at 11:28 PM Chris Morgan <macroalpha82@gmail.com> wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Use the new devicetree property of gpio-ranges to determine the GPIO
> bank ID. Preserve the "old" way of doing things too, so that boards
> can be migrated and tested gradually (I only have a 3566 and 3326 to
> test).
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
gpio-ranges are not supposed to be used like this, because there is
no semantic restrictions on how gpio-ranges are set up. For example:
gpio-ranges = <&pfc 0 0 32>;
that looks nice for this usecase, and I guess this is something
like what you have but then look at this from arch/arm/boot/dts/hi3620.dtsi:
gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
&pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
&pmx0 6 16 1 &pmx0 7 16 1>;
This is perfectly fine as well. Ranges can start anywhere in the hardware
offsets and go anywhere, and be set up in smaller chunks however
the author of the DTS file wants it.
I am pretty sure the same discontiguous
ranges can be encoded into the rk_gpio relevant DTS files as well,
so this is not a good solution to your problem.
What has been used in the past is just some unique hardware ID in the
device tree, so I would just add that.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 8/9] arm64: dts: rockchip: add gpio-ranges property to gpio nodes
2023-02-13 22:27 ` [PATCH V2 8/9] arm64: dts: rockchip: add gpio-ranges property to gpio nodes Chris Morgan
2023-02-22 7:47 ` Kever Yang
@ 2023-02-23 21:12 ` Vasily Khoruzhick
2023-02-28 11:26 ` Quentin Schulz
1 sibling, 1 reply; 33+ messages in thread
From: Vasily Khoruzhick @ 2023-02-23 21:12 UTC (permalink / raw)
To: Chris Morgan
Cc: u-boot, heiko, sjg, philipp.tomsich, kever.yang, chenjh,
pgwipeout, heiko.stuebner, Chris Morgan
On Mon, Feb 13, 2023 at 2:30 PM Chris Morgan <macroalpha82@gmail.com> wrote:
>
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Add gpio-ranges property to GPIO nodes so that the bank ID can
> be correctly derived for each GPIO bank.
Should not it be merged into linux first? Otherwise it will be
overwritten during the next dts sync with linux.
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> ---
> arch/arm/dts/rk356x.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi
> index 5706c3e24f..6492ace0de 100644
> --- a/arch/arm/dts/rk356x.dtsi
> +++ b/arch/arm/dts/rk356x.dtsi
> @@ -1806,6 +1806,7 @@
> interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
> gpio-controller;
> + gpio-ranges = <&pinctrl 0 0 32>;
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> @@ -1817,6 +1818,7 @@
> interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
> gpio-controller;
> + gpio-ranges = <&pinctrl 0 32 32>;
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> @@ -1828,6 +1830,7 @@
> interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
> gpio-controller;
> + gpio-ranges = <&pinctrl 0 64 32>;
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> @@ -1839,6 +1842,7 @@
> interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
> gpio-controller;
> + gpio-ranges = <&pinctrl 0 96 32>;
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> @@ -1850,6 +1854,7 @@
> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
> gpio-controller;
> + gpio-ranges = <&pinctrl 0 128 32>;
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller
2023-02-13 22:27 ` [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller Chris Morgan
` (2 preceding siblings ...)
2023-02-22 8:28 ` Kever Yang
@ 2023-02-23 22:14 ` Vasily Khoruzhick
2023-03-01 8:25 ` Eugen Hristev
4 siblings, 0 replies; 33+ messages in thread
From: Vasily Khoruzhick @ 2023-02-23 22:14 UTC (permalink / raw)
To: Chris Morgan
Cc: u-boot, heiko, sjg, philipp.tomsich, kever.yang, chenjh,
pgwipeout, heiko.stuebner, Chris Morgan
On Mon, Feb 13, 2023 at 2:30 PM Chris Morgan <macroalpha82@gmail.com> wrote:
>
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Add support for the newer GPIO controller used by the rk356x series,
> as well as the pinctrl device for the rk356x series. The GPIOv2
> controller has a write enable bit for some registers which differs
> from the older versions of the GPIO controller.
>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
With pinctrl part from
https://patchwork.ozlabs.org/project/uboot/patch/20230217115845.75303-11-jagan@amarulasolutions.com/
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
> ---
> arch/arm/include/asm/arch-rockchip/gpio.h | 38 ++
> drivers/gpio/rk_gpio.c | 49 +-
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl-rk3568.c | 453 ++++++++++++++++++
> .../pinctrl/rockchip/pinctrl-rockchip-core.c | 12 +-
> 5 files changed, 540 insertions(+), 13 deletions(-)
> create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c
>
> diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h
> index 1aaec5faec..15f5de321b 100644
> --- a/arch/arm/include/asm/arch-rockchip/gpio.h
> +++ b/arch/arm/include/asm/arch-rockchip/gpio.h
> @@ -6,6 +6,7 @@
> #ifndef _ASM_ARCH_GPIO_H
> #define _ASM_ARCH_GPIO_H
>
> +#if !defined(CONFIG_ROCKCHIP_RK3568)
> struct rockchip_gpio_regs {
> u32 swport_dr;
> u32 swport_ddr;
> @@ -22,7 +23,44 @@ struct rockchip_gpio_regs {
> u32 reserved1[(0x60 - 0x54) / 4];
> u32 ls_sync;
> };
> +
> check_member(rockchip_gpio_regs, ls_sync, 0x60);
> +#else
> +struct rockchip_gpio_regs {
> + u32 swport_dr_l; /* ADDRESS OFFSET: 0x0000 */
> + u32 swport_dr_h; /* ADDRESS OFFSET: 0x0004 */
> + u32 swport_ddr_l; /* ADDRESS OFFSET: 0x0008 */
> + u32 swport_ddr_h; /* ADDRESS OFFSET: 0x000c */
> + u32 int_en_l; /* ADDRESS OFFSET: 0x0010 */
> + u32 int_en_h; /* ADDRESS OFFSET: 0x0014 */
> + u32 int_mask_l; /* ADDRESS OFFSET: 0x0018 */
> + u32 int_mask_h; /* ADDRESS OFFSET: 0x001c */
> + u32 int_type_l; /* ADDRESS OFFSET: 0x0020 */
> + u32 int_type_h; /* ADDRESS OFFSET: 0x0024 */
> + u32 int_polarity_l; /* ADDRESS OFFSET: 0x0028 */
> + u32 int_polarity_h; /* ADDRESS OFFSET: 0x002c */
> + u32 int_bothedge_l; /* ADDRESS OFFSET: 0x0030 */
> + u32 int_bothedge_h; /* ADDRESS OFFSET: 0x0034 */
> + u32 debounce_l; /* ADDRESS OFFSET: 0x0038 */
> + u32 debounce_h; /* ADDRESS OFFSET: 0x003c */
> + u32 dbclk_div_en_l; /* ADDRESS OFFSET: 0x0040 */
> + u32 dbclk_div_en_h; /* ADDRESS OFFSET: 0x0044 */
> + u32 dbclk_div_con; /* ADDRESS OFFSET: 0x0048 */
> + u32 reserved004c; /* ADDRESS OFFSET: 0x004c */
> + u32 int_status; /* ADDRESS OFFSET: 0x0050 */
> + u32 reserved0054; /* ADDRESS OFFSET: 0x0054 */
> + u32 int_rawstatus; /* ADDRESS OFFSET: 0x0058 */
> + u32 reserved005c; /* ADDRESS OFFSET: 0x005c */
> + u32 port_eoi_l; /* ADDRESS OFFSET: 0x0060 */
> + u32 port_eoi_h; /* ADDRESS OFFSET: 0x0064 */
> + u32 reserved0068[2]; /* ADDRESS OFFSET: 0x0068 */
> + u32 ext_port; /* ADDRESS OFFSET: 0x0070 */
> + u32 reserved0074; /* ADDRESS OFFSET: 0x0074 */
> + u32 ver_id; /* ADDRESS OFFSET: 0x0078 */
> +};
> +
> +check_member(rockchip_gpio_regs, ver_id, 0x0078);
> +#endif
>
> enum gpio_pu_pd {
> GPIO_PULL_NORMAL = 0,
> diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
> index 98a79b5f4d..e2653be058 100644
> --- a/drivers/gpio/rk_gpio.c
> +++ b/drivers/gpio/rk_gpio.c
> @@ -2,12 +2,15 @@
> /*
> * (C) Copyright 2015 Google, Inc
> *
> - * (C) Copyright 2008-2014 Rockchip Electronics
> + * (C) Copyright 2008-2023 Rockchip Electronics
> * Peter, Software Engineering, <superpeter.cai@gmail.com>.
> + * Jianqun Xu, Software Engineering, <jay.xu@rock-chips.com>.
> */
>
> #include <common.h>
> #include <dm.h>
> +#include <dm/of_access.h>
> +#include <dm/device_compat.h>
> #include <syscon.h>
> #include <linux/errno.h>
> #include <asm/gpio.h>
> @@ -23,6 +26,35 @@ enum {
>
> #define OFFSET_TO_BIT(bit) (1UL << (bit))
>
> +/*
> + * Newer Rockchip devices have additional registers that must be
> + * accounted for.
> + */
> +#if defined(CONFIG_ROCKCHIP_RK3568)
> +#define GPIO_VER 2
> +#define REG_L(R) (R##_l)
> +#define REG_H(R) (R##_h)
> +#define READ_REG(REG) ((readl(REG_L(REG)) & 0xFFFF) | \
> + ((readl(REG_H(REG)) & 0xFFFF) << 16))
> +#define WRITE_REG(REG, VAL) \
> +{\
> + writel(((VAL) & 0xFFFF) | 0xFFFF0000, REG_L(REG)); \
> + writel((((VAL) & 0xFFFF0000) >> 16) | 0xFFFF0000, REG_H(REG));\
> +}
> +#define CLRBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) & ~(MASK))
> +#define SETBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) | (MASK))
> +#define CLRSETBITS_LE32(REG, MASK, VAL) WRITE_REG(REG, \
> + (READ_REG(REG) & ~(MASK)) | (VAL))
> +
> +#else
> +#define GPIO_VER 1
> +#define READ_REG(REG) readl(REG)
> +#define WRITE_REG(REG, VAL) writel(VAL, REG)
> +#define CLRBITS_LE32(REG, MASK) clrbits_le32(REG, MASK)
> +#define SETBITS_LE32(REG, MASK) setbits_le32(REG, MASK)
> +#define CLRSETBITS_LE32(REG, MASK, VAL) clrsetbits_le32(REG, MASK, VAL)
> +#endif
> +
> struct rockchip_gpio_priv {
> struct rockchip_gpio_regs *regs;
> struct udevice *pinctrl;
> @@ -35,7 +68,7 @@ static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset)
> struct rockchip_gpio_priv *priv = dev_get_priv(dev);
> struct rockchip_gpio_regs *regs = priv->regs;
>
> - clrbits_le32(®s->swport_ddr, OFFSET_TO_BIT(offset));
> + CLRBITS_LE32(®s->swport_ddr, OFFSET_TO_BIT(offset));
>
> return 0;
> }
> @@ -47,8 +80,8 @@ static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset,
> struct rockchip_gpio_regs *regs = priv->regs;
> int mask = OFFSET_TO_BIT(offset);
>
> - clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0);
> - setbits_le32(®s->swport_ddr, mask);
> + CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0);
> + SETBITS_LE32(®s->swport_ddr, mask);
>
> return 0;
> }
> @@ -68,7 +101,7 @@ static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
> struct rockchip_gpio_regs *regs = priv->regs;
> int mask = OFFSET_TO_BIT(offset);
>
> - clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0);
> + CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0);
>
> return 0;
> }
> @@ -86,14 +119,14 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
> ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
> if (ret)
> return ret;
> - is_output = readl(®s->swport_ddr) & OFFSET_TO_BIT(offset);
> + is_output = READ_REG(®s->swport_ddr) & OFFSET_TO_BIT(offset);
>
> return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
> #endif
> }
>
> /* Simple SPL interface to GPIOs */
> -#ifdef CONFIG_SPL_BUILD
> +#if defined(CONFIG_SPL_BUILD) && (GPIO_VER == 1)
>
> enum {
> PULL_NONE_1V8 = 0,
> @@ -143,7 +176,7 @@ static int rockchip_gpio_probe(struct udevice *dev)
> struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> struct rockchip_gpio_priv *priv = dev_get_priv(dev);
> struct ofnode_phandle_args args;
> - char *end;
> + char *end = NULL;
> int ret;
>
> priv->regs = dev_read_addr_ptr(dev);
> diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
> index 9884355473..90461ae881 100644
> --- a/drivers/pinctrl/rockchip/Makefile
> +++ b/drivers/pinctrl/rockchip/Makefile
> @@ -14,5 +14,6 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o
> obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
> obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
> +obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
> obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
> obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o
> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
> new file mode 100644
> index 0000000000..dce1c1e7ee
> --- /dev/null
> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
> @@ -0,0 +1,453 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2020 Rockchip Electronics Co., Ltd
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <dm/pinctrl.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +
> +#include "pinctrl-rockchip.h"
> +
> +static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
> + /* CAN0 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)),
> + /* CAN0 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)),
> + /* CAN1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)),
> + /* CAN1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)),
> + /* CAN2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)),
> + /* CAN2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)),
> + /* EDPDP_HPDIN IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)),
> + /* EDPDP_HPDIN IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)),
> + /* GMAC1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 0)),
> + /* GMAC1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PA7, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 1)),
> + /* HDMITX IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PD1, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 0)),
> + /* HDMITX IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO0, RK_PC7, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 1)),
> + /* I2C2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PB6, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 0)),
> + /* I2C2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PB4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 1)),
> + /* I2C3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA0, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(0, 0, 0)),
> + /* I2C3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(0, 0, 1)),
> + /* I2C4 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PB2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(2, 2, 0)),
> + /* I2C4 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)),
> + /* I2C5 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)),
> + /* I2C5 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)),
> + /* PWM4 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)),
> + /* PWM4 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)),
> + /* PWM5 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)),
> + /* PWM5 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)),
> + /* PWM6 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)),
> + /* PWM6 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)),
> + /* PWM7 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)),
> + /* PWM7 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)),
> + /* PWM8 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)),
> + /* PWM8 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)),
> + /* PWM9 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)),
> + /* PWM9 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)),
> + /* PWM10 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)),
> + /* PWM10 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)),
> + /* PWM11 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)),
> + /* PWM11 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)),
> + /* PWM12 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)),
> + /* PWM12 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)),
> + /* PWM13 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)),
> + /* PWM13 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)),
> + /* PWM14 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)),
> + /* PWM14 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)),
> + /* PWM15 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)),
> + /* PWM15 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)),
> + /* SDMMC2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)),
> + /* SDMMC2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)),
> + /* SPI0 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)),
> + /* SPI0 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(0, 0, 1)),
> + /* SPI1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PB5, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 0)),
> + /* SPI1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 1)),
> + /* SPI2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(4, 4, 0)),
> + /* SPI2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(4, 4, 1)),
> + /* SPI3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)),
> + /* SPI3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)),
> + /* UART1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)),
> + /* UART1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)),
> + /* UART2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)),
> + /* UART2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)),
> + /* UART3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)),
> + /* UART3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(12, 12, 1)),
> + /* UART4 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(14, 14, 0)),
> + /* UART4 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(14, 14, 1)),
> + /* UART5 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PA2, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(0, 0, 0)),
> + /* UART5 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(0, 0, 1)),
> + /* UART6 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PA4, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 0)),
> + /* UART6 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)),
> + /* UART7 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)),
> + /* UART7 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)),
> + /* UART7 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)),
> + /* UART8 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)),
> + /* UART8 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)),
> + /* UART9 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)),
> + /* UART9 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 1)),
> + /* UART9 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO4, RK_PA4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 2)),
> + /* I2S1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(11, 10, 0)),
> + /* I2S1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(11, 10, 1)),
> + /* I2S1 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(11, 10, 2)),
> + /* I2S2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(12, 12, 0)),
> + /* I2S2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)),
> + /* I2S3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)),
> + /* I2S3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)),
> + /* PDM IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)),
> + /* PDM IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)),
> + /* PCIE20 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)),
> + /* PCIE20 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)),
> + /* PCIE20 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)),
> + /* PCIE30X1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(5, 4, 0)),
> + /* PCIE30X1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 1)),
> + /* PCIE30X1 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 2)),
> + /* PCIE30X2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PA6, RK_FUNC_2, 0x0314, RK_GENMASK_VAL(7, 6, 0)),
> + /* PCIE30X2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 1)),
> + /* PCIE30X2 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 2)),
> +};
> +
> +static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int iomux_num = (pin / 8);
> + struct regmap *regmap;
> + int reg, ret, mask;
> + u8 bit;
> + u32 data;
> +
> + debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
> +
> + if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
> + regmap = priv->regmap_pmu;
> + else
> + regmap = priv->regmap_base;
> +
> + reg = bank->iomux[iomux_num].offset;
> + if ((pin % 8) >= 4)
> + reg += 0x4;
> + bit = (pin % 4) * 4;
> + mask = 0xf;
> +
> + data = (mask << (bit + 16));
> + data |= (mux & mask) << bit;
> + ret = regmap_write(regmap, reg, data);
> +
> + return ret;
> +}
> +
> +#define RK3568_PULL_PMU_OFFSET 0x20
> +#define RK3568_PULL_GRF_OFFSET 0x80
> +#define RK3568_PULL_BITS_PER_PIN 2
> +#define RK3568_PULL_PINS_PER_REG 8
> +#define RK3568_PULL_BANK_STRIDE 0x10
> +
> +static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *info = bank->priv;
> +
> + if (bank->bank_num == 0) {
> + *regmap = info->regmap_pmu;
> + *reg = RK3568_PULL_PMU_OFFSET;
> + *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
> + } else {
> + *regmap = info->regmap_base;
> + *reg = RK3568_PULL_GRF_OFFSET;
> + *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
> + *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
> + *bit *= RK3568_PULL_BITS_PER_PIN;
> +}
> +
> +#define RK3568_DRV_PMU_OFFSET 0x70
> +#define RK3568_DRV_GRF_OFFSET 0x200
> +#define RK3568_DRV_BITS_PER_PIN 8
> +#define RK3568_DRV_PINS_PER_REG 2
> +#define RK3568_DRV_BANK_STRIDE 0x40
> +
> +static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *info = bank->priv;
> +
> + /* The first 32 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = info->regmap_pmu;
> + *reg = RK3568_DRV_PMU_OFFSET;
> + } else {
> + *regmap = info->regmap_base;
> + *reg = RK3568_DRV_GRF_OFFSET;
> + *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
> + *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
> + *bit *= RK3568_DRV_BITS_PER_PIN;
> +}
> +
> +#define RK3568_SCHMITT_BITS_PER_PIN 2
> +#define RK3568_SCHMITT_PINS_PER_REG 8
> +#define RK3568_SCHMITT_BANK_STRIDE 0x10
> +#define RK3568_SCHMITT_GRF_OFFSET 0xc0
> +#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
> +
> +static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *info = bank->priv;
> +
> + if (bank->bank_num == 0) {
> + *regmap = info->regmap_pmu;
> + *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
> + } else {
> + *regmap = info->regmap_base;
> + *reg = RK3568_SCHMITT_GRF_OFFSET;
> + *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
> + *bit *= RK3568_SCHMITT_BITS_PER_PIN;
> +
> + return 0;
> +}
> +
> +static int rk3568_set_pull(struct rockchip_pin_bank *bank,
> + int pin_num, int pull)
> +{
> + struct regmap *regmap;
> + int reg, ret;
> + u8 bit, type;
> + u32 data;
> +
> + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
> + return -EOPNOTSUPP;
> +
> + rk3568_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> + type = bank->pull_type[pin_num / 8];
> + ret = rockchip_translate_pull_value(type, pull);
> + if (ret < 0) {
> + debug("unsupported pull setting %d\n", pull);
> + return ret;
> + }
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
> +
> + data |= (ret << bit);
> + ret = regmap_write(regmap, reg, data);
> +
> + return ret;
> +}
> +
> +static int rk3568_set_drive(struct rockchip_pin_bank *bank,
> + int pin_num, int strength)
> +{
> + struct regmap *regmap;
> + int reg;
> + u32 data;
> + u8 bit;
> + int drv = (1 << (strength + 1)) - 1;
> + int ret = 0;
> +
> + rk3568_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16);
> + data |= (drv << bit);
> +
> + ret = regmap_write(regmap, reg, data);
> + if (ret)
> + return ret;
> +
> + if (bank->bank_num == 1 && pin_num == 21)
> + reg = 0x0840;
> + else if (bank->bank_num == 2 && pin_num == 2)
> + reg = 0x0844;
> + else if (bank->bank_num == 2 && pin_num == 8)
> + reg = 0x0848;
> + else if (bank->bank_num == 3 && pin_num == 0)
> + reg = 0x084c;
> + else if (bank->bank_num == 3 && pin_num == 6)
> + reg = 0x0850;
> + else if (bank->bank_num == 4 && pin_num == 0)
> + reg = 0x0854;
> + else
> + return 0;
> +
> + data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16;
> + data |= drv;
> +
> + return regmap_write(regmap, reg, data);
> +}
> +
> +static int rk3568_set_schmitt(struct rockchip_pin_bank *bank,
> + int pin_num, int enable)
> +{
> + struct regmap *regmap;
> + int reg;
> + u32 data;
> + u8 bit;
> +
> + rk3568_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
> + data |= (enable << bit);
> +
> + return regmap_write(regmap, reg, data);
> +}
> +
> +static struct rockchip_pin_bank rk3568_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
> + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
> + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
> + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> +};
> +
> +static const struct rockchip_pin_ctrl rk3568_pin_ctrl = {
> + .pin_banks = rk3568_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
> + .nr_pins = 160,
> + .grf_mux_offset = 0x0,
> + .pmu_mux_offset = 0x0,
> + .iomux_routes = rk3568_mux_route_data,
> + .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
> + .set_mux = rk3568_set_mux,
> + .set_pull = rk3568_set_pull,
> + .set_drive = rk3568_set_drive,
> + .set_schmitt = rk3568_set_schmitt,
> +};
> +
> +static const struct udevice_id rk3568_pinctrl_ids[] = {
> + {
> + .compatible = "rockchip,rk3568-pinctrl",
> + .data = (ulong)&rk3568_pin_ctrl
> + },
> + { }
> +};
> +
> +U_BOOT_DRIVER(pinctrl_rk3568) = {
> + .name = "rockchip_rk3568_pinctrl",
> + .id = UCLASS_PINCTRL,
> + .of_match = rk3568_pinctrl_ids,
> + .priv_auto = sizeof(struct rockchip_pinctrl_priv),
> + .ops = &rockchip_pinctrl_ops,
> +#if !IS_ENABLED(CONFIG_OF_PLATDATA)
> + .bind = dm_scan_fdt_dev,
> +#endif
> + .probe = rockchip_pinctrl_probe,
> +};
> diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
> index d9d61fdb72..1481c1e51c 100644
> --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
> +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
> @@ -433,7 +433,7 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
> int prop_len, param;
> const u32 *data;
> ofnode node;
> -#ifdef CONFIG_OF_LIVE
> +#if CONFIG_IS_ENABLED(OF_LIVE)
> const struct device_node *np;
> struct property *pp;
> #else
> @@ -473,7 +473,7 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
> node = ofnode_get_by_phandle(conf);
> if (!ofnode_valid(node))
> return -ENODEV;
> -#ifdef CONFIG_OF_LIVE
> +#if CONFIG_IS_ENABLED(OF_LIVE)
> np = ofnode_to_np(node);
> for (pp = np->properties; pp; pp = pp->next) {
> prop_name = pp->name;
> @@ -548,13 +548,15 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d
>
> /* preset iomux offset value, set new start value */
> if (iom->offset >= 0) {
> - if (iom->type & IOMUX_SOURCE_PMU)
> + if ((iom->type & IOMUX_SOURCE_PMU) || \
> + (iom->type & IOMUX_L_SOURCE_PMU))
> pmu_offs = iom->offset;
> else
> grf_offs = iom->offset;
> } else { /* set current iomux offset */
> - iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
> - pmu_offs : grf_offs;
> + iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
> + (iom->type & IOMUX_L_SOURCE_PMU)) ?
> + pmu_offs : grf_offs;
> }
>
> /* preset drv offset value, set new start value */
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 8/9] arm64: dts: rockchip: add gpio-ranges property to gpio nodes
2023-02-23 21:12 ` Vasily Khoruzhick
@ 2023-02-28 11:26 ` Quentin Schulz
2023-03-02 2:49 ` Kever Yang
0 siblings, 1 reply; 33+ messages in thread
From: Quentin Schulz @ 2023-02-28 11:26 UTC (permalink / raw)
To: Vasily Khoruzhick, Chris Morgan
Cc: u-boot, heiko, sjg, philipp.tomsich, kever.yang, chenjh,
pgwipeout, heiko.stuebner, Chris Morgan
Hi Vasily,
On 2/23/23 22:12, Vasily Khoruzhick wrote:
> On Mon, Feb 13, 2023 at 2:30 PM Chris Morgan <macroalpha82@gmail.com> wrote:
>>
>> From: Chris Morgan <macromorgan@hotmail.com>
>>
>> Add gpio-ranges property to GPIO nodes so that the bank ID can
>> be correctly derived for each GPIO bank.
>
> Should not it be merged into linux first? Otherwise it will be
> overwritten during the next dts sync with linux.
>
Considering that Linux maintainers have just rejected this
implementation, yes we should wait on it being merged before supporting
it in U-Boot :)
Cheers,
Quentin
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller
2023-02-13 22:27 ` [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller Chris Morgan
` (3 preceding siblings ...)
2023-02-23 22:14 ` Vasily Khoruzhick
@ 2023-03-01 8:25 ` Eugen Hristev
2023-03-01 15:02 ` Simon Glass
4 siblings, 1 reply; 33+ messages in thread
From: Eugen Hristev @ 2023-03-01 8:25 UTC (permalink / raw)
To: Chris Morgan, u-boot
Cc: heiko, sjg, philipp.tomsich, kever.yang, chenjh, pgwipeout,
heiko.stuebner, Chris Morgan
On 2/14/23 00:27, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Add support for the newer GPIO controller used by the rk356x series,
> as well as the pinctrl device for the rk356x series. The GPIOv2
> controller has a write enable bit for some registers which differs
> from the older versions of the GPIO controller.
>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Hi Chris,
In the file below you have added
> + * Jianqun Xu, Software Engineering, <jay.xu@rock-chips.com>.
as copyright owner, maybe add him as co-author of this patch ? Or what
was his contribution ?
> ---
> arch/arm/include/asm/arch-rockchip/gpio.h | 38 ++
> drivers/gpio/rk_gpio.c | 49 +-
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl-rk3568.c | 453 ++++++++++++++++++
> .../pinctrl/rockchip/pinctrl-rockchip-core.c | 12 +-
> 5 files changed, 540 insertions(+), 13 deletions(-)
> create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c
>
> diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h
> index 1aaec5faec..15f5de321b 100644
> --- a/arch/arm/include/asm/arch-rockchip/gpio.h
> +++ b/arch/arm/include/asm/arch-rockchip/gpio.h
> @@ -6,6 +6,7 @@
> #ifndef _ASM_ARCH_GPIO_H
> #define _ASM_ARCH_GPIO_H
>
> +#if !defined(CONFIG_ROCKCHIP_RK3568)
Can't we figure out from the compatible which struct layout to use ?
Using conditionally compile code makes things difficult to read after
some time.
> struct rockchip_gpio_regs {
> u32 swport_dr;
> u32 swport_ddr;
> @@ -22,7 +23,44 @@ struct rockchip_gpio_regs {
> u32 reserved1[(0x60 - 0x54) / 4];
> u32 ls_sync;
> };
> +
> check_member(rockchip_gpio_regs, ls_sync, 0x60);
> +#else
> +struct rockchip_gpio_regs {
> + u32 swport_dr_l; /* ADDRESS OFFSET: 0x0000 */
> + u32 swport_dr_h; /* ADDRESS OFFSET: 0x0004 */
> + u32 swport_ddr_l; /* ADDRESS OFFSET: 0x0008 */
> + u32 swport_ddr_h; /* ADDRESS OFFSET: 0x000c */
> + u32 int_en_l; /* ADDRESS OFFSET: 0x0010 */
> + u32 int_en_h; /* ADDRESS OFFSET: 0x0014 */
> + u32 int_mask_l; /* ADDRESS OFFSET: 0x0018 */
> + u32 int_mask_h; /* ADDRESS OFFSET: 0x001c */
> + u32 int_type_l; /* ADDRESS OFFSET: 0x0020 */
> + u32 int_type_h; /* ADDRESS OFFSET: 0x0024 */
> + u32 int_polarity_l; /* ADDRESS OFFSET: 0x0028 */
> + u32 int_polarity_h; /* ADDRESS OFFSET: 0x002c */
> + u32 int_bothedge_l; /* ADDRESS OFFSET: 0x0030 */
> + u32 int_bothedge_h; /* ADDRESS OFFSET: 0x0034 */
> + u32 debounce_l; /* ADDRESS OFFSET: 0x0038 */
> + u32 debounce_h; /* ADDRESS OFFSET: 0x003c */
> + u32 dbclk_div_en_l; /* ADDRESS OFFSET: 0x0040 */
> + u32 dbclk_div_en_h; /* ADDRESS OFFSET: 0x0044 */
> + u32 dbclk_div_con; /* ADDRESS OFFSET: 0x0048 */
> + u32 reserved004c; /* ADDRESS OFFSET: 0x004c */
> + u32 int_status; /* ADDRESS OFFSET: 0x0050 */
> + u32 reserved0054; /* ADDRESS OFFSET: 0x0054 */
> + u32 int_rawstatus; /* ADDRESS OFFSET: 0x0058 */
> + u32 reserved005c; /* ADDRESS OFFSET: 0x005c */
> + u32 port_eoi_l; /* ADDRESS OFFSET: 0x0060 */
> + u32 port_eoi_h; /* ADDRESS OFFSET: 0x0064 */
> + u32 reserved0068[2]; /* ADDRESS OFFSET: 0x0068 */
> + u32 ext_port; /* ADDRESS OFFSET: 0x0070 */
> + u32 reserved0074; /* ADDRESS OFFSET: 0x0074 */
> + u32 ver_id; /* ADDRESS OFFSET: 0x0078 */
> +};
> +
> +check_member(rockchip_gpio_regs, ver_id, 0x0078);
> +#endif
>
> enum gpio_pu_pd {
> GPIO_PULL_NORMAL = 0,
> diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
> index 98a79b5f4d..e2653be058 100644
> --- a/drivers/gpio/rk_gpio.c
> +++ b/drivers/gpio/rk_gpio.c
> @@ -2,12 +2,15 @@
> /*
> * (C) Copyright 2015 Google, Inc
> *
> - * (C) Copyright 2008-2014 Rockchip Electronics
> + * (C) Copyright 2008-2023 Rockchip Electronics
> * Peter, Software Engineering, <superpeter.cai@gmail.com>.
> + * Jianqun Xu, Software Engineering, <jay.xu@rock-chips.com>.
> */
>
> #include <common.h>
> #include <dm.h>
> +#include <dm/of_access.h>
> +#include <dm/device_compat.h>
> #include <syscon.h>
> #include <linux/errno.h>
> #include <asm/gpio.h>
> @@ -23,6 +26,35 @@ enum {
>
> #define OFFSET_TO_BIT(bit) (1UL << (bit))
>
> +/*
> + * Newer Rockchip devices have additional registers that must be
> + * accounted for.
> + */
> +#if defined(CONFIG_ROCKCHIP_RK3568)
> +#define GPIO_VER 2
Why don't you use the gpio versioning from here:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpio/gpio-rockchip.c#n30
I think it's best to reuse the definitions from Linux kernel, as it's
already implemented there.
> +#define REG_L(R) (R##_l)
> +#define REG_H(R) (R##_h)
> +#define READ_REG(REG) ((readl(REG_L(REG)) & 0xFFFF) | \
> + ((readl(REG_H(REG)) & 0xFFFF) << 16))
> +#define WRITE_REG(REG, VAL) \
> +{\
> + writel(((VAL) & 0xFFFF) | 0xFFFF0000, REG_L(REG)); \
> + writel((((VAL) & 0xFFFF0000) >> 16) | 0xFFFF0000, REG_H(REG));\
> +}
> +#define CLRBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) & ~(MASK))
> +#define SETBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) | (MASK))
> +#define CLRSETBITS_LE32(REG, MASK, VAL) WRITE_REG(REG, \
> + (READ_REG(REG) & ~(MASK)) | (VAL))
> +
> +#else
> +#define GPIO_VER 1
ditto
> +#define READ_REG(REG) readl(REG)
> +#define WRITE_REG(REG, VAL) writel(VAL, REG)
> +#define CLRBITS_LE32(REG, MASK) clrbits_le32(REG, MASK)
> +#define SETBITS_LE32(REG, MASK) setbits_le32(REG, MASK)
> +#define CLRSETBITS_LE32(REG, MASK, VAL) clrsetbits_le32(REG, MASK, VAL)
> +#endif
> +
> struct rockchip_gpio_priv {
> struct rockchip_gpio_regs *regs;
> struct udevice *pinctrl;
> @@ -35,7 +68,7 @@ static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset)
> struct rockchip_gpio_priv *priv = dev_get_priv(dev);
> struct rockchip_gpio_regs *regs = priv->regs;
>
> - clrbits_le32(®s->swport_ddr, OFFSET_TO_BIT(offset));
> + CLRBITS_LE32(®s->swport_ddr, OFFSET_TO_BIT(offset));
>
> return 0;
> }
> @@ -47,8 +80,8 @@ static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset,
> struct rockchip_gpio_regs *regs = priv->regs;
> int mask = OFFSET_TO_BIT(offset);
>
> - clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0);
> - setbits_le32(®s->swport_ddr, mask);
> + CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0);
> + SETBITS_LE32(®s->swport_ddr, mask);
>
> return 0;
> }
> @@ -68,7 +101,7 @@ static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
> struct rockchip_gpio_regs *regs = priv->regs;
> int mask = OFFSET_TO_BIT(offset);
>
> - clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0);
> + CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0);
>
> return 0;
> }
> @@ -86,14 +119,14 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
> ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
> if (ret)
> return ret;
> - is_output = readl(®s->swport_ddr) & OFFSET_TO_BIT(offset);
> + is_output = READ_REG(®s->swport_ddr) & OFFSET_TO_BIT(offset);
>
> return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
> #endif
> }
>
> /* Simple SPL interface to GPIOs */
> -#ifdef CONFIG_SPL_BUILD
> +#if defined(CONFIG_SPL_BUILD) && (GPIO_VER == 1)
>
> enum {
> PULL_NONE_1V8 = 0,
> @@ -143,7 +176,7 @@ static int rockchip_gpio_probe(struct udevice *dev)
> struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> struct rockchip_gpio_priv *priv = dev_get_priv(dev);
> struct ofnode_phandle_args args;
> - char *end;
> + char *end = NULL;
> int ret;
>
> priv->regs = dev_read_addr_ptr(dev);
> diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
> index 9884355473..90461ae881 100644
> --- a/drivers/pinctrl/rockchip/Makefile
> +++ b/drivers/pinctrl/rockchip/Makefile
> @@ -14,5 +14,6 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o
> obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
> obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
> +obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
> obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
> obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o
> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
> new file mode 100644
> index 0000000000..dce1c1e7ee
> --- /dev/null
> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
> @@ -0,0 +1,453 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2020 Rockchip Electronics Co., Ltd
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <dm/pinctrl.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +
> +#include "pinctrl-rockchip.h"
> +
> +static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
> + /* CAN0 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)),
> + /* CAN0 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)),
> + /* CAN1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)),
> + /* CAN1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)),
> + /* CAN2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)),
> + /* CAN2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)),
> + /* EDPDP_HPDIN IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)),
> + /* EDPDP_HPDIN IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)),
> + /* GMAC1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 0)),
> + /* GMAC1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PA7, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 1)),
> + /* HDMITX IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PD1, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 0)),
> + /* HDMITX IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO0, RK_PC7, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 1)),
> + /* I2C2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PB6, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 0)),
> + /* I2C2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PB4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 1)),
> + /* I2C3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA0, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(0, 0, 0)),
> + /* I2C3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(0, 0, 1)),
> + /* I2C4 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PB2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(2, 2, 0)),
> + /* I2C4 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)),
> + /* I2C5 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)),
> + /* I2C5 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)),
> + /* PWM4 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)),
> + /* PWM4 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)),
> + /* PWM5 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)),
> + /* PWM5 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)),
> + /* PWM6 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)),
> + /* PWM6 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)),
> + /* PWM7 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)),
> + /* PWM7 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)),
> + /* PWM8 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)),
> + /* PWM8 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)),
> + /* PWM9 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)),
> + /* PWM9 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)),
> + /* PWM10 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)),
> + /* PWM10 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)),
> + /* PWM11 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)),
> + /* PWM11 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)),
> + /* PWM12 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)),
> + /* PWM12 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)),
> + /* PWM13 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)),
> + /* PWM13 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)),
> + /* PWM14 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)),
> + /* PWM14 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)),
> + /* PWM15 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)),
> + /* PWM15 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)),
> + /* SDMMC2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)),
> + /* SDMMC2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)),
> + /* SPI0 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)),
> + /* SPI0 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(0, 0, 1)),
> + /* SPI1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PB5, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 0)),
> + /* SPI1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 1)),
> + /* SPI2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(4, 4, 0)),
> + /* SPI2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(4, 4, 1)),
> + /* SPI3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)),
> + /* SPI3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)),
> + /* UART1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)),
> + /* UART1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)),
> + /* UART2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)),
> + /* UART2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)),
> + /* UART3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)),
> + /* UART3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(12, 12, 1)),
> + /* UART4 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(14, 14, 0)),
> + /* UART4 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(14, 14, 1)),
> + /* UART5 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PA2, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(0, 0, 0)),
> + /* UART5 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(0, 0, 1)),
> + /* UART6 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PA4, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 0)),
> + /* UART6 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)),
> + /* UART7 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)),
> + /* UART7 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)),
> + /* UART7 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)),
> + /* UART8 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)),
> + /* UART8 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)),
> + /* UART9 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)),
> + /* UART9 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 1)),
> + /* UART9 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO4, RK_PA4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 2)),
> + /* I2S1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(11, 10, 0)),
> + /* I2S1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(11, 10, 1)),
> + /* I2S1 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(11, 10, 2)),
> + /* I2S2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(12, 12, 0)),
> + /* I2S2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)),
> + /* I2S3 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)),
> + /* I2S3 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)),
> + /* PDM IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)),
> + /* PDM IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)),
> + /* PCIE20 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)),
> + /* PCIE20 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)),
> + /* PCIE20 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)),
> + /* PCIE30X1 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(5, 4, 0)),
> + /* PCIE30X1 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 1)),
> + /* PCIE30X1 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 2)),
> + /* PCIE30X2 IO mux selection M0 */
> + MR_TOPGRF(RK_GPIO0, RK_PA6, RK_FUNC_2, 0x0314, RK_GENMASK_VAL(7, 6, 0)),
> + /* PCIE30X2 IO mux selection M1 */
> + MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 1)),
> + /* PCIE30X2 IO mux selection M2 */
> + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 2)),
> +};
> +
> +static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int iomux_num = (pin / 8);
> + struct regmap *regmap;
> + int reg, ret, mask;
> + u8 bit;
> + u32 data;
> +
> + debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
> +
> + if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
> + regmap = priv->regmap_pmu;
> + else
> + regmap = priv->regmap_base;
> +
> + reg = bank->iomux[iomux_num].offset;
> + if ((pin % 8) >= 4)
> + reg += 0x4;
> + bit = (pin % 4) * 4;
> + mask = 0xf;
> +
> + data = (mask << (bit + 16));
> + data |= (mux & mask) << bit;
> + ret = regmap_write(regmap, reg, data);
> +
> + return ret;
> +}
> +
> +#define RK3568_PULL_PMU_OFFSET 0x20
> +#define RK3568_PULL_GRF_OFFSET 0x80
> +#define RK3568_PULL_BITS_PER_PIN 2
> +#define RK3568_PULL_PINS_PER_REG 8
> +#define RK3568_PULL_BANK_STRIDE 0x10
> +
> +static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *info = bank->priv;
> +
> + if (bank->bank_num == 0) {
> + *regmap = info->regmap_pmu;
> + *reg = RK3568_PULL_PMU_OFFSET;
> + *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
> + } else {
> + *regmap = info->regmap_base;
> + *reg = RK3568_PULL_GRF_OFFSET;
> + *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
> + *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
> + *bit *= RK3568_PULL_BITS_PER_PIN;
> +}
> +
> +#define RK3568_DRV_PMU_OFFSET 0x70
> +#define RK3568_DRV_GRF_OFFSET 0x200
> +#define RK3568_DRV_BITS_PER_PIN 8
> +#define RK3568_DRV_PINS_PER_REG 2
> +#define RK3568_DRV_BANK_STRIDE 0x40
> +
> +static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *info = bank->priv;
> +
> + /* The first 32 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = info->regmap_pmu;
> + *reg = RK3568_DRV_PMU_OFFSET;
> + } else {
> + *regmap = info->regmap_base;
> + *reg = RK3568_DRV_GRF_OFFSET;
> + *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
> + *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
> + *bit *= RK3568_DRV_BITS_PER_PIN;
> +}
> +
> +#define RK3568_SCHMITT_BITS_PER_PIN 2
> +#define RK3568_SCHMITT_PINS_PER_REG 8
> +#define RK3568_SCHMITT_BANK_STRIDE 0x10
> +#define RK3568_SCHMITT_GRF_OFFSET 0xc0
> +#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
> +
> +static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *info = bank->priv;
> +
> + if (bank->bank_num == 0) {
> + *regmap = info->regmap_pmu;
> + *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
> + } else {
> + *regmap = info->regmap_base;
> + *reg = RK3568_SCHMITT_GRF_OFFSET;
> + *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
> + *bit *= RK3568_SCHMITT_BITS_PER_PIN;
> +
> + return 0;
> +}
> +
> +static int rk3568_set_pull(struct rockchip_pin_bank *bank,
> + int pin_num, int pull)
> +{
> + struct regmap *regmap;
> + int reg, ret;
> + u8 bit, type;
> + u32 data;
> +
> + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
> + return -EOPNOTSUPP;
> +
> + rk3568_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> + type = bank->pull_type[pin_num / 8];
> + ret = rockchip_translate_pull_value(type, pull);
> + if (ret < 0) {
> + debug("unsupported pull setting %d\n", pull);
> + return ret;
> + }
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
> +
> + data |= (ret << bit);
> + ret = regmap_write(regmap, reg, data);
> +
> + return ret;
> +}
> +
> +static int rk3568_set_drive(struct rockchip_pin_bank *bank,
> + int pin_num, int strength)
> +{
> + struct regmap *regmap;
> + int reg;
> + u32 data;
> + u8 bit;
> + int drv = (1 << (strength + 1)) - 1;
> + int ret = 0;
> +
> + rk3568_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16);
> + data |= (drv << bit);
> +
> + ret = regmap_write(regmap, reg, data);
> + if (ret)
> + return ret;
> +
> + if (bank->bank_num == 1 && pin_num == 21)
> + reg = 0x0840;
> + else if (bank->bank_num == 2 && pin_num == 2)
> + reg = 0x0844;
> + else if (bank->bank_num == 2 && pin_num == 8)
> + reg = 0x0848;
> + else if (bank->bank_num == 3 && pin_num == 0)
> + reg = 0x084c;
> + else if (bank->bank_num == 3 && pin_num == 6)
> + reg = 0x0850;
> + else if (bank->bank_num == 4 && pin_num == 0)
> + reg = 0x0854;
> + else
> + return 0;
> +
> + data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16;
> + data |= drv;
> +
> + return regmap_write(regmap, reg, data);
> +}
> +
> +static int rk3568_set_schmitt(struct rockchip_pin_bank *bank,
> + int pin_num, int enable)
> +{
> + struct regmap *regmap;
> + int reg;
> + u32 data;
> + u8 bit;
> +
> + rk3568_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
> + data |= (enable << bit);
> +
> + return regmap_write(regmap, reg, data);
> +}
> +
> +static struct rockchip_pin_bank rk3568_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
> + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
> + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
> + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT),
> +};
> +
> +static const struct rockchip_pin_ctrl rk3568_pin_ctrl = {
> + .pin_banks = rk3568_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
> + .nr_pins = 160,
> + .grf_mux_offset = 0x0,
> + .pmu_mux_offset = 0x0,
> + .iomux_routes = rk3568_mux_route_data,
> + .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
> + .set_mux = rk3568_set_mux,
> + .set_pull = rk3568_set_pull,
> + .set_drive = rk3568_set_drive,
> + .set_schmitt = rk3568_set_schmitt,
> +};
> +
> +static const struct udevice_id rk3568_pinctrl_ids[] = {
> + {
> + .compatible = "rockchip,rk3568-pinctrl",
> + .data = (ulong)&rk3568_pin_ctrl
> + },
> + { }
> +};
> +
> +U_BOOT_DRIVER(pinctrl_rk3568) = {
> + .name = "rockchip_rk3568_pinctrl",
> + .id = UCLASS_PINCTRL,
> + .of_match = rk3568_pinctrl_ids,
> + .priv_auto = sizeof(struct rockchip_pinctrl_priv),
> + .ops = &rockchip_pinctrl_ops,
> +#if !IS_ENABLED(CONFIG_OF_PLATDATA)
you should use here #if IS_ENABLED(CONFIG_OF_REAL)
> + .bind = dm_scan_fdt_dev,
> +#endif
> + .probe = rockchip_pinctrl_probe,
> +};
> diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
> index d9d61fdb72..1481c1e51c 100644
> --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
> +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
> @@ -433,7 +433,7 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
> int prop_len, param;
> const u32 *data;
> ofnode node;
> -#ifdef CONFIG_OF_LIVE
> +#if CONFIG_IS_ENABLED(OF_LIVE)
> const struct device_node *np;
> struct property *pp;
> #else
> @@ -473,7 +473,7 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
> node = ofnode_get_by_phandle(conf);
> if (!ofnode_valid(node))
> return -ENODEV;
> -#ifdef CONFIG_OF_LIVE
> +#if CONFIG_IS_ENABLED(OF_LIVE)
> np = ofnode_to_np(node);
> for (pp = np->properties; pp; pp = pp->next) {
> prop_name = pp->name;
> @@ -548,13 +548,15 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d
>
> /* preset iomux offset value, set new start value */
> if (iom->offset >= 0) {
> - if (iom->type & IOMUX_SOURCE_PMU)
> + if ((iom->type & IOMUX_SOURCE_PMU) || \
> + (iom->type & IOMUX_L_SOURCE_PMU))
> pmu_offs = iom->offset;
> else
> grf_offs = iom->offset;
> } else { /* set current iomux offset */
> - iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
> - pmu_offs : grf_offs;
> + iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
> + (iom->type & IOMUX_L_SOURCE_PMU)) ?
> + pmu_offs : grf_offs;
> }
>
> /* preset drv offset value, set new start value */
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller
2023-03-01 8:25 ` Eugen Hristev
@ 2023-03-01 15:02 ` Simon Glass
0 siblings, 0 replies; 33+ messages in thread
From: Simon Glass @ 2023-03-01 15:02 UTC (permalink / raw)
To: Eugen Hristev
Cc: Chris Morgan, u-boot, heiko, philipp.tomsich, kever.yang, chenjh,
pgwipeout, heiko.stuebner, Chris Morgan
Hi,
On Wed, 1 Mar 2023 at 01:25, Eugen Hristev <eugen.hristev@collabora.com> wrote:
>
> On 2/14/23 00:27, Chris Morgan wrote:
> > From: Chris Morgan <macromorgan@hotmail.com>
> >
> > Add support for the newer GPIO controller used by the rk356x series,
> > as well as the pinctrl device for the rk356x series. The GPIOv2
> > controller has a write enable bit for some registers which differs
> > from the older versions of the GPIO controller.
> >
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
>
> Hi Chris,
>
> In the file below you have added
>
> > + * Jianqun Xu, Software Engineering, <jay.xu@rock-chips.com>.
>
> as copyright owner, maybe add him as co-author of this patch ? Or what
> was his contribution ?
>
>
> > ---
> > arch/arm/include/asm/arch-rockchip/gpio.h | 38 ++
> > drivers/gpio/rk_gpio.c | 49 +-
> > drivers/pinctrl/rockchip/Makefile | 1 +
> > drivers/pinctrl/rockchip/pinctrl-rk3568.c | 453 ++++++++++++++++++
> > .../pinctrl/rockchip/pinctrl-rockchip-core.c | 12 +-
> > 5 files changed, 540 insertions(+), 13 deletions(-)
> > create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c
> >
> > diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h
> > index 1aaec5faec..15f5de321b 100644
> > --- a/arch/arm/include/asm/arch-rockchip/gpio.h
> > +++ b/arch/arm/include/asm/arch-rockchip/gpio.h
> > @@ -6,6 +6,7 @@
> > #ifndef _ASM_ARCH_GPIO_H
> > #define _ASM_ARCH_GPIO_H
> >
> > +#if !defined(CONFIG_ROCKCHIP_RK3568)
>
> Can't we figure out from the compatible which struct layout to use ?
> Using conditionally compile code makes things difficult to read after
> some time.
Yes, we must not add arch-specific CONFIG things to drivers. Handle it
at runtime instead, i.e. the driver should handle both.
Regards,
SImon
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 8/9] arm64: dts: rockchip: add gpio-ranges property to gpio nodes
2023-02-28 11:26 ` Quentin Schulz
@ 2023-03-02 2:49 ` Kever Yang
2023-03-07 19:14 ` Vasily Khoruzhick
0 siblings, 1 reply; 33+ messages in thread
From: Kever Yang @ 2023-03-02 2:49 UTC (permalink / raw)
To: Quentin Schulz, Vasily Khoruzhick, Chris Morgan
Cc: u-boot, heiko, sjg, philipp.tomsich, chenjh, pgwipeout,
heiko.stuebner, Chris Morgan
Hi Quentin, Vasily,
On 2023/2/28 19:26, Quentin Schulz wrote:
> Hi Vasily,
>
> On 2/23/23 22:12, Vasily Khoruzhick wrote:
>> On Mon, Feb 13, 2023 at 2:30 PM Chris Morgan <macroalpha82@gmail.com>
>> wrote:
>>>
>>> From: Chris Morgan <macromorgan@hotmail.com>
>>>
>>> Add gpio-ranges property to GPIO nodes so that the bank ID can
>>> be correctly derived for each GPIO bank.
>>
>> Should not it be merged into linux first? Otherwise it will be
>> overwritten during the next dts sync with linux.
>>
>
> Considering that Linux maintainers have just rejected this
> implementation, yes we should wait on it being merged before
> supporting it in U-Boot :)
There are still some drivers are different with kernel, eg.
pinctrl&GPIO, and clock driver and etc, and kernel driver also changes.
Since the gpio bank support issue has been a period, I would like to
take one version driver at least can fix it and make U-Boot work with
new kernel dts
and new device. The U-Boot only use small set of the devices, so we want
to have a small enough but enough for U-Boot version driver.
So I have take this patch set, and we can improve later when kernel have
a version and we have a better solution for U-Boot.
Thanks,
- Kever
>
> Cheers,
> Quentin
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 1/9] gpio: gpio-rockchip: parse gpio-ranges for bank id
2023-02-23 8:59 ` Linus Walleij
@ 2023-03-02 2:54 ` Kever Yang
2023-03-02 13:59 ` Chris Morgan
0 siblings, 1 reply; 33+ messages in thread
From: Kever Yang @ 2023-03-02 2:54 UTC (permalink / raw)
To: Linus Walleij, Chris Morgan
Cc: u-boot, heiko, sjg, philipp.tomsich, chenjh, pgwipeout,
heiko.stuebner, Chris Morgan
Hi Linus,
On 2023/2/23 16:59, Linus Walleij wrote:
> On Mon, Feb 13, 2023 at 11:28 PM Chris Morgan <macroalpha82@gmail.com> wrote:
>
>> From: Chris Morgan <macromorgan@hotmail.com>
>>
>> Use the new devicetree property of gpio-ranges to determine the GPIO
>> bank ID. Preserve the "old" way of doing things too, so that boards
>> can be migrated and tested gradually (I only have a 3566 and 3326 to
>> test).
>>
>> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> gpio-ranges are not supposed to be used like this, because there is
> no semantic restrictions on how gpio-ranges are set up. For example:
>
> gpio-ranges = <&pfc 0 0 32>;
>
> that looks nice for this usecase, and I guess this is something
> like what you have but then look at this from arch/arm/boot/dts/hi3620.dtsi:
>
> gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
> &pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
> &pmx0 6 16 1 &pmx0 7 16 1>;
I can understand the gpio-ranges and pinctrl framework are flexible
enough for different hardware.
Rockchip SoC do not have this kind of GPIO/PINMUX hardware, one bank
GPIO is always
in one pinctrl/ioc for now, so this driver do work for rockchip platform
in U-Boot for now.
Thanks,
- Kever
>
> This is perfectly fine as well. Ranges can start anywhere in the hardware
> offsets and go anywhere, and be set up in smaller chunks however
> the author of the DTS file wants it.
>
> I am pretty sure the same discontiguous
> ranges can be encoded into the rk_gpio relevant DTS files as well,
> so this is not a good solution to your problem.
>
> What has been used in the past is just some unique hardware ID in the
> device tree, so I would just add that.
>
> Yours,
> Linus Walleij
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 1/9] gpio: gpio-rockchip: parse gpio-ranges for bank id
2023-03-02 2:54 ` Kever Yang
@ 2023-03-02 13:59 ` Chris Morgan
0 siblings, 0 replies; 33+ messages in thread
From: Chris Morgan @ 2023-03-02 13:59 UTC (permalink / raw)
To: Kever Yang
Cc: Linus Walleij, Chris Morgan, u-boot, heiko, sjg, philipp.tomsich,
chenjh, pgwipeout, heiko.stuebner
On Thu, Mar 02, 2023 at 10:54:57AM +0800, Kever Yang wrote:
> Hi Linus,
>
> On 2023/2/23 16:59, Linus Walleij wrote:
> > On Mon, Feb 13, 2023 at 11:28 PM Chris Morgan <macroalpha82@gmail.com> wrote:
> >
> > > From: Chris Morgan <macromorgan@hotmail.com>
> > >
> > > Use the new devicetree property of gpio-ranges to determine the GPIO
> > > bank ID. Preserve the "old" way of doing things too, so that boards
> > > can be migrated and tested gradually (I only have a 3566 and 3326 to
> > > test).
> > >
> > > Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> > gpio-ranges are not supposed to be used like this, because there is
> > no semantic restrictions on how gpio-ranges are set up. For example:
> >
> > gpio-ranges = <&pfc 0 0 32>;
> >
> > that looks nice for this usecase, and I guess this is something
> > like what you have but then look at this from arch/arm/boot/dts/hi3620.dtsi:
> >
> > gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
> > &pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
> > &pmx0 6 16 1 &pmx0 7 16 1>;
>
> I can understand the gpio-ranges and pinctrl framework are flexible enough
> for different hardware.
>
> Rockchip SoC do not have this kind of GPIO/PINMUX hardware, one bank GPIO is
> always
>
> in one pinctrl/ioc for now, so this driver do work for rockchip platform in
> U-Boot for now.
>
>
> Thanks,
>
> - Kever
I think I jumped the gun (sorry, just anxious to get my hardware supported)
and it looks like Linux is going in a different direction. I'm going to work
with this for now, but once Linux decides on a correct direction I'll update
the driver in U-Boot to match the Linux behavior.
Thank you.
>
> >
> > This is perfectly fine as well. Ranges can start anywhere in the hardware
> > offsets and go anywhere, and be set up in smaller chunks however
> > the author of the DTS file wants it.
> >
> > I am pretty sure the same discontiguous
> > ranges can be encoded into the rk_gpio relevant DTS files as well,
> > so this is not a good solution to your problem.
> >
> > What has been used in the past is just some unique hardware ID in the
> > device tree, so I would just add that.
> >
> > Yours,
> > Linus Walleij
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH V2 8/9] arm64: dts: rockchip: add gpio-ranges property to gpio nodes
2023-03-02 2:49 ` Kever Yang
@ 2023-03-07 19:14 ` Vasily Khoruzhick
0 siblings, 0 replies; 33+ messages in thread
From: Vasily Khoruzhick @ 2023-03-07 19:14 UTC (permalink / raw)
To: Kever Yang
Cc: Quentin Schulz, Chris Morgan, u-boot, heiko, sjg,
philipp.tomsich, chenjh, pgwipeout, heiko.stuebner, Chris Morgan
On Wed, Mar 1, 2023 at 6:49 PM Kever Yang <kever.yang@rock-chips.com> wrote:
Hi Kever,
> So I have take this patch set, and we can improve later when kernel have
> a version and we have a better solution for U-Boot.
My concern is that dts will be overwritten during the next dts sync
with the kernel. U-boot specific properties should be moved into an
appropriate -u-boot.dtsi file.
Regards,
Vasily
^ permalink raw reply [flat|nested] 33+ messages in thread
end of thread, other threads:[~2023-03-07 19:15 UTC | newest]
Thread overview: 33+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-02-13 22:27 [PATCH V2 0/9] Rockchip: Improve Support for RK3566 Devices Chris Morgan
2023-02-13 22:27 ` [PATCH V2 1/9] gpio: gpio-rockchip: parse gpio-ranges for bank id Chris Morgan
2023-02-22 7:44 ` Kever Yang
2023-02-22 10:59 ` Johan Jonker
2023-02-23 8:59 ` Linus Walleij
2023-03-02 2:54 ` Kever Yang
2023-03-02 13:59 ` Chris Morgan
2023-02-13 22:27 ` [PATCH V2 2/9] dts: rockchip: px30: add gpio-ranges property to gpio nodes Chris Morgan
2023-02-22 7:44 ` Kever Yang
2023-02-13 22:27 ` [PATCH V2 3/9] rockchip: vop2: Add vop2 dt-binding from Linux Chris Morgan
2023-02-13 22:27 ` [PATCH V2 4/9] arm64: dts: rockchip: Sync rk356x from Linux main Chris Morgan
2023-02-15 18:44 ` Jonas Karlman
2023-02-22 7:32 ` Kever Yang
2023-02-13 22:27 ` [PATCH V2 5/9] rockchip: rk3568: add boot device detection Chris Morgan
2023-02-15 18:28 ` Jonas Karlman
2023-02-22 7:45 ` Kever Yang
2023-02-13 22:27 ` [PATCH V2 6/9] rockchip: rk3568: enable automatic power savings Chris Morgan
2023-02-22 7:34 ` Kever Yang
2023-02-13 22:27 ` [PATCH V2 7/9] gpio/rockchip: rk_gpio support v2 gpio controller Chris Morgan
2023-02-16 11:19 ` FUKAUMI Naoki
2023-02-22 7:49 ` Kever Yang
2023-02-22 8:28 ` Kever Yang
2023-02-23 22:14 ` Vasily Khoruzhick
2023-03-01 8:25 ` Eugen Hristev
2023-03-01 15:02 ` Simon Glass
2023-02-13 22:27 ` [PATCH V2 8/9] arm64: dts: rockchip: add gpio-ranges property to gpio nodes Chris Morgan
2023-02-22 7:47 ` Kever Yang
2023-02-23 21:12 ` Vasily Khoruzhick
2023-02-28 11:26 ` Quentin Schulz
2023-03-02 2:49 ` Kever Yang
2023-03-07 19:14 ` Vasily Khoruzhick
2023-02-13 22:27 ` [PATCH V2 9/9] evb1-v10-rk3568: Update MAINTAINERS and documentation Chris Morgan
2023-02-22 7:48 ` Kever Yang
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