From: "Lim, Elly Siew Chin" <elly.siew.chin.lim@intel.com>
To: Ley Foon Tan <lftan.linux@gmail.com>
Cc: ZY - u-boot <u-boot@lists.denx.de>, Marek Vasut <marex@denx.de>,
"Simon Goldschmidt" <simon.k.r.goldschmidt@gmail.com>,
"Chee, Tien Fong" <tien.fong.chee@intel.com>,
"Westergreen, Dalon" <dalon.westergreen@intel.com>,
Simon Glass <sjg@chromium.org>,
"Gan, Yau Wai" <yau.wai.gan@intel.com>
Subject: RE: [v3 15/17] arm: dts: Add base dtsi and devkit dts for Intel N5X device
Date: Fri, 9 Jul 2021 01:10:28 +0000 [thread overview]
Message-ID: <CO1PR11MB5092C42328B3E86B75C8C90591189@CO1PR11MB5092.namprd11.prod.outlook.com> (raw)
In-Reply-To: <CAFiDJ5-7zQtZ-EOUb1o3GaBn+Nh5yPNda9pUpmVNt3qLrEy9vQ@mail.gmail.com>
> -----Original Message-----
> From: Ley Foon Tan <lftan.linux@gmail.com>
> Sent: Friday, July 9, 2021 12:33 AM
> To: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> Cc: ZY - u-boot <u-boot@lists.denx.de>; Marek Vasut <marex@denx.de>;
> Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>; Westergreen, Dalon
> <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Gan,
> Yau Wai <yau.wai.gan@intel.com>
> Subject: Re: [v3 15/17] arm: dts: Add base dtsi and devkit dts for Intel N5X
> device
>
> On Sun, Jun 13, 2021 at 4:49 PM Siew Chin Lim <elly.siew.chin.lim@intel.com>
> wrote:
> >
> > Add device tree for N5X.
> >
> > Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > ---
> > v3:
> > - Update comment for memory example code
> > - Move all common dts settings for N5X from
> > socfpga_n5x_socdk.dts to socfpga_n5x-u-boot.dtsi
> > - Remove unused parameter "u-boot,boot0"
> >
> > v2:
> > - Remove socfpga_n5x.dtsi
> > - Reuse socfpga_agilex.dtsi in socfpga_n5x_socdk.dts and update
> > n5x data accordingly.
> > ---
> > arch/arm/dts/Makefile | 1 +
> > arch/arm/dts/socfpga_n5x-u-boot.dtsi | 175 ++++++++++++++++++
> > arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 67 +++++++
> > ...agilex_socdk.dts => socfpga_n5x_socdk.dts} | 25 ++-
> > 4 files changed, 262 insertions(+), 6 deletions(-) create mode
> > 100644 arch/arm/dts/socfpga_n5x-u-boot.dtsi
> > create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
> > copy arch/arm/dts/{socfpga_agilex_socdk.dts => socfpga_n5x_socdk.dts}
> > (81%)
> >
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
> > 096068261d..8a513e2a87 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -393,6 +393,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
> \
> > socfpga_cyclone5_socrates.dtb \
> > socfpga_cyclone5_sr1500.dtb \
> > socfpga_cyclone5_vining_fpga.dtb \
> > + socfpga_n5x_socdk.dtb \
> > socfpga_stratix10_socdk.dtb
> >
> > dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
> diff
> > --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi
> > b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
> > new file mode 100644
> > index 0000000000..d144116e71
> > --- /dev/null
> > +++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
> > @@ -0,0 +1,175 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * U-Boot additions
> > + *
> > + * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> */
> > +
> > +#include "socfpga_soc64_fit-u-boot.dtsi"
> > +
> > +/{
> > + memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + u-boot,dm-pre-reloc;
> > + };
> > +
> > + soc {
> > + u-boot,dm-pre-reloc;
> > +
> > + ccu: cache-controller@f7000000 {
> > + compatible = "arteris,ncore-ccu";
> > + reg = <0xf7000000 0x100900>;
> > + u-boot,dm-pre-reloc;
> > + };
> > + };
> > +};
> > +
> > +&clkmgr {
> > + compatible = "intel,n5x-clkmgr";
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +
> > +&gmac1 {
> > + altr,sysmgr-syscon = <&sysmgr 0x48 0>;
> > + clocks = <&clkmgr N5X_EMAC1_CLK>; };
> > +
> > +&gmac2 {
> > + altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
> > + clocks = <&clkmgr N5X_EMAC2_CLK>; };
> > +
> > +&i2c0 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>;
> > + reset-names = "i2c";
> > +};
> > +
> > +&i2c1 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>;
> > + reset-names = "i2c";
> > +};
> > +
> > +&i2c2 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>;
> > + reset-names = "i2c";
> > +};
> > +
> > +&i2c3 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>;
> > + reset-names = "i2c";
> > +};
> > +
> > +&i2c4 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>;
> > + reset-names = "i2c";
> > +};
> > +
> > +&memclkmgr {
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +
> > +&mmc {
> > + clocks = <&clkmgr N5X_L4_MP_CLK>,
> > + <&clkmgr N5X_SDMMC_CLK>;
> > + resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; };
> > +
> > +&pdma {
> > + clocks = <&clkmgr N5X_L4_MAIN_CLK>; };
> > +
> > +&spi0 {
> > + clocks = <&clkmgr N5X_L4_MAIN_CLK>; };
> > +
> > +&spi1 {
> > + clocks = <&clkmgr N5X_L4_MAIN_CLK>; };
> > +
> > +&timer0 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>; };
> > +
> > +&timer1 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>; };
> > +
> > +&timer2 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>; };
> > +
> > +&timer3 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>; };
> > +
> > +&porta {
> > + bank-name = "porta";
> > +};
> > +
> > +&portb {
> > + bank-name = "portb";
> > +};
> > +
> > +&qspi {
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&rst {
> > + compatible = "altr,rst-mgr";
> > + altr,modrst-offset = <0x20>;
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&sdr {
> > + compatible = "intel,sdr-ctl-n5x";
> > + resets = <&rst DDRSCH_RESET>;
> > + clocks = <&memclkmgr>;
> > + clock-names = "mem_clk";
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&sysmgr {
> > + compatible = "altr,sys-mgr", "syscon";
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&uart0 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>;
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&uart1 {
> > + clocks = <&clkmgr N5X_L4_SP_CLK>; };
> > +
> > +&usb0 {
> > + clocks = <&clkmgr N5X_USB_CLK>;
> > + disable-over-current;
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&usb1 {
> > + clocks = <&clkmgr N5X_USB_CLK>;
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&watchdog0 {
> > + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>;
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&watchdog1 {
> > + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; };
> > +
> > +&watchdog2 {
> > + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; };
> > +
> > +&watchdog3 {
> > + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; };
> > +
> > diff --git a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
> > b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
> > new file mode 100644
> > index 0000000000..612d394019
> > --- /dev/null
> > +++ b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
> > @@ -0,0 +1,67 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * U-Boot additions
> > + *
> > + * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> */
> > +
> > +#include "socfpga_n5x-u-boot.dtsi"
> > +
> > +/{
> > + aliases {
> > + spi0 = &qspi;
> > + i2c0 = &i2c1;
> > + };
> > +
> > + memory {
> > + /*
> > + * Memory type: DDR4 (interleaving mode)
> > + * 16GB
> > + * <0 0x00000000 0 0x80000000>,
> > + * <4 0x80000000 3 0x80000000>;
> > + *
> > + * 8GB
> > + * <0 0x00000000 0 0x80000000>,
> > + * <2 0x80000000 1 0x80000000>;
> > + *
> > + * 4GB
> > + * <0 0x00000000 0 0x80000000>,
> > + * <1 0x80000000 0 0x80000000>;
> > + *
> > + * Memory type: LPDDR4 (non-interleaving mode)
> > + * Total memory size 3GB, usable = 2.5GB, 0.5GB trade off for
> secure
> > + * region.
> > + */
> > + reg = <0 0x00000000 0 0x60000000>,
> > + <0x10 0x00100000 0 0x40000000>;
> > + };
> > +};
> > +
> > +&flash0 {
> > + compatible = "jedec,spi-nor";
> > + spi-tx-bus-width = <4>;
> > + spi-rx-bus-width = <4>;
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&i2c1 {
> > + status = "okay";
> > +};
> > +
> > +&nand {
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&mmc {
> > + drvsel = <3>;
> > + smplsel = <0>;
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&qspi {
> > + status = "okay";
> > +};
> > +
> > +&watchdog0 {
> > + u-boot,dm-pre-reloc;
> > +};
> > diff --git a/arch/arm/dts/socfpga_agilex_socdk.dts
> > b/arch/arm/dts/socfpga_n5x_socdk.dts
> > similarity index 81%
> > copy from arch/arm/dts/socfpga_agilex_socdk.dts
> > copy to arch/arm/dts/socfpga_n5x_socdk.dts
> > index bcdeecc0e0..4cb71b5de3 100644
> > --- a/arch/arm/dts/socfpga_agilex_socdk.dts
> > +++ b/arch/arm/dts/socfpga_n5x_socdk.dts
> > @@ -1,11 +1,12 @@
> > // SPDX-License-Identifier: GPL-2.0
> > /*
> > - * Copyright (C) 2019, Intel Corporation
> > + * Copyright (C) 2020-2021, Intel Corporation
> > */
> > #include "socfpga_agilex.dtsi"
> > +#include <dt-bindings/clock/n5x-clock.h>
> >
> > / {
> > - model = "SoCFPGA Agilex SoCDK";
> > + model = "eASIC N5X SoCDK";
> >
> > aliases {
> > serial0 = &uart0;
> > @@ -47,6 +48,18 @@
> > osc1 {
> > clock-frequency = <25000000>;
> > };
> > +
> > + dram_eosc_clk: dram-eosc-clk {
> > + #clock-cells = <0>;
> > + compatible = "fixed-clock";
> > + };
> > + };
> > +
> > + memclkmgr: mem-clock-controller@f8040000 {
> > + compatible = "intel,n5x-mem-clkmgr";
> > + reg = <0xf8040000 0x1000>;
> > + #clock-cells = <0>;
> > + clocks = <&dram_eosc_clk>, <&f2s_free_clk>;
> > };
> > };
> > };
> > @@ -59,8 +72,8 @@
> > status = "okay";
> > phy-mode = "rgmii";
> > phy-handle = <&phy0>;
> > -
> > max-frame-size = <9000>;
> > + clocks = <&clkmgr N5X_EMAC0_CLK>;
> >
> > mdio0 {
> > #address-cells = <1>;
> > @@ -98,14 +111,14 @@
> >
> > &usb0 {
> > status = "okay";
> > - disable-over-current;
> > };
> >
> > -&watchdog0 {
> > +&usb1 {
> > status = "okay";
> > };
> >
> > &qspi {
> > + status = "okay";
> > flash0: flash@0 {
> > #address-cells = <1>;
> > #size-cells = <1>;
> > @@ -116,7 +129,7 @@
> > m25p,fast-read;
> > cdns,page-size = <256>;
> > cdns,block-size = <16>;
> > - cdns,read-delay = <1>;
> > + cdns,read-delay = <3>;
> > cdns,tshsl-ns = <50>;
> > cdns,tsd2d-ns = <50>;
> > cdns,tchsh-ns = <4>;
> > --
> > 2.19.0
> >
>
> socfpga_n5x_socdk.dts is not imported from
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/
> arm64/boot/dts/intel/socfpga_n5x_socdk.dts?
> Reuse socfpga_n5x_socdk.dts from Linux and add U-boot specifc dts to u-
> boot.dtsi.
>
> Regards
> Ley Foon
Noted.
Thanks,
Siew Chin
next prev parent reply other threads:[~2021-07-09 1:10 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-13 8:48 [v3 00/17] Add Intel N5X SoC support Siew Chin Lim
2021-06-13 8:48 ` [v3 01/17] arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux function Siew Chin Lim
2021-06-13 8:48 ` [v3 02/17] arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h Siew Chin Lim
2021-06-13 8:48 ` [v3 03/17] arm: socfpga: Add base address for Intel N5X device Siew Chin Lim
2021-06-13 8:48 ` [v3 04/17] arm: socfpga: Add handoff data support " Siew Chin Lim
2021-07-08 16:15 ` Ley Foon Tan
2021-06-13 8:48 ` [v3 05/17] drivers: clk: Add clock driver " Siew Chin Lim
2021-07-08 16:17 ` Ley Foon Tan
2021-06-13 8:48 ` [v3 06/17] arm: socfpga: Get clock manager base address " Siew Chin Lim
2021-06-13 8:48 ` [v3 07/17] drivers: clk: Add memory clock driver " Siew Chin Lim
2021-07-08 16:19 ` Ley Foon Tan
2021-06-13 8:48 ` [v3 08/17] arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.h Siew Chin Lim
2021-06-13 8:48 ` [v3 09/17] arm: socfpga: Add clock manager for Intel N5X device Siew Chin Lim
2021-06-13 8:48 ` [v3 10/17] arm: socfpga: Changed misc_s10.c to misc_soc64.c Siew Chin Lim
2021-06-13 8:48 ` [v3 11/17] ddr: socfpga: Enable memory test on memory size less than 1GB Siew Chin Lim
2021-06-13 8:48 ` [v3 12/17] ddr: altera: Add SDRAM driver for Intel N5X device Siew Chin Lim
2021-07-08 17:06 ` Ley Foon Tan
2021-06-13 8:48 ` [v3 13/17] arm: socfpga: Add SPL " Siew Chin Lim
2021-06-13 8:48 ` [v3 14/17] board: intel: Add socdk board support " Siew Chin Lim
2021-06-13 8:48 ` [v3 15/17] arm: dts: Add base dtsi and devkit dts " Siew Chin Lim
2021-07-08 16:32 ` Ley Foon Tan
2021-07-09 1:10 ` Lim, Elly Siew Chin [this message]
2021-06-13 8:48 ` [v3 16/17] include: configs: Add Intel N5X device CONFIGs Siew Chin Lim
2021-06-13 8:48 ` [v3 17/17] arm: socfpga: Enable Intel N5X device build Siew Chin Lim
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