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From: "Jan Beulich" <JBeulich@suse.com>
To: xen-devel <xen-devel@lists.xenproject.org>
Cc: George Dunlap <George.Dunlap@eu.citrix.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>,
	Wei Liu <wei.liu2@citrix.com>,
	Roger Pau Monne <roger.pau@citrix.com>
Subject: [PATCH v8 32/50] x86emul: support AVX512F gather insns
Date: Fri, 15 Mar 2019 04:58:47 -0600
Message-ID: <5C8B8567020000780021F24E@prv1-mh.provo.novell.com> (raw)
In-Reply-To: <5C8B7EC0020000780021F10B@prv1-mh.provo.novell.com>

This requires getting modrm_reg and sib_index set correctly in the EVEX
case, to account for the high 16 [XYZ]MM registers. Extend the
adjustments to modrm_rm as well, such that x86_insn_modrm() would
correctly report register numbers (this was a latent issue only as we
don't currently have callers of that function which would care about an
EVEX case). The adjustment in turn requires dropping the assertion from
decode_gpr() as well as re-introducing the explicit masking, as we now
need to actively mask off the high bit when a GPR is meant.
_decode_gpr() invocations also need slight adjustments, when invoked in
generic code ahead of the main switch(). All other uses of modrm_reg and
modrm_rm already get suitably masked where necessary.

There was also an encoding mistake in the EVEX Disp8 test code, which
was benign (due to %rdx getting set to zero) to all non-vSIB tests as it
mistakenly encoded <disp8>(%rdx,%rdx) instead of <disp8>(%rdx,%riz). In
the vSIB case this meant <disp8>(%rdx,%zmm2) instead of the intended
<disp8>(%rdx,%zmm4).

Likewise the access count check wasn't entirely correct for the S/G
case: In the quad-word-index but dword-data case only half the number
of full vector elements get accessed.

As an unrelated change in the main test harness source file distinguish
the "n/a" messages by bitness.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
v8: Re-base.
v7: Fix ByteOp register decode. Re-base.
v6: New.

--- a/tools/tests/x86_emulator/Makefile
+++ b/tools/tests/x86_emulator/Makefile
@@ -18,7 +18,7 @@ CFLAGS += $(CFLAGS_xeninclude)
 
 SIMD := 3dnow sse sse2 sse4 avx avx2 xop avx512f avx512bw avx512dq avx512er
 FMA := fma4 fma
-SG := avx2-sg
+SG := avx2-sg avx512f-sg avx512vl-sg
 TESTCASES := blowfish $(SIMD) $(FMA) $(SG)
 
 OPMASK := avx512f avx512dq avx512bw
@@ -66,6 +66,14 @@ xop-flts := $(avx-flts)
 avx512f-vecs := 64 16 32
 avx512f-ints := 4 8
 avx512f-flts := 4 8
+avx512f-sg-vecs := 64
+avx512f-sg-idxs := 4 8
+avx512f-sg-ints := $(avx512f-ints)
+avx512f-sg-flts := $(avx512f-flts)
+avx512vl-sg-vecs := 16 32
+avx512vl-sg-idxs := $(avx512f-sg-idxs)
+avx512vl-sg-ints := $(avx512f-ints)
+avx512vl-sg-flts := $(avx512f-flts)
 avx512bw-vecs := $(avx512f-vecs)
 avx512bw-ints := 1 2
 avx512bw-flts :=
--- a/tools/tests/x86_emulator/evex-disp8.c
+++ b/tools/tests/x86_emulator/evex-disp8.c
@@ -176,6 +176,8 @@ static const struct test avx512f_all[] =
     INSN(fnmsub213,    66, 0f38, af,    el,     sd, el),
     INSN(fnmsub231,    66, 0f38, be,    vl,     sd, vl),
     INSN(fnmsub231,    66, 0f38, bf,    el,     sd, el),
+    INSN(gatherd,      66, 0f38, 92,    vl,     sd, el),
+    INSN(gatherq,      66, 0f38, 93,    vl,     sd, el),
     INSN(getexp,       66, 0f38, 42,    vl,     sd, vl),
     INSN(getexp,       66, 0f38, 43,    el,     sd, el),
     INSN(getmant,      66, 0f3a, 26,    vl,     sd, vl),
@@ -229,6 +231,8 @@ static const struct test avx512f_all[] =
     INSN(permt2,       66, 0f38, 7e,    vl,     dq, vl),
     INSN(permt2,       66, 0f38, 7f,    vl,     sd, vl),
     INSN(pexpand,      66, 0f38, 89,    vl,     dq, el),
+    INSN(pgatherd,     66, 0f38, 90,    vl,     dq, el),
+    INSN(pgatherq,     66, 0f38, 91,    vl,     dq, el),
     INSN(pmaxs,        66, 0f38, 3d,    vl,     dq, vl),
     INSN(pmaxu,        66, 0f38, 3f,    vl,     dq, vl),
     INSN(pmins,        66, 0f38, 39,    vl,     dq, vl),
@@ -698,7 +702,7 @@ static void test_one(const struct test *
     instr[3] = evex.raw[2];
     instr[4] = test->opc;
     instr[5] = 0x44 | (test->ext << 3); /* ModR/M */
-    instr[6] = 0x12; /* SIB: base rDX, index none / xMM4 */
+    instr[6] = 0x22; /* SIB: base rDX, index none / xMM4 */
     instr[7] = 1; /* Disp8 */
     instr[8] = 0; /* immediate, if any */
 
@@ -718,7 +722,8 @@ static void test_one(const struct test *
          if ( accessed[i] )
              goto fail;
     for ( ; i < (test->scale == SC_vl ? vsz : esz) + (sg ? esz : vsz); ++i )
-         if ( accessed[i] != (sg ? vsz / esz : 1) )
+         if ( accessed[i] != (sg ? (vsz / esz) >> (test->opc & 1 & !evex.w)
+                                 : 1) )
              goto fail;
     for ( ; i < ARRAY_SIZE(accessed); ++i )
          if ( accessed[i] )
--- a/tools/tests/x86_emulator/simd-sg.c
+++ b/tools/tests/x86_emulator/simd-sg.c
@@ -35,13 +35,78 @@ typedef long long __attribute__((vector_
 #define ITEM_COUNT (VEC_SIZE / ELEM_SIZE < IVEC_SIZE / IDX_SIZE ? \
                     VEC_SIZE / ELEM_SIZE : IVEC_SIZE / IDX_SIZE)
 
-#if VEC_SIZE == 16
-# define to_bool(cmp) __builtin_ia32_ptestc128(cmp, (vec_t){} == 0)
-#else
-# define to_bool(cmp) __builtin_ia32_ptestc256(cmp, (vec_t){} == 0)
-#endif
+#if defined(__AVX512F__)
+# define ALL_TRUE (~0ULL >> (64 - ELEM_COUNT))
+# if ELEM_SIZE == 4
+#  if IDX_SIZE == 4 || defined(__AVX512VL__)
+#   define to_mask(msk) B(ptestmd, , (vsi_t)(msk), (vsi_t)(msk), ~0)
+#   define eq(x, y) (B(pcmpeqd, _mask, (vsi_t)(x), (vsi_t)(y), -1) == ALL_TRUE)
+#  else
+#   define widen(x) __builtin_ia32_pmovzxdq512_mask((vsi_t)(x), (idi_t){}, ~0)
+#   define to_mask(msk) __builtin_ia32_ptestmq512(widen(msk), widen(msk), ~0)
+#   define eq(x, y) (__builtin_ia32_pcmpeqq512_mask(widen(x), widen(y), ~0) == ALL_TRUE)
+#  endif
+#  define BG_(dt, it, reg, mem, idx, msk, scl) \
+    __builtin_ia32_gather##it##dt(reg, mem, idx, to_mask(msk), scl)
+# else
+#  define eq(x, y) (B(pcmpeqq, _mask, (vdi_t)(x), (vdi_t)(y), -1) == ALL_TRUE)
+#  define BG_(dt, it, reg, mem, idx, msk, scl) \
+    __builtin_ia32_gather##it##dt(reg, mem, idx, B(ptestmq, , (vdi_t)(msk), (vdi_t)(msk), ~0), scl)
+# endif
+/*
+ * Instead of replicating the main IDX_SIZE conditional below three times, use
+ * a double layer of macro invocations, allowing for substitution of the
+ * respective relevant macro argument tokens.
+ */
+# define BG(dt, it, reg, mem, idx, msk, scl) BG_(dt, it, reg, mem, idx, msk, scl)
+# if VEC_MAX < 64
+/*
+ * The sub-512-bit built-ins have an extra "3" infix, presumably because the
+ * 512-bit names were chosen without the AVX512VL extension in mind (and hence
+ * making the latter collide with the AVX2 ones).
+ */
+#  define si 3si
+#  define di 3di
+# endif
+# if VEC_MAX == 16
+#  define v8df v2df
+#  define v8di v2di
+#  define v16sf v4sf
+#  define v16si v4si
+# elif VEC_MAX == 32
+#  define v8df v4df
+#  define v8di v4di
+#  define v16sf v8sf
+#  define v16si v8si
+# endif
+# if IDX_SIZE == 4
+#  if INT_SIZE == 4
+#   define gather(reg, mem, idx, msk, scl) BG(v16si, si, reg, mem, idx, msk, scl)
+#  elif INT_SIZE == 8
+#   define gather(reg, mem, idx, msk, scl) (vec_t)(BG(v8di, si, (vdi_t)(reg), mem, idx, msk, scl))
+#  elif FLOAT_SIZE == 4
+#   define gather(reg, mem, idx, msk, scl) BG(v16sf, si, reg, mem, idx, msk, scl)
+#  elif FLOAT_SIZE == 8
+#   define gather(reg, mem, idx, msk, scl) BG(v8df, si, reg, mem, idx, msk, scl)
+#  endif
+# elif IDX_SIZE == 8
+#  if INT_SIZE == 4
+#   define gather(reg, mem, idx, msk, scl) BG(v16si, di, reg, mem, (idi_t)(idx), msk, scl)
+#  elif INT_SIZE == 8
+#   define gather(reg, mem, idx, msk, scl) (vec_t)(BG(v8di, di, (vdi_t)(reg), mem, (idi_t)(idx), msk, scl))
+#  elif FLOAT_SIZE == 4
+#   define gather(reg, mem, idx, msk, scl) BG(v16sf, di, reg, mem, (idi_t)(idx), msk, scl)
+#  elif FLOAT_SIZE == 8
+#   define gather(reg, mem, idx, msk, scl) BG(v8df, di, reg, mem, (idi_t)(idx), msk, scl)
+#  endif
+# endif
+#elif defined(__AVX2__)
+# if VEC_SIZE == 16
+#  define to_bool(cmp) __builtin_ia32_ptestc128(cmp, (vec_t){} == 0)
+# else
+#  define to_bool(cmp) __builtin_ia32_ptestc256(cmp, (vec_t){} == 0)
+# endif
 
-#if defined(__AVX2__)
 # if VEC_MAX == 16
 #  if IDX_SIZE == 4
 #   if INT_SIZE == 4
@@ -111,6 +176,10 @@ typedef long long __attribute__((vector_
 # endif
 #endif
 
+#ifndef eq
+# define eq(x, y) to_bool((x) == (y))
+#endif
+
 #define GLUE_(x, y) x ## y
 #define GLUE(x, y) GLUE_(x, y)
 
@@ -119,6 +188,7 @@ typedef long long __attribute__((vector_
 #define PUT8(n)  PUT4(n),   PUT4((n) +  4)
 #define PUT16(n) PUT8(n),   PUT8((n) +  8)
 #define PUT32(n) PUT16(n), PUT16((n) + 16)
+#define PUT64(n) PUT32(n), PUT32((n) + 32)
 
 const typeof((vec_t){}[0]) array[] = {
     GLUE(PUT, VEC_MAX)(1),
@@ -174,7 +244,7 @@ int sg_test(void)
 
     y = gather(full, array + ITEM_COUNT, -idx, full, ELEM_SIZE);
 #if ITEM_COUNT == ELEM_COUNT
-    if ( !to_bool(y == x - 1) )
+    if ( !eq(y, x - 1) )
         return __LINE__;
 #else
     for ( i = 0; i < ITEM_COUNT; ++i )
--- a/tools/tests/x86_emulator/test_x86_emulator.c
+++ b/tools/tests/x86_emulator/test_x86_emulator.c
@@ -22,6 +22,8 @@ asm ( ".pushsection .test, \"ax\", @prog
 #include "avx512dq-opmask.h"
 #include "avx512bw-opmask.h"
 #include "avx512f.h"
+#include "avx512f-sg.h"
+#include "avx512vl-sg.h"
 #include "avx512bw.h"
 #include "avx512dq.h"
 #include "avx512er.h"
@@ -90,11 +92,13 @@ static bool simd_check_avx512f(void)
     return cpu_has_avx512f;
 }
 #define simd_check_avx512f_opmask simd_check_avx512f
+#define simd_check_avx512f_sg simd_check_avx512f
 
 static bool simd_check_avx512f_vl(void)
 {
     return cpu_has_avx512f && cpu_has_avx512vl;
 }
+#define simd_check_avx512vl_sg simd_check_avx512f_vl
 
 static bool simd_check_avx512dq(void)
 {
@@ -291,6 +295,14 @@ static const struct {
     SIMD(AVX512F u32x16,      avx512f,      64u4),
     SIMD(AVX512F s64x8,       avx512f,      64i8),
     SIMD(AVX512F u64x8,       avx512f,      64u8),
+    SIMD(AVX512F S/G f32[16x32], avx512f_sg, 64x4f4),
+    SIMD(AVX512F S/G f64[ 8x32], avx512f_sg, 64x4f8),
+    SIMD(AVX512F S/G f32[ 8x64], avx512f_sg, 64x8f4),
+    SIMD(AVX512F S/G f64[ 8x64], avx512f_sg, 64x8f8),
+    SIMD(AVX512F S/G i32[16x32], avx512f_sg, 64x4i4),
+    SIMD(AVX512F S/G i64[ 8x32], avx512f_sg, 64x4i8),
+    SIMD(AVX512F S/G i32[ 8x64], avx512f_sg, 64x8i4),
+    SIMD(AVX512F S/G i64[ 8x64], avx512f_sg, 64x8i8),
     AVX512VL(VL f32x4,        avx512f,      16f4),
     AVX512VL(VL f64x2,        avx512f,      16f8),
     AVX512VL(VL f32x8,        avx512f,      32f4),
@@ -303,6 +315,22 @@ static const struct {
     AVX512VL(VL u64x2,        avx512f,      16u8),
     AVX512VL(VL s64x4,        avx512f,      32i8),
     AVX512VL(VL u64x4,        avx512f,      32u8),
+    SIMD(AVX512VL S/G f32[4x32], avx512vl_sg, 16x4f4),
+    SIMD(AVX512VL S/G f64[2x32], avx512vl_sg, 16x4f8),
+    SIMD(AVX512VL S/G f32[2x64], avx512vl_sg, 16x8f4),
+    SIMD(AVX512VL S/G f64[2x64], avx512vl_sg, 16x8f8),
+    SIMD(AVX512VL S/G f32[8x32], avx512vl_sg, 32x4f4),
+    SIMD(AVX512VL S/G f64[4x32], avx512vl_sg, 32x4f8),
+    SIMD(AVX512VL S/G f32[4x64], avx512vl_sg, 32x8f4),
+    SIMD(AVX512VL S/G f64[4x64], avx512vl_sg, 32x8f8),
+    SIMD(AVX512VL S/G i32[4x32], avx512vl_sg, 16x4i4),
+    SIMD(AVX512VL S/G i64[2x32], avx512vl_sg, 16x4i8),
+    SIMD(AVX512VL S/G i32[2x64], avx512vl_sg, 16x8i4),
+    SIMD(AVX512VL S/G i64[2x64], avx512vl_sg, 16x8i8),
+    SIMD(AVX512VL S/G i32[8x32], avx512vl_sg, 32x4i4),
+    SIMD(AVX512VL S/G i64[4x32], avx512vl_sg, 32x4i8),
+    SIMD(AVX512VL S/G i32[4x64], avx512vl_sg, 32x8i4),
+    SIMD(AVX512VL S/G i64[4x64], avx512vl_sg, 32x8i8),
     SIMD(AVX512BW s8x64,     avx512bw,      64i1),
     SIMD(AVX512BW u8x64,     avx512bw,      64u1),
     SIMD(AVX512BW s16x32,    avx512bw,      64i2),
@@ -4260,7 +4288,7 @@ int main(int argc, char **argv)
 
         if ( !blobs[j].size )
         {
-            printf("%-39s n/a\n", blobs[j].name);
+            printf("%-39s n/a (%u-bit)\n", blobs[j].name, blobs[j].bitness);
             continue;
         }
 
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -499,7 +499,7 @@ static const struct ext0f38_table {
     [0x8c] = { .simd_size = simd_packed_int },
     [0x8d] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
     [0x8e] = { .simd_size = simd_packed_int, .to_mem = 1 },
-    [0x90 ... 0x93] = { .simd_size = simd_other, .vsib = 1 },
+    [0x90 ... 0x93] = { .simd_size = simd_other, .vsib = 1, .d8s = d8s_dq },
     [0x96 ... 0x98] = { .simd_size = simd_packed_fp, .d8s = d8s_vl },
     [0x99] = { .simd_size = simd_scalar_vexw, .d8s = d8s_dq },
     [0x9a] = { .simd_size = simd_packed_fp, .d8s = d8s_vl },
@@ -3054,7 +3054,8 @@ x86_decode(
 
         d &= ~ModRM;
 #undef ModRM /* Only its aliases are valid to use from here on. */
-        modrm_reg = ((rex_prefix & 4) << 1) | ((modrm & 0x38) >> 3);
+        modrm_reg = ((rex_prefix & 4) << 1) | ((modrm & 0x38) >> 3) |
+                    ((evex_encoded() && !evex.R) << 4);
         modrm_rm  = modrm & 0x07;
 
         /*
@@ -3224,7 +3225,8 @@ x86_decode(
         if ( modrm_mod == 3 )
         {
             generate_exception_if(d & vSIB, EXC_UD);
-            modrm_rm |= (rex_prefix & 1) << 3;
+            modrm_rm |= ((rex_prefix & 1) << 3) |
+                        (evex_encoded() && !evex.x) << 4;
             ea.type = OP_REG;
         }
         else if ( ad_bytes == 2 )
@@ -3289,7 +3291,10 @@ x86_decode(
 
                 state->sib_index = ((sib >> 3) & 7) | ((rex_prefix << 2) & 8);
                 state->sib_scale = (sib >> 6) & 3;
-                if ( state->sib_index != 4 && !(d & vSIB) )
+                if ( unlikely(d & vSIB) )
+                    state->sib_index |= (mode_64bit() && evex_encoded() &&
+                                         !evex.RX) << 4;
+                else if ( state->sib_index != 4 )
                 {
                     ea.mem.off = *decode_gpr(state->regs, state->sib_index);
                     ea.mem.off <<= state->sib_scale;
@@ -3592,7 +3597,7 @@ x86_emulate(
     generate_exception_if(state->not_64bit && mode_64bit(), EXC_UD);
 
     if ( ea.type == OP_REG )
-        ea.reg = _decode_gpr(&_regs, modrm_rm, (d & ByteOp) && !rex_prefix);
+        ea.reg = _decode_gpr(&_regs, modrm_rm, (d & ByteOp) && !rex_prefix && !vex.opcx);
 
     memset(mmvalp, 0xaa /* arbitrary */, sizeof(*mmvalp));
 
@@ -3606,7 +3611,7 @@ x86_emulate(
         src.type = OP_REG;
         if ( d & ByteOp )
         {
-            src.reg = _decode_gpr(&_regs, modrm_reg, !rex_prefix);
+            src.reg = _decode_gpr(&_regs, modrm_reg, !rex_prefix && !vex.opcx);
             src.val = *(uint8_t *)src.reg;
             src.bytes = 1;
         }
@@ -3704,7 +3709,7 @@ x86_emulate(
         dst.type = OP_REG;
         if ( d & ByteOp )
         {
-            dst.reg = _decode_gpr(&_regs, modrm_reg, !rex_prefix);
+            dst.reg = _decode_gpr(&_regs, modrm_reg, !rex_prefix && !vex.opcx);
             dst.val = *(uint8_t *)dst.reg;
             dst.bytes = 1;
         }
@@ -9119,6 +9124,130 @@ x86_emulate(
         put_stub(stub);
 
         state->simd_size = simd_none;
+        break;
+    }
+
+    case X86EMUL_OPC_EVEX_66(0x0f38, 0x90): /* vpgatherd{d,q} mem,[xyz]mm{k} */
+    case X86EMUL_OPC_EVEX_66(0x0f38, 0x91): /* vpgatherq{d,q} mem,[xyz]mm{k} */
+    case X86EMUL_OPC_EVEX_66(0x0f38, 0x92): /* vgatherdp{s,d} mem,[xyz]mm{k} */
+    case X86EMUL_OPC_EVEX_66(0x0f38, 0x93): /* vgatherqp{s,d} mem,[xyz]mm{k} */
+    {
+        typeof(evex) *pevex;
+        union {
+            int32_t dw[16];
+            int64_t qw[8];
+        } index;
+        bool done = false;
+
+        ASSERT(ea.type == OP_MEM);
+        generate_exception_if((!evex.opmsk || evex.brs || evex.z ||
+                               evex.reg != 0xf ||
+                               modrm_reg == state->sib_index),
+                              EXC_UD);
+        avx512_vlen_check(false);
+        host_and_vcpu_must_have(avx512f);
+        get_fpu(X86EMUL_FPU_zmm);
+
+        /* Read destination and index registers. */
+        opc = init_evex(stub);
+        pevex = copy_EVEX(opc, evex);
+        pevex->opcx = vex_0f;
+        opc[0] = 0x7f; /* vmovdqa{32,64} */
+        /*
+         * The register writeback below has to retain masked-off elements, but
+         * needs to clear upper portions in the index-wider-than-data cases.
+         * Therefore read (and write below) the full register. The alternative
+         * would have been to fiddle with the mask register used.
+         */
+        pevex->opmsk = 0;
+        /* Use (%rax) as destination and modrm_reg as source. */
+        pevex->b = 1;
+        opc[1] = (modrm_reg & 7) << 3;
+        pevex->RX = 1;
+        opc[2] = 0xc3;
+
+        invoke_stub("", "", "=m" (*mmvalp) : "a" (mmvalp));
+
+        pevex->pfx = vex_f3; /* vmovdqu{32,64} */
+        pevex->w = b & 1;
+        /* Switch to sib_index as source. */
+        pevex->r = !mode_64bit() || !(state->sib_index & 0x08);
+        pevex->R = !mode_64bit() || !(state->sib_index & 0x10);
+        opc[1] = (state->sib_index & 7) << 3;
+
+        invoke_stub("", "", "=m" (index) : "a" (&index));
+        put_stub(stub);
+
+        /* Clear untouched parts of the destination and mask values. */
+        n = 1 << (2 + evex.lr - ((b & 1) | evex.w));
+        op_bytes = 4 << evex.w;
+        memset((void *)mmvalp + n * op_bytes, 0, 64 - n * op_bytes);
+        op_mask &= (1 << n) - 1;
+
+        for ( i = 0; op_mask; ++i )
+        {
+            signed long idx = b & 1 ? index.qw[i] : index.dw[i];
+
+            if ( !(op_mask & (1 << i)) )
+                continue;
+
+            rc = ops->read(ea.mem.seg,
+                           truncate_ea(ea.mem.off + (idx << state->sib_scale)),
+                           (void *)mmvalp + i * op_bytes, op_bytes, ctxt);
+            if ( rc != X86EMUL_OKAY )
+            {
+                /*
+                 * If we've made some progress and the access did not fault,
+                 * force a retry instead. This is for example necessary to
+                 * cope with the limited capacity of HVM's MMIO cache.
+                 */
+                if ( rc != X86EMUL_EXCEPTION && done )
+                    rc = X86EMUL_RETRY;
+                break;
+            }
+
+            op_mask &= ~(1 << i);
+            done = true;
+
+#ifdef __XEN__
+            if ( op_mask && local_events_need_delivery() )
+            {
+                rc = X86EMUL_RETRY;
+                break;
+            }
+#endif
+        }
+
+        /* Write destination and mask registers. */
+        opc = init_evex(stub);
+        pevex = copy_EVEX(opc, evex);
+        pevex->opcx = vex_0f;
+        opc[0] = 0x6f; /* vmovdqa{32,64} */
+        pevex->opmsk = 0;
+        /* Use modrm_reg as destination and (%rax) as source. */
+        pevex->b = 1;
+        opc[1] = (modrm_reg & 7) << 3;
+        pevex->RX = 1;
+        opc[2] = 0xc3;
+
+        invoke_stub("", "", "+m" (*mmvalp) : "a" (mmvalp));
+
+        /*
+         * kmovw: This is VEX-encoded, so we can't use pevex. Avoid copy_VEX() etc
+         * as well, since we can easily use the 2-byte VEX form here.
+         */
+        opc -= EVEX_PFX_BYTES;
+        opc[0] = 0xc5;
+        opc[1] = 0xf8;
+        opc[2] = 0x90;
+        /* Use (%rax) as source. */
+        opc[3] = evex.opmsk << 3;
+        opc[4] = 0xc3;
+
+        invoke_stub("", "", "+m" (op_mask) : "a" (&op_mask));
+        put_stub(stub);
+
+        state->simd_size = simd_none;
         break;
     }
 
--- a/xen/arch/x86/x86_emulate/x86_emulate.h
+++ b/xen/arch/x86/x86_emulate/x86_emulate.h
@@ -662,8 +662,6 @@ static inline unsigned long *decode_gpr(
     BUILD_BUG_ON(ARRAY_SIZE(cpu_user_regs_gpr_offsets) &
                  (ARRAY_SIZE(cpu_user_regs_gpr_offsets) - 1));
 
-    ASSERT(modrm < ARRAY_SIZE(cpu_user_regs_gpr_offsets));
-
     /* Note that this also acts as array_access_nospec() stand-in. */
     modrm &= ARRAY_SIZE(cpu_user_regs_gpr_offsets) - 1;
 




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  parent reply index

Thread overview: 465+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-09  8:15 [PATCH 0/6] x86emul: fixes, improvements, and beginnings of AVX512 support Jan Beulich
2018-08-09  8:23 ` [PATCH 1/6] x86emul: fix FMA scalar operand sizes Jan Beulich
2018-08-09  8:24 ` [PATCH 2/6] x86emul: extend MASKMOV{Q,DQU} tests Jan Beulich
2018-08-09  8:24 ` [PATCH 3/6] x86emul: support AVX512 opmask insns Jan Beulich
2018-08-09  8:25 ` [PATCH 4/6] x86emul: clean up AVX2 insn use in test harness Jan Beulich
2018-08-09  8:25 ` [PATCH 5/6] x86emul: correct EVEX decoding Jan Beulich
2018-08-09  8:26 ` [PATCH 6/6] x86emul: generalize vector length handling for AVX512/EVEX Jan Beulich
2018-08-29 14:20 ` [PATCH v2 0/6] x86emul: fixes, improvements, and beginnings of AVX512 support Jan Beulich
2018-08-29 14:23   ` [PATCH v2 1/6] x86emul: fix FMA scalar operand sizes Jan Beulich
2018-09-03 16:43     ` Andrew Cooper
2018-09-04  7:52       ` Jan Beulich
2018-08-29 14:23   ` [PATCH v2 2/6] x86emul: extend MASKMOV{Q,DQU} tests Jan Beulich
2018-09-03 16:44     ` [PATCH v2 2/6] x86emul: extend MASKMOV{Q, DQU} tests Andrew Cooper
2018-08-29 14:24   ` [PATCH v2 3/6] x86emul: support AVX512 opmask insns Jan Beulich
2018-09-03 17:57     ` Andrew Cooper
2018-09-04  7:58       ` Jan Beulich
2018-08-29 14:24   ` [PATCH v2 4/6] x86emul: clean up AVX2 insn use in test harness Jan Beulich
2018-09-03 18:04     ` Andrew Cooper
2018-08-29 14:25   ` [PATCH v2 5/6] x86emul: correct EVEX decoding Jan Beulich
2018-09-04 10:48     ` Andrew Cooper
2018-09-04 12:48       ` Jan Beulich
2018-08-29 14:25   ` [PATCH v2 6/6] x86emul: generalize vector length handling for AVX512/EVEX Jan Beulich
2018-09-04 11:02     ` Andrew Cooper
2018-09-04 12:50       ` Jan Beulich
2018-09-18 11:46 ` [PATCH v3 00/34] x86emul: fixes, improvements, and beginnings of AVX512 support Jan Beulich
2018-09-18 11:53   ` [PATCH v3 01/34] x86emul: support AVX512 opmask insns Jan Beulich
2018-10-25 18:32     ` Andrew Cooper
2018-10-26  9:03       ` Jan Beulich
2018-10-26 11:29         ` Andrew Cooper
2018-10-26 11:59           ` Jan Beulich
2018-10-26 12:19             ` Andrew Cooper
2018-10-26 12:34               ` Jan Beulich
2018-09-18 11:53   ` [PATCH v3 02/34] x86/HVM: grow MMIO cache data size to 64 bytes Jan Beulich
2018-09-18 16:05     ` Paul Durrant
2018-10-25 18:36     ` Andrew Cooper
2018-10-26  9:04       ` Jan Beulich
2018-10-26 11:29         ` Andrew Cooper
2018-09-18 11:55   ` [PATCH v3 03/34] x86emul: correct EVEX decoding Jan Beulich
2018-09-18 11:55   ` [PATCH v3 04/34] x86emul: generalize vector length handling for AVX512/EVEX Jan Beulich
2018-09-18 11:56   ` [PATCH v3 05/34] x86emul: support basic AVX512 moves Jan Beulich
2018-09-18 11:57   ` [PATCH v3 06/34] x86emul: test for correct EVEX Disp8 scaling Jan Beulich
2018-09-18 11:57   ` [PATCH v3 07/34] x86emul: use AVX512 logic for emulating V{, P}MASKMOV* Jan Beulich
2018-09-18 11:58   ` [PATCH v3 08/34] x86emul: support AVX512F legacy-equivalent arithmetic FP insns Jan Beulich
2018-09-18 11:59   ` [PATCH v3 09/34] x86emul: support AVX512DQ logic " Jan Beulich
2018-09-18 11:59   ` [PATCH v3 10/34] x86emul: support AVX512F "normal" FP compare insns Jan Beulich
2018-09-18 12:00   ` [PATCH v3 11/34] x86emul: support AVX512F misc legacy-equivalent FP insns Jan Beulich
2018-09-18 12:00   ` [PATCH v3 12/34] x86emul: support AVX512F fused-multiply-add insns Jan Beulich
2018-09-18 12:01   ` [PATCH v3 13/34] x86emul: support AVX512F legacy-equivalent logic insns Jan Beulich
2018-09-18 12:02   ` [PATCH v3 14/34] x86emul: support AVX512{F, DQ} FP broadcast insns Jan Beulich
2018-09-18 12:03   ` [PATCH v3 15/34] x86emul: support AVX512F v{, u}comis{d, s} insns Jan Beulich
2018-09-18 12:03   ` [PATCH v3 16/34] x86emul/test: introduce eq() Jan Beulich
2018-09-18 12:04   ` [PATCH v3 17/34] x86emul: support AVX512{F, BW} packed integer compare insns Jan Beulich
2018-09-18 12:05   ` [PATCH v3 18/34] x86emul: support AVX512{F, BW} packed integer arithmetic insns Jan Beulich
2018-09-18 12:05   ` [PATCH v3 19/34] x86emul: use simd_128 also for legacy vector shift insns Jan Beulich
2018-09-18 12:05   ` [PATCH v3 20/34] x86emul: support AVX512{F, BW} shift/rotate insns Jan Beulich
2018-09-18 12:06   ` [PATCH v3 21/34] x86emul: support AVX512{F, BW, DQ} extract insns Jan Beulich
2018-09-18 12:07   ` [PATCH v3 22/34] x86emul: support AVX512{F, BW, DQ} insert insns Jan Beulich
2018-09-18 12:07   ` [PATCH v3 23/34] x86emul: basic AVX512F testing Jan Beulich
2018-09-18 12:08   ` [PATCH v3 24/34] x86emul: support AVX512{F, BW, DQ} integer broadcast insns Jan Beulich
2018-09-18 12:09   ` [PATCH v3 25/34] x86emul: basic AVX512VL testing Jan Beulich
2018-09-18 12:09   ` [PATCH v3 26/34] x86emul: support AVX512{F, BW} zero- and sign-extending moves Jan Beulich
2018-09-18 12:09   ` [PATCH v3 27/34] x86emul: support AVX512{F, BW} down conversion moves Jan Beulich
2018-09-18 12:10   ` [PATCH v3 28/34] x86emul: support AVX512{F, BW} integer unpack insns Jan Beulich
2018-09-18 12:11   ` [PATCH v3 29/34] x86emul: support AVX512{F, BW, _VBMI} full permute insns Jan Beulich
2018-09-18 12:11   ` [PATCH v3 29/34] x86emul: support AVX512{F, BW} integer shuffle insns Jan Beulich
2018-09-18 12:12   ` [PATCH v3 30/34] x86emul: support AVX512{BW, DQ} mask move insns Jan Beulich
2018-09-18 12:14   ` [PATCH v3 32/34] x86emul: basic AVX512BW testing Jan Beulich
2018-09-18 12:14   ` [PATCH v3 33/34] x86emul: basic AVX512DQ testing Jan Beulich
2018-09-18 12:14   ` [PATCH v3 34/34] x86emul: also allow running the 32-bit harness on a 64-bit distro Jan Beulich
2018-09-25 13:14 ` [PATCH v4 00/44] x86emul: fixes, improvements, and beginnings of AVX512 support Jan Beulich
2018-09-25 13:25   ` [PATCH v4 01/44] x86emul: support AVX512 opmask insns Jan Beulich
2018-09-26  6:06     ` Jan Beulich
2018-09-25 13:26   ` [PATCH v4 02/44] x86/HVM: grow MMIO cache data size to 64 bytes Jan Beulich
2018-09-25 13:27   ` [PATCH v4 03/44] x86emul: correct EVEX decoding Jan Beulich
2018-10-26 14:33     ` Andrew Cooper
2018-09-25 13:28   ` [PATCH v4 04/44] x86emul: generalize vector length handling for AVX512/EVEX Jan Beulich
2018-10-26 16:10     ` Andrew Cooper
2018-09-25 13:28   ` [PATCH v4 05/44] x86emul: support basic AVX512 moves Jan Beulich
2018-11-13 17:12     ` Andrew Cooper
2018-11-14 14:35       ` Jan Beulich
2018-11-14 16:26         ` Andrew Cooper
2018-11-15  9:54           ` Jan Beulich
2018-09-25 13:29   ` [PATCH v4 06/44] x86emul: test for correct EVEX Disp8 scaling Jan Beulich
2018-11-12 17:42     ` Andrew Cooper
2018-11-13 11:12       ` Jan Beulich
2018-11-13 15:45         ` Andrew Cooper
2018-11-14 14:17           ` Jan Beulich
2018-11-14 14:42             ` Andrew Cooper
2018-11-14 14:58               ` Jan Beulich
2018-09-25 13:29   ` [PATCH v4 07/44] x86emul: also allow running the 32-bit harness on a 64-bit distro Jan Beulich
2018-11-12 17:50     ` Andrew Cooper
2018-11-13 11:42       ` Jan Beulich
2018-11-13 15:58         ` Andrew Cooper
2018-11-14  8:42           ` Jan Beulich
2018-09-25 13:30   ` [PATCH v4 08/44] x86emul: use AVX512 logic for emulating V{, P}MASKMOV* Jan Beulich
2018-11-13 18:12     ` Andrew Cooper
2018-09-25 13:31   ` [PATCH v4 09/44] x86emul: support AVX512F legacy-equivalent arithmetic FP insns Jan Beulich
2018-11-13 18:21     ` Andrew Cooper
2018-09-25 13:32   ` [PATCH v4 10/44] x86emul: support AVX512DQ logic " Jan Beulich
2018-11-13 18:56     ` Andrew Cooper
2018-09-25 13:32   ` [PATCH v4 11/44] x86emul: support AVX512F "normal" FP compare insns Jan Beulich
2018-11-13 19:04     ` Andrew Cooper
2018-11-14 14:41       ` Jan Beulich
2018-11-14 14:45         ` Andrew Cooper
2018-09-25 13:33   ` [PATCH v4 12/44] x86emul: support AVX512F misc legacy-equivalent FP insns Jan Beulich
2018-11-13 19:17     ` Andrew Cooper
2018-09-25 13:33   ` [PATCH v4 13/44] x86emul: support AVX512F fused-multiply-add insns Jan Beulich
2018-11-13 19:28     ` Andrew Cooper
2018-09-25 13:34   ` [PATCH v4 14/44] x86emul: support AVX512F legacy-equivalent logic insns Jan Beulich
2018-11-13 19:30     ` Andrew Cooper
2018-09-25 13:35   ` [PATCH v4 15/44] x86emul: support AVX512{F, DQ} FP broadcast insns Jan Beulich
2018-11-13 19:37     ` Andrew Cooper
2018-09-25 13:35   ` [PATCH v4 16/44] x86emul: support AVX512F v{, u}comis{d, s} insns Jan Beulich
2018-11-13 19:39     ` Andrew Cooper
2018-09-25 13:36   ` [PATCH v4 17/44] x86emul/test: introduce eq() Jan Beulich
2018-10-26 11:31     ` Andrew Cooper
2018-09-25 13:37   ` [PATCH v4 18/44] x86emul: support AVX512{F, BW} packed integer compare insns Jan Beulich
2018-09-25 13:37   ` [PATCH v4 19/44] x86emul: support AVX512{F, BW} packed integer arithmetic insns Jan Beulich
2018-09-25 13:38   ` [PATCH v4 20/44] x86emul: use simd_128 also for legacy vector shift insns Jan Beulich
2018-09-25 13:39   ` [PATCH v4 21/44] x86emul: support AVX512{F, BW} shift/rotate insns Jan Beulich
2018-09-25 13:40   ` [PATCH v4 22/44] x86emul: support AVX512{F, BW, DQ} extract insns Jan Beulich
2018-09-25 13:40   ` [PATCH v4 23/44] x86emul: support AVX512{F, BW, DQ} insert insns Jan Beulich
2018-09-25 13:41   ` [PATCH v4 24/44] x86emul: basic AVX512F testing Jan Beulich
2018-09-25 13:41   ` [PATCH v4 25/44] x86emul: support AVX512{F, BW, DQ} integer broadcast insns Jan Beulich
2018-09-25 13:42   ` [PATCH v4 26/44] x86emul: basic AVX512VL testing Jan Beulich
2018-09-25 13:43   ` [PATCH v4 27/44] x86emul: support AVX512{F, BW} zero- and sign-extending moves Jan Beulich
2018-09-25 13:43   ` [PATCH v4 28/44] x86emul: support AVX512{F, BW} down conversion moves Jan Beulich
2018-09-25 13:44   ` [PATCH v4 29/44] x86emul: support AVX512{F, BW} integer unpack insns Jan Beulich
2018-09-25 13:44   ` [PATCH v4 30/44] x86emul: support AVX512{F, BW, _VBMI} full permute insns Jan Beulich
2018-09-25 13:46   ` [PATCH v4 31/44] x86emul: support AVX512{F, BW} integer shuffle insns Jan Beulich
2018-09-25 13:46   ` [PATCH v4 32/44] x86emul: support AVX512{BW, DQ} mask move insns Jan Beulich
2018-09-25 13:47   ` [PATCH v4 33/44] x86emul: basic AVX512BW testing Jan Beulich
2018-09-25 13:48   ` [PATCH v4 34/44] x86emul: basic AVX512DQ testing Jan Beulich
2018-09-25 13:48   ` [PATCH v4 35/44] x86emul: support AVX512F move high/low insns Jan Beulich
2018-09-25 13:49   ` [PATCH v4 36/44] x86emul: support AVX512F move duplicate insns Jan Beulich
2018-09-25 13:49   ` [PATCH v4 37/44] x86emul: support AVX512{F, BW, VBMI} permute insns Jan Beulich
2018-09-25 13:50   ` [PATCH v4 38/44] x86emul: support AVX512BW pack insns Jan Beulich
2018-09-25 13:51   ` [PATCH v4 39/44] x86emul: support AVX512F floating-point conversion insns Jan Beulich
2018-09-25 13:52   ` [PATCH v4 40/44] x86emul: support AVX512F legacy-equivalent packed int/FP " Jan Beulich
2018-09-25 13:53   ` [PATCH v4 41/44] x86emul: support AVX512F legacy-equivalent scalar " Jan Beulich
2018-09-25 13:53   ` [PATCH v4 42/44] x86emul: support AVX512DQ packed quad-int/FP " Jan Beulich
2018-09-25 13:54   ` [PATCH v4 43/44] x86emul: support AVX512{F, DQ} uint-to-FP " Jan Beulich
2018-09-25 13:55   ` [PATCH v4 44/44] x86emul: support AVX512{F, DQ} FP-to-uint " Jan Beulich
2018-11-19 10:00 ` [PATCH v5 00/47] x86emul: fair parts of AVX512 support Jan Beulich
2018-11-19 10:13   ` [PATCH v5 01/47] x86emul: introduce IMPOSSIBLE() Jan Beulich
2018-11-19 18:11     ` Andrew Cooper
2018-11-20  8:12       ` Jan Beulich
2018-11-19 10:13   ` [PATCH v5 02/47] x86emul: support basic AVX512 moves Jan Beulich
2018-11-19 18:35     ` Andrew Cooper
2018-11-19 10:14   ` [PATCH v5 03/47] x86emul: test for correct EVEX Disp8 scaling Jan Beulich
2018-11-19 18:35     ` Andrew Cooper
2018-11-19 10:14   ` [PATCH v5 04/47] x86emul: also allow running the 32-bit harness on a 64-bit distro Jan Beulich
2018-11-19 18:40     ` Andrew Cooper
2018-11-19 10:15   ` [PATCH v5 05/47] x86emul: use AVX512 logic for emulating V{, P}MASKMOV* Jan Beulich
2018-11-19 10:16   ` [PATCH v5 06/47] x86emul: support AVX512F legacy-equivalent arithmetic FP insns Jan Beulich
2018-11-19 10:16   ` [PATCH v5 07/47] x86emul: support AVX512DQ logic " Jan Beulich
2018-11-19 10:17   ` [PATCH v5 08/47] x86emul: support basic AVX512F FP compare insns Jan Beulich
2018-11-19 10:17   ` [PATCH v5 09/47] x86emul: support AVX512F misc legacy-equivalent FP insns Jan Beulich
2018-11-19 10:18   ` [PATCH v5 10/47] x86emul: support AVX512F fused-multiply-add insns Jan Beulich
2018-11-19 10:18   ` [PATCH v5 11/47] x86emul: support AVX512F legacy-equivalent logic insns Jan Beulich
2018-11-19 10:19   ` [PATCH v5 12/47] x86emul: support AVX512{F, DQ} FP broadcast insns Jan Beulich
2018-11-19 18:44     ` Andrew Cooper
2018-11-19 10:20   ` [PATCH v5 13/47] x86emul: support AVX512F v{, u}comis{d, s} insns Jan Beulich
2018-11-19 10:21   ` [PATCH v5 14/47] x86emul: support AVX512{F, BW} packed integer compare insns Jan Beulich
2018-11-19 19:09     ` Andrew Cooper
2018-11-19 10:21   ` [PATCH v5 15/47] x86emul: support AVX512{F, BW} packed integer arithmetic insns Jan Beulich
2018-11-19 19:18     ` Andrew Cooper
2018-11-19 10:22   ` [PATCH v5 16/47] x86emul: use simd_128 also for legacy vector shift insns Jan Beulich
2018-11-19 19:21     ` Andrew Cooper
2018-11-19 10:22   ` [PATCH v5 17/47] x86emul: support AVX512{F, BW} shift/rotate insns Jan Beulich
2018-11-19 10:23   ` [PATCH v5 18/47] x86emul: support AVX512{F, BW, DQ} extract insns Jan Beulich
2018-11-19 10:23   ` [PATCH v5 19/47] x86emul: support AVX512{F, BW, DQ} insert insns Jan Beulich
2018-11-19 10:24   ` [PATCH v5 20/47] x86emul: basic AVX512F testing Jan Beulich
2018-11-19 10:25   ` [PATCH v5 21/47] x86emul: support AVX512{F, BW, DQ} integer broadcast insns Jan Beulich
2018-11-19 10:25   ` [PATCH v5 22/47] x86emul: basic AVX512VL testing Jan Beulich
2018-11-19 10:26   ` [PATCH v5 23/47] x86emul: support AVX512{F, BW} zero- and sign-extending moves Jan Beulich
2018-11-19 10:26   ` [PATCH v5 24/47] x86emul: support AVX512{F, BW} down conversion moves Jan Beulich
2018-11-19 10:28   ` [PATCH v5 25/47] x86emul: support AVX512{F, BW} integer unpack insns Jan Beulich
2018-11-19 10:28   ` [PATCH v5 26/47] x86emul: support AVX512{F, BW, _VBMI} full permute insns Jan Beulich
2018-11-19 10:29   ` [PATCH v5 27/47] x86emul: support AVX512{F, BW} integer shuffle insns Jan Beulich
2018-11-19 10:30   ` [PATCH v5 28/47] x86emul: support AVX512{BW, DQ} mask move insns Jan Beulich
2018-11-19 10:30   ` [PATCH v5 29/47] x86emul: basic AVX512BW testing Jan Beulich
2018-11-19 10:31   ` [PATCH v5 30/47] x86emul: basic AVX512DQ testing Jan Beulich
2018-11-19 10:31   ` [PATCH v5 31/47] x86emul: support AVX512F move high/low insns Jan Beulich
2018-11-19 10:31   ` [PATCH v5 32/47] x86emul: support AVX512F move duplicate insns Jan Beulich
2018-11-19 10:32   ` [PATCH v5 33/47] x86emul: support AVX512{F, BW, VBMI} permute insns Jan Beulich
2018-11-19 10:33   ` [PATCH v5 34/47] x86emul: support AVX512BW pack insns Jan Beulich
2018-11-19 10:33   ` [PATCH v5 35/47] x86emul: support AVX512F floating-point conversion insns Jan Beulich
2018-11-19 10:34   ` [PATCH v5 36/47] x86emul: support AVX512F legacy-equivalent packed int/FP " Jan Beulich
2018-11-19 10:35   ` [PATCH v5 37/47] x86emul: support AVX512F legacy-equivalent scalar " Jan Beulich
2018-11-19 10:36   ` [PATCH v5 38/47] x86emul: support AVX512DQ packed quad-int/FP " Jan Beulich
2018-11-19 10:37   ` [PATCH v5 39/47] x86emul: support AVX512{F, DQ} uint-to-FP " Jan Beulich
2018-11-19 10:37   ` [PATCH v5 40/47] x86emul: support AVX512{F, DQ} FP-to-uint " Jan Beulich
2018-11-19 10:38   ` [PATCH v5 41/47] x86emul: support remaining AVX512F legacy-equivalent insns Jan Beulich
2018-11-19 10:38   ` [PATCH v5 42/47] x86emul: support remaining AVX512BW " Jan Beulich
2018-11-19 10:39   ` [PATCH v5 43/47] x86emul: support AVX512{F, ER} reciprocal insns Jan Beulich
2018-11-19 10:39   ` [PATCH v5 44/47] x86emul: support AVX512F floating point manipulation insns Jan Beulich
2018-11-19 10:40   ` [PATCH v5 45/47] x86emul: support AVX512DQ " Jan Beulich
2018-11-19 10:40   ` [PATCH v5 46/47] x86emul: support AVX512{F, _VBMI2} compress/expand insns Jan Beulich
2018-11-19 10:41   ` [PATCH v5 47/47] x86emul: support remaining misc AVX512{F, BW} insns Jan Beulich
2018-12-06  9:45 ` [PATCH v6 00/42] x86emul: fair parts of AVX512 support Jan Beulich
2018-12-06  9:51   ` [PATCH v6 01/42] x86emul: support AVX512{F, BW} shift/rotate insns Jan Beulich
2018-12-06  9:51   ` [PATCH v6 02/42] x86emul: support AVX512{F, BW, DQ} extract insns Jan Beulich
2018-12-06  9:51   ` [PATCH v6 03/42] x86emul: support AVX512{F, BW, DQ} insert insns Jan Beulich
2018-12-06  9:52   ` [PATCH v6 04/42] x86emul: basic AVX512F testing Jan Beulich
2018-12-06  9:53   ` [PATCH v6 05/42] x86emul: support AVX512{F, BW, DQ} integer broadcast insns Jan Beulich
2018-12-06  9:53   ` [PATCH v6 06/42] x86emul: basic AVX512VL testing Jan Beulich
2018-12-06  9:53   ` [PATCH v6 07/42] x86emul: support AVX512{F, BW} zero- and sign-extending moves Jan Beulich
2018-12-06  9:54   ` [PATCH v6 08/42] x86emul: support AVX512{F, BW} down conversion moves Jan Beulich
2018-12-06  9:54   ` [PATCH v6 09/42] x86emul: support AVX512{F, BW} integer unpack insns Jan Beulich
2018-12-06  9:55   ` [PATCH v6 10/42] x86emul: support AVX512{F, BW, _VBMI} full permute insns Jan Beulich
2018-12-06  9:55   ` [PATCH v6 11/42] x86emul: support AVX512{F, BW} integer shuffle insns Jan Beulich
2018-12-06  9:55   ` [PATCH v6 12/42] x86emul: support AVX512{BW, DQ} mask move insns Jan Beulich
2018-12-06  9:56   ` [PATCH v6 13/42] x86emul: basic AVX512BW testing Jan Beulich
2018-12-06  9:57   ` [PATCH v6 14/42] x86emul: basic AVX512DQ testing Jan Beulich
2018-12-06  9:57   ` [PATCH v6 15/42] x86emul: support AVX512F move high/low insns Jan Beulich
2018-12-06  9:58   ` [PATCH v6 16/42] x86emul: support AVX512F move duplicate insns Jan Beulich
2018-12-06  9:59   ` [PATCH v6 17/42] x86emul: support AVX512{F, BW, _VBMI} permute insns Jan Beulich
2018-12-06  9:59   ` [PATCH v6 18/42] x86emul: support AVX512BW pack insns Jan Beulich
2018-12-06 10:00   ` [PATCH v6 19/42] x86emul: support AVX512F floating-point conversion insns Jan Beulich
2018-12-06 10:00   ` [PATCH v6 20/42] x86emul: support AVX512F legacy-equivalent packed int/FP " Jan Beulich
2018-12-06 10:01   ` [PATCH v6 21/42] x86emul: support AVX512F legacy-equivalent scalar " Jan Beulich
2018-12-06 10:01   ` [PATCH v6 22/42] x86emul: support AVX512DQ packed quad-int/FP " Jan Beulich
2018-12-06 10:02   ` [PATCH v6 23/42] x86emul: support AVX512{F, DQ} uint-to-FP " Jan Beulich
2018-12-06 10:02   ` [PATCH v6 24/42] x86emul: support AVX512{F, DQ} FP-to-uint " Jan Beulich
2018-12-06 10:04   ` [PATCH v6 25/42] x86emul: support remaining AVX512F legacy-equivalent insns Jan Beulich
2018-12-06 10:04   ` [PATCH v6 26/42] x86emul: support remaining AVX512BW " Jan Beulich
2018-12-06 10:04   ` [PATCH v6 27/42] x86emul: support AVX512{F, ER} reciprocal insns Jan Beulich
2018-12-06 10:05   ` [PATCH v6 28/42] x86emul: support AVX512F floating point manipulation insns Jan Beulich
2018-12-06 10:05   ` [PATCH v6 29/42] x86emul: support AVX512DQ " Jan Beulich
2018-12-06 10:06   ` [PATCH v6 30/42] x86emul: support AVX512{F, _VBMI2} compress/expand insns Jan Beulich
2018-12-06 10:07   ` [PATCH v6 31/42] x86emul: support remaining misc AVX512{F, BW} insns Jan Beulich
2018-12-06 10:07   ` [PATCH v6 32/42] x86emul: support AVX512F gather insns Jan Beulich
2018-12-06 10:08   ` [PATCH v6 33/42] x86emul: add high register S/G test cases Jan Beulich
2018-12-06 10:08   ` [PATCH v6 34/42] x86emul: support AVX512F scatter insns Jan Beulich
2018-12-06 10:09   ` [PATCH v6 35/42] x86emul: support AVX512PF insns Jan Beulich
2018-12-06 10:09   ` [PATCH v6 36/42] x86emul: support AVX512CD insns Jan Beulich
2018-12-06 10:10   ` [PATCH v6 37/42] x86emul: complete support of AVX512_VBMI insns Jan Beulich
2018-12-06 10:10   ` [PATCH v6 38/42] x86emul: support of AVX512* population count insns Jan Beulich
2018-12-06 10:11   ` [PATCH v6 39/42] x86emul: support of AVX512_IFMA insns Jan Beulich
2018-12-06 10:11   ` [PATCH v6 40/42] x86emul: support remaining AVX512_VBMI2 insns Jan Beulich
2018-12-06 10:12   ` [PATCH v6 41/42] x86emul: support AVX512_4FMAPS insns Jan Beulich
2018-12-06 10:12   ` [PATCH v6 42/42] x86emul: support AVX512_4VNNIW insns Jan Beulich
2018-12-19 14:17 ` [PATCH v7 00/49] x86emul: remaining AVX512 support Jan Beulich
2018-12-19 14:34   ` Jan Beulich
2018-12-19 14:35   ` [PATCH v7 01/49] x86emul: rename evex.br to evex.brs Jan Beulich
2018-12-19 15:14     ` Andrew Cooper
2018-12-19 14:36   ` [PATCH v7 02/49] x86emul: support AVX512{F, BW} shift/rotate insns Jan Beulich
2018-12-19 16:00     ` Andrew Cooper
2018-12-19 14:36   ` [PATCH v7 03/49] x86emul: support AVX512{F, BW, DQ} extract insns Jan Beulich
2018-12-19 18:20     ` Andrew Cooper
2018-12-20  7:49       ` Jan Beulich
2018-12-19 14:37   ` [PATCH v7 04/49] x86emul: support AVX512{F, BW, DQ} insert insns Jan Beulich
2019-03-14 15:35     ` Andrew Cooper
2018-12-19 14:37   ` [PATCH v7 05/49] x86emul: basic AVX512F testing Jan Beulich
2019-03-14 15:42     ` Andrew Cooper
2018-12-19 14:38   ` [PATCH v7 06/49] x86emul: support AVX512{F, BW, DQ} integer broadcast insns Jan Beulich
2019-03-14 16:38     ` Andrew Cooper
2019-03-14 17:15       ` Jan Beulich
2019-03-15 16:39         ` Andrew Cooper
2019-03-18  9:45           ` Jan Beulich
2018-12-19 14:38   ` [PATCH v7 07/49] x86emul: basic AVX512VL testing Jan Beulich
2019-03-14 16:39     ` Andrew Cooper
2018-12-19 14:41   ` [PATCH v7 08/49] x86emul: support AVX512{F, BW} zero- and sign-extending moves Jan Beulich
2018-12-19 14:41   ` [PATCH v7 09/49] x86emul: support AVX512{F, BW} down conversion moves Jan Beulich
2018-12-19 14:42   ` [PATCH v7 10/49] x86emul: support AVX512{F, BW} integer unpack insns Jan Beulich
2018-12-19 14:42   ` [PATCH v7 11/49] x86emul: support AVX512{F, BW, _VBMI} full permute insns Jan Beulich
2018-12-19 14:43   ` [PATCH v7 12/49] x86emul: support AVX512{F, BW} integer shuffle insns Jan Beulich
2018-12-19 14:43   ` [PATCH v7 13/49] x86emul: support AVX512{BW, DQ} mask move insns Jan Beulich
2018-12-19 14:44   ` [PATCH v7 14/49] x86emul: basic AVX512BW testing Jan Beulich
2018-12-19 14:46   ` [PATCH v7 15/49] x86emul: basic AVX512DQ testing Jan Beulich
2018-12-19 14:46   ` [PATCH v7 16/49] x86emul: support AVX512F move high/low insns Jan Beulich
2018-12-19 14:47   ` [PATCH v7 17/49] x86emul: support AVX512F move duplicate insns Jan Beulich
2018-12-19 14:47   ` [PATCH v7 18/49] x86emul: support AVX512{F, BW, _VBMI} permute insns Jan Beulich
2018-12-19 14:48   ` [PATCH v7 19/49] x86emul: support AVX512BW pack insns Jan Beulich
2018-12-19 14:48   ` [PATCH v7 20/49] x86emul: support AVX512F floating-point conversion insns Jan Beulich
2018-12-19 14:48   ` [PATCH v7 21/49] x86emul: support AVX512F legacy-equivalent packed int/FP " Jan Beulich
2018-12-19 14:51   ` [PATCH v7 22/49] x86emul: support AVX512F legacy-equivalent scalar " Jan Beulich
2018-12-19 14:51   ` [PATCH v7 23/49] x86emul: support AVX512DQ packed quad-int/FP " Jan Beulich
2018-12-19 14:52   ` [PATCH v7 24/49] x86emul: support AVX512{F, DQ} uint-to-FP " Jan Beulich
2018-12-19 14:52   ` [PATCH v7 25/49] x86emul: support AVX512{F, DQ} FP-to-uint " Jan Beulich
2018-12-19 14:53   ` [PATCH v7 26/49] x86emul: support remaining AVX512F legacy-equivalent insns Jan Beulich
2018-12-19 14:53   ` [PATCH v7 27/49] x86emul: support remaining AVX512BW " Jan Beulich
2018-12-19 14:54   ` [PATCH v7 28/49] x86emul: support AVX512{F, ER} reciprocal insns Jan Beulich
2018-12-19 14:55   ` [PATCH v7 29/49] x86emul: support AVX512F floating point manipulation insns Jan Beulich
2018-12-19 14:55   ` [PATCH v7 30/49] x86emul: support AVX512DQ " Jan Beulich
2018-12-19 14:56   ` [PATCH v7 31/49] x86emul: support AVX512{F, _VBMI2} compress/expand insns Jan Beulich
2018-12-19 14:56   ` [PATCH v7 32/49] x86emul: support remaining misc AVX512{F, BW} insns Jan Beulich
2018-12-19 14:57   ` [PATCH v7 33/49] x86emul: support AVX512F gather insns Jan Beulich
2018-12-19 14:57   ` [PATCH v7 34/49] x86emul: add high register S/G test cases Jan Beulich
2018-12-19 14:58   ` [PATCH v7 35/49] x86emul: support AVX512F scatter insns Jan Beulich
2018-12-19 14:59   ` [PATCH v7 36/49] x86emul: support AVX512PF insns Jan Beulich
2018-12-19 14:59   ` [PATCH v7 37/49] x86emul: support AVX512CD insns Jan Beulich
2018-12-19 15:00   ` [PATCH v7 38/49] x86emul: complete support of AVX512_VBMI insns Jan Beulich
2018-12-19 15:00   ` [PATCH v7 39/49] x86emul: support of AVX512* population count insns Jan Beulich
2018-12-19 15:01   ` [PATCH v7 40/49] x86emul: support of AVX512_IFMA insns Jan Beulich
2018-12-19 15:01   ` [PATCH v7 42/49] x86emul: support remaining AVX512_VBMI2 insns Jan Beulich
2018-12-19 15:02   ` [PATCH v7 42/49] x86emul: support AVX512_4FMAPS insns Jan Beulich
2018-12-19 15:05   ` [PATCH v7 43/49] x86emul: support AVX512_4VNNIW insns Jan Beulich
2018-12-19 15:06   ` [PATCH v7 44/49] x86emul: support AVX512_VNNI insns Jan Beulich
2018-12-19 15:06   ` [PATCH v7 45/49] x86emul: support VPCLMULQDQ insns Jan Beulich
2018-12-19 15:07   ` [PATCH v7 46/49] x86emul: support VAES insns Jan Beulich
2018-12-19 15:07   ` [PATCH v7 47/49] x86emul: support GFNI insns Jan Beulich
2018-12-19 15:07   ` [PATCH v7 48/49] x86emul: restore ordering within main switch statement Jan Beulich
2018-12-19 15:08   ` [PATCH v7 49/49] tools: re-sync CPUID leaf 7 tables Jan Beulich
2019-03-14 11:07     ` Andrew Cooper
2019-03-15 10:30 ` [PATCH v8 00/50] x86emul: remaining AVX512 support Jan Beulich
2019-03-15 10:36   ` [PATCH v8 01/50] x86emul: no need to set fault_suppression to false for VMOVNT* Jan Beulich
2019-03-15 16:52     ` Andrew Cooper
2019-03-15 10:36   ` [PATCH v8 02/50] x86emul: support AVX512{F, BW, DQ} extract insns Jan Beulich
2019-03-15 17:51     ` Andrew Cooper
2019-03-15 10:37   ` [PATCH v8 03/50] x86emul: support AVX512{F, BW, DQ} insert insns Jan Beulich
2019-03-15 10:38   ` [PATCH v8 04/50] x86emul: basic AVX512F testing Jan Beulich
2019-03-15 10:39   ` [PATCH v8 05/50] x86emul: support AVX512{F, BW, DQ} integer broadcast insns Jan Beulich
2019-03-15 10:39   ` [PATCH v8 06/50] x86emul: basic AVX512VL testing Jan Beulich
2019-03-15 10:40   ` [PATCH v8 07/50] x86emul: support AVX512{F, BW} zero- and sign-extending moves Jan Beulich
2019-03-15 18:02     ` Andrew Cooper
2019-03-15 10:40   ` [PATCH v8 08/50] x86emul: support AVX512{F, BW} down conversion moves Jan Beulich
2019-03-15 18:10     ` Andrew Cooper
2019-03-15 10:41   ` [PATCH v8 09/50] x86emul: support AVX512{F, BW} integer unpack insns Jan Beulich
2019-03-15 18:21     ` Andrew Cooper
2019-03-18  9:55       ` Jan Beulich
2019-05-20 12:11         ` Andrew Cooper
2019-05-20 12:11           ` [Xen-devel] " Andrew Cooper
2019-03-15 10:41   ` [PATCH v8 10/50] x86emul: support AVX512{F, BW, _VBMI} full permute insns Jan Beulich
2019-05-17 16:50     ` Andrew Cooper
2019-05-17 16:50       ` [Xen-devel] " Andrew Cooper
2019-05-20  6:55       ` Jan Beulich
2019-05-20  6:55         ` [Xen-devel] " Jan Beulich
2019-05-20 12:10         ` Andrew Cooper
2019-05-20 12:10           ` [Xen-devel] " Andrew Cooper
2019-03-15 10:43   ` [PATCH v8 11/50] x86emul: support AVX512{F, BW} integer shuffle insns Jan Beulich
2019-05-17 17:01     ` Andrew Cooper
2019-05-17 17:01       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:43   ` [PATCH v8 12/50] x86emul: support AVX512{BW, DQ} mask move insns Jan Beulich
2019-05-17 17:02     ` Andrew Cooper
2019-05-17 17:02       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:43   ` [PATCH v8 13/50] x86emul: basic AVX512BW testing Jan Beulich
2019-05-17 17:03     ` Andrew Cooper
2019-05-17 17:03       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:44   ` [PATCH v8 14/50] x86emul: basic AVX512DQ testing Jan Beulich
2019-05-17 17:03     ` Andrew Cooper
2019-05-17 17:03       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:44   ` [PATCH v8 15/50] x86emul: support AVX512F move high/low insns Jan Beulich
2019-05-21 10:59     ` Andrew Cooper
2019-05-21 10:59       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:45   ` [PATCH v8 16/50] x86emul: support AVX512F move duplicate insns Jan Beulich
2019-05-21 11:09     ` Andrew Cooper
2019-05-21 11:09       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:46   ` [PATCH v8 17/50] x86emul: support AVX512{F, BW, _VBMI} permute insns Jan Beulich
2019-05-21 11:24     ` Andrew Cooper
2019-05-21 11:24       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:46   ` [PATCH v8 18/50] x86emul: support AVX512BW pack insns Jan Beulich
2019-05-21 11:26     ` Andrew Cooper
2019-05-21 11:26       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:47   ` [PATCH v8 19/50] x86emul: support AVX512F floating-point conversion insns Jan Beulich
2019-05-21 11:33     ` Andrew Cooper
2019-05-21 11:33       ` [Xen-devel] " Andrew Cooper
2019-05-21 15:46       ` Jan Beulich
2019-05-21 15:46         ` [Xen-devel] " Jan Beulich
2019-05-23 16:08         ` Andrew Cooper
2019-05-23 16:08           ` [Xen-devel] " Andrew Cooper
2019-03-15 10:47   ` [PATCH v8 20/50] x86emul: support AVX512F legacy-equivalent packed int/FP " Jan Beulich
2019-05-21 11:37     ` Andrew Cooper
2019-05-21 11:37       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:52   ` [PATCH v8 21/50] x86emul: support AVX512F legacy-equivalent scalar " Jan Beulich
2019-05-21 11:44     ` Andrew Cooper
2019-05-21 11:44       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:52   ` [PATCH v8 22/50] x86emul: support AVX512DQ packed quad-int/FP " Jan Beulich
2019-05-21 11:53     ` Andrew Cooper
2019-05-21 11:53       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:53   ` [PATCH v8 23/50] x86emul: support AVX512{F, DQ} uint-to-FP " Jan Beulich
2019-05-21 11:58     ` Andrew Cooper
2019-05-21 11:58       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:54   ` [PATCH v8 24/50] x86emul: support AVX512{F, DQ} FP-to-uint " Jan Beulich
2019-05-21 12:09     ` Andrew Cooper
2019-05-21 12:09       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:54   ` [PATCH v8 25/50] x86emul: support remaining AVX512F legacy-equivalent insns Jan Beulich
2019-05-21 13:06     ` Andrew Cooper
2019-05-21 13:06       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:54   ` [PATCH v8 26/50] x86emul: support remaining AVX512BW " Jan Beulich
2019-05-21 13:08     ` Andrew Cooper
2019-05-21 13:08       ` [Xen-devel] " Andrew Cooper
2019-05-21 13:34       ` Jan Beulich
2019-05-21 13:34         ` [Xen-devel] " Jan Beulich
2019-05-23 16:10     ` Andrew Cooper
2019-05-23 16:10       ` [Xen-devel] " Andrew Cooper
2019-03-15 10:55   ` [PATCH v8 27/50] x86emul: support AVX512{F, ER} reciprocal insns Jan Beulich
2019-05-23 16:15     ` Andrew Cooper
2019-05-23 16:15       ` [Xen-devel] " Andrew Cooper
2019-05-24  6:43       ` Jan Beulich
2019-05-24  6:43         ` [Xen-devel] " Jan Beulich
2019-05-24 20:48         ` Andrew Cooper
2019-05-24 20:48           ` [Xen-devel] " Andrew Cooper
2019-05-27  8:02           ` Jan Beulich
2019-05-27  8:02             ` [Xen-devel] " Jan Beulich
2019-05-29 10:00             ` Andrew Cooper
2019-05-29 10:00               ` [Xen-devel] " Andrew Cooper
2019-03-15 10:56   ` [PATCH v8 28/50] x86emul: support AVX512F floating point manipulation insns Jan Beulich
2019-05-29 12:51     ` Andrew Cooper
2019-05-29 12:51       ` [Xen-devel] " Andrew Cooper
2019-05-29 13:15       ` Jan Beulich
2019-05-29 13:15         ` [Xen-devel] " Jan Beulich
2019-06-10 14:01         ` Andrew Cooper
2019-06-10 14:03     ` Andrew Cooper
2019-03-15 10:56   ` [PATCH v8 29/50] x86emul: support AVX512DQ " Jan Beulich
2019-06-10 14:06     ` [Xen-devel] " Andrew Cooper
2019-03-15 10:56   ` [PATCH v8 30/50] x86emul: support AVX512{F, _VBMI2} compress/expand insns Jan Beulich
2019-06-10 14:51     ` [Xen-devel] " Andrew Cooper
2019-06-11 10:20       ` Jan Beulich
2019-06-18 16:24         ` Andrew Cooper
2019-06-19  6:38           ` Jan Beulich
2019-03-15 10:58   ` [PATCH v8 31/50] x86emul: support remaining misc AVX512{F, BW} insns Jan Beulich
2019-06-18 16:42     ` [Xen-devel] " Andrew Cooper
2019-06-19  6:44       ` Jan Beulich
2019-03-15 10:58   ` Jan Beulich [this message]
2019-06-19 12:05     ` [Xen-devel] [PATCH v8 32/50] x86emul: support AVX512F gather insns Andrew Cooper
2019-06-19 12:43       ` Jan Beulich
2019-03-15 10:59   ` [PATCH v8 33/50] x86emul: add high register S/G test cases Jan Beulich
2019-06-19 12:07     ` [Xen-devel] " Andrew Cooper
2019-03-15 10:59   ` [PATCH v8 34/50] x86emul: support AVX512F scatter insns Jan Beulich
2019-03-15 11:00   ` [PATCH v8 35/50] x86emul: support AVX512PF insns Jan Beulich
2019-03-15 11:00   ` [PATCH v8 36/50] x86emul: support AVX512CD insns Jan Beulich
2019-06-19 12:13     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:01   ` [PATCH v8 37/50] x86emul: complete support of AVX512_VBMI insns Jan Beulich
2019-06-19 12:16     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:01   ` [PATCH v8 38/50] x86emul: support of AVX512* population count insns Jan Beulich
2019-06-19 12:22     ` [Xen-devel] " Andrew Cooper
2019-06-19 12:48       ` Jan Beulich
2019-03-15 11:02   ` [PATCH v8 39/50] x86emul: support of AVX512_IFMA insns Jan Beulich
2019-06-19 12:23     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:02   ` [PATCH v8 40/50] x86emul: support remaining AVX512_VBMI2 insns Jan Beulich
2019-06-19 12:25     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:04   ` [PATCH v8 41/50] x86emul: support AVX512_4FMAPS insns Jan Beulich
2019-06-19 14:58     ` [Xen-devel] " Andrew Cooper
2019-06-21  6:50       ` Jan Beulich
2019-03-15 11:04   ` [PATCH v8 42/50] x86emul: support AVX512_4VNNIW insns Jan Beulich
2019-06-19 14:58     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:04   ` [PATCH v8 43/50] x86emul: support AVX512_VNNI insns Jan Beulich
2019-06-19 15:01     ` [Xen-devel] " Andrew Cooper
2019-06-21  6:55       ` Jan Beulich
2019-03-15 11:05   ` [PATCH v8 44/50] x86emul: support VPCLMULQDQ insns Jan Beulich
2019-06-21 12:52     ` [Xen-devel] " Andrew Cooper
2019-06-21 13:44       ` Jan Beulich
2019-03-15 11:06   ` [PATCH v8 45/50] x86emul: support VAES insns Jan Beulich
2019-06-21 12:57     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:06   ` [PATCH v8 46/50] x86emul: support GFNI insns Jan Beulich
2019-06-21 13:19     ` [Xen-devel] " Andrew Cooper
2019-06-21 13:33       ` Andrew Cooper
2019-06-21 14:00       ` Jan Beulich
2019-06-21 14:20         ` Andrew Cooper
2019-06-21 15:02           ` Jan Beulich
2019-06-25  6:48           ` Jan Beulich
2019-03-15 11:07   ` [PATCH v8 47/50] x86emul: restore ordering within main switch statement Jan Beulich
2019-06-21 13:20     ` [Xen-devel] " Andrew Cooper
2019-03-15 11:07   ` [PATCH v8 48/50] x86emul: add an AES/VAES test case to the harness Jan Beulich
2019-06-21 13:36     ` [Xen-devel] " Andrew Cooper
2019-06-21 14:04       ` Jan Beulich
2019-06-21 14:20         ` Andrew Cooper
2019-03-15 11:08   ` [PATCH v8 49/50] x86emul: add a SHA " Jan Beulich
2019-06-21 13:51     ` [Xen-devel] " Andrew Cooper
2019-06-21 14:10       ` Jan Beulich
2019-06-21 14:23         ` Andrew Cooper
2019-03-15 11:08   ` [PATCH v8 50/50] x86emul: add a PCLMUL/VPCLMUL " Jan Beulich
2019-06-21 13:58     ` [Xen-devel] " Andrew Cooper

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