From: Julien Grall <julien.grall@arm.com>
To: Andre Przywara <andre.przywara@arm.com>,
Stefano Stabellini <sstabellini@kernel.org>
Cc: xen-devel@lists.xenproject.org,
Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>,
Vijay Kilari <vijay.kilari@gmail.com>,
Shanker Donthineni <shankerd@codeaurora.org>
Subject: Re: [PATCH v10 02/32] ARM: GICv3: setup number of LPI bits for a GICv3 guest
Date: Tue, 30 May 2017 11:54:51 +0100 [thread overview]
Message-ID: <89a8de5a-682b-3c5e-b95d-24e153518576@arm.com> (raw)
In-Reply-To: <20170526173540.10066-3-andre.przywara@arm.com>
Hi Andre,
On 26/05/17 18:35, Andre Przywara wrote:
> The host supports a certain number of LPI identifiers, as stored in
> the GICD_TYPER register.
> Store this number from the hardware register in vgic_v3_hw to allow
> injecting the very same number into a guest (Dom0).
> DomUs get the legacy number of 10 bits here, since for now it only sees
> SPIs, so it does not need more. This should be revisited once we get
> proper DomU ITS support.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> xen/arch/arm/gic-v3.c | 6 +++++-
> xen/arch/arm/vgic-v3.c | 10 +++++++++-
> xen/include/asm-arm/domain.h | 1 +
> xen/include/asm-arm/vgic.h | 3 ++-
> 4 files changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index a559e5e..29c8964 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -1579,6 +1579,7 @@ static int __init gicv3_init(void)
> {
> int res, i;
> uint32_t reg;
> + unsigned int intid_bits;
>
> if ( !cpu_has_gicv3 )
> {
> @@ -1622,8 +1623,11 @@ static int __init gicv3_init(void)
> i, r->base, r->base + r->size);
> }
>
> + reg = readl_relaxed(GICD + GICD_TYPER);
> + intid_bits = GICD_TYPE_ID_BITS(reg);
> +
> vgic_v3_setup_hw(dbase, gicv3.rdist_count, gicv3.rdist_regions,
> - gicv3.rdist_stride);
> + gicv3.rdist_stride, intid_bits);
> gicv3_init_v2();
>
> spin_lock_init(&gicv3.lock);
> diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
> index d10757a..87f5fb3 100644
> --- a/xen/arch/arm/vgic-v3.c
> +++ b/xen/arch/arm/vgic-v3.c
> @@ -57,18 +57,21 @@ static struct {
> unsigned int nr_rdist_regions;
> const struct rdist_region *regions;
> uint32_t rdist_stride; /* Re-distributor stride */
> + unsigned int intid_bits; /* Number of interrupt ID bits */
> } vgic_v3_hw;
>
> void vgic_v3_setup_hw(paddr_t dbase,
> unsigned int nr_rdist_regions,
> const struct rdist_region *regions,
> - uint32_t rdist_stride)
> + uint32_t rdist_stride,
> + unsigned int intid_bits)
> {
> vgic_v3_hw.enabled = 1;
> vgic_v3_hw.dbase = dbase;
> vgic_v3_hw.nr_rdist_regions = nr_rdist_regions;
> vgic_v3_hw.regions = regions;
> vgic_v3_hw.rdist_stride = rdist_stride;
> + vgic_v3_hw.intid_bits = intid_bits;
> }
>
> static struct vcpu *vgic_v3_irouter_to_vcpu(struct domain *d, uint64_t irouter)
> @@ -1482,6 +1485,8 @@ static int vgic_v3_domain_init(struct domain *d)
>
> first_cpu += size / d->arch.vgic.rdist_stride;
> }
> +
> + d->arch.vgic.intid_bits = vgic_v3_hw.intid_bits;
> }
> else
> {
> @@ -1497,6 +1502,9 @@ static int vgic_v3_domain_init(struct domain *d)
> d->arch.vgic.rdist_regions[0].base = GUEST_GICV3_GICR0_BASE;
> d->arch.vgic.rdist_regions[0].size = GUEST_GICV3_GICR0_SIZE;
> d->arch.vgic.rdist_regions[0].first_cpu = 0;
> +
> + /* TODO: only SPIs for now, adjust this when guests need LPIs */
> + d->arch.vgic.intid_bits = 10;
What if the guest support no SPIs? Should not you based this number of
the number of SPIs supported by the guest?
> }
>
> ret = vgic_v3_its_init_domain(d);
> diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
> index 6de8082..7c3829d 100644
> --- a/xen/include/asm-arm/domain.h
> +++ b/xen/include/asm-arm/domain.h
> @@ -111,6 +111,7 @@ struct arch_domain
> uint32_t rdist_stride; /* Re-Distributor stride */
> struct rb_root its_devices; /* Devices mapped to an ITS */
> spinlock_t its_devices_lock; /* Protects the its_devices tree */
> + unsigned int intid_bits;
> #endif
> } vgic;
>
> diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
> index 544867a..df75064 100644
> --- a/xen/include/asm-arm/vgic.h
> +++ b/xen/include/asm-arm/vgic.h
> @@ -346,7 +346,8 @@ struct rdist_region;
> void vgic_v3_setup_hw(paddr_t dbase,
> unsigned int nr_rdist_regions,
> const struct rdist_region *regions,
> - uint32_t rdist_stride);
> + uint32_t rdist_stride,
> + unsigned int intid_bits);
> #endif
>
> #endif /* __ASM_ARM_VGIC_H__ */
>
Cheers,
--
Julien Grall
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next prev parent reply other threads:[~2017-05-30 10:54 UTC|newest]
Thread overview: 96+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-26 17:35 [PATCH v10 00/32] arm64: Dom0 ITS emulation Andre Przywara
2017-05-26 17:35 ` [PATCH v10 01/32] ARM: vGIC: avoid rank lock when reading priority Andre Przywara
2017-05-30 10:47 ` Julien Grall
2017-05-30 21:39 ` Stefano Stabellini
2017-05-31 10:42 ` Julien Grall
2017-06-02 17:44 ` Julien Grall
2017-06-06 17:06 ` Andre Przywara
2017-06-06 17:11 ` Julien Grall
2017-06-06 17:20 ` Andre Przywara
2017-06-06 17:21 ` Julien Grall
2017-06-06 18:39 ` Stefano Stabellini
2017-05-26 17:35 ` [PATCH v10 02/32] ARM: GICv3: setup number of LPI bits for a GICv3 guest Andre Przywara
2017-05-30 10:54 ` Julien Grall [this message]
2017-06-06 10:19 ` Andre Przywara
2017-05-26 17:35 ` [PATCH v10 03/32] ARM: vGIC: move irq_to_pending() calls under the VGIC VCPU lock Andre Przywara
2017-05-30 11:08 ` Julien Grall
2017-05-30 21:46 ` Stefano Stabellini
2017-05-31 10:44 ` Julien Grall
2017-06-06 17:24 ` Andre Przywara
2017-06-06 18:46 ` Stefano Stabellini
2017-06-07 10:49 ` Andre Przywara
2017-05-26 17:35 ` [PATCH v10 04/32] ARM: vGIC: rework gic_remove_from_queues() Andre Przywara
2017-05-30 11:15 ` Julien Grall
2017-05-26 17:35 ` [PATCH v10 05/32] ARM: vGIC: introduce gic_remove_irq() Andre Przywara
2017-05-30 11:31 ` Julien Grall
2017-06-06 10:19 ` Andre Przywara
2017-05-26 17:35 ` [PATCH v10 06/32] ARM: GIC: Add checks for NULL pointer pending_irq's Andre Przywara
2017-05-30 11:38 ` Julien Grall
2017-06-06 10:19 ` Andre Przywara
2017-06-07 11:19 ` Julien Grall
2017-05-26 17:35 ` [PATCH v10 07/32] ARM: GICv3: introduce separate pending_irq structs for LPIs Andre Przywara
2017-05-26 17:35 ` [PATCH v10 08/32] ARM: GIC: export and extend vgic_init_pending_irq() Andre Przywara
2017-05-26 17:35 ` [PATCH v10 09/32] ARM: vGIC: cache virtual LPI priority in struct pending_irq Andre Przywara
2017-05-26 17:35 ` [PATCH v10 10/32] ARM: vGIC: add LPI VCPU ID to " Andre Przywara
2017-05-26 17:35 ` [PATCH v10 11/32] ARM: GICv3: forward pending LPIs to guests Andre Przywara
2017-05-30 11:56 ` Julien Grall
2017-05-30 22:07 ` Stefano Stabellini
2017-05-31 11:09 ` Julien Grall
2017-05-31 17:56 ` Stefano Stabellini
2017-05-31 18:39 ` Julien Grall
2017-05-26 17:35 ` [PATCH v10 12/32] ARM: GICv3: enable ITS and LPIs on the host Andre Przywara
2017-05-30 11:58 ` Julien Grall
2017-05-26 17:35 ` [PATCH v10 13/32] ARM: vGICv3: handle virtual LPI pending and property tables Andre Przywara
2017-05-26 17:35 ` [PATCH v10 14/32] ARM: introduce vgic_access_guest_memory() Andre Przywara
2017-05-26 17:35 ` [PATCH v10 15/32] ARM: vGICv3: re-use vgic_reg64_check_access Andre Przywara
2017-05-26 17:35 ` [PATCH v10 16/32] ARM: vGIC: advertise LPI support Andre Przywara
2017-05-30 12:59 ` Julien Grall
2017-05-26 17:35 ` [PATCH v10 17/32] ARM: vITS: add command handling stub and MMIO emulation Andre Przywara
2017-06-01 18:13 ` Julien Grall
2017-06-08 9:57 ` Julien Grall
2017-05-26 17:35 ` [PATCH v10 18/32] ARM: vITS: introduce translation table walks Andre Przywara
2017-06-02 16:25 ` Julien Grall
2017-06-08 9:35 ` Julien Grall
2017-06-08 9:45 ` Andre Przywara
2017-05-26 17:35 ` [PATCH v10 19/32] ARM: vITS: provide access to struct pending_irq Andre Przywara
2017-06-02 16:32 ` Julien Grall
2017-06-02 16:45 ` Julien Grall
2017-06-06 10:19 ` Andre Przywara
2017-06-06 11:13 ` Julien Grall
2017-05-26 17:35 ` [PATCH v10 20/32] ARM: vITS: handle INT command Andre Przywara
2017-06-02 16:37 ` Julien Grall
2017-05-26 17:35 ` [PATCH v10 21/32] ARM: vITS: handle MAPC command Andre Przywara
2017-05-26 17:35 ` [PATCH v10 22/32] ARM: vITS: handle CLEAR command Andre Przywara
2017-06-02 16:40 ` Julien Grall
2017-05-26 17:35 ` [PATCH v10 23/32] ARM: vITS: handle MAPD command Andre Przywara
2017-06-02 16:46 ` Julien Grall
2017-05-26 17:35 ` [PATCH v10 24/32] ARM: GICv3: handle unmapped LPIs Andre Przywara
2017-06-02 16:55 ` Julien Grall
2017-06-02 20:45 ` Stefano Stabellini
2017-06-08 9:45 ` Julien Grall
2017-06-08 13:51 ` Andre Przywara
2017-05-26 17:35 ` [PATCH v10 25/32] ARM: vITS: handle MAPTI/MAPI command Andre Przywara
2017-06-02 17:12 ` Julien Grall
2017-06-07 17:49 ` Andre Przywara
2017-06-12 16:33 ` Julien Grall
2017-06-09 11:17 ` Andre Przywara
2017-06-09 19:14 ` Stefano Stabellini
2017-06-12 16:10 ` Andre Przywara
2017-05-26 17:35 ` [PATCH v10 26/32] ARM: vITS: handle MOVI command Andre Przywara
2017-05-30 22:35 ` Stefano Stabellini
2017-05-31 11:23 ` Julien Grall
2017-05-31 17:53 ` Stefano Stabellini
2017-05-31 18:49 ` Julien Grall
2017-06-02 17:17 ` Julien Grall
2017-06-02 20:36 ` Stefano Stabellini
2017-05-26 17:35 ` [PATCH v10 27/32] ARM: vITS: handle DISCARD command Andre Przywara
2017-06-02 17:21 ` Julien Grall
2017-05-26 17:35 ` [PATCH v10 28/32] ARM: vITS: handle INV command Andre Przywara
2017-05-30 22:23 ` Stefano Stabellini
2017-05-26 17:35 ` [PATCH v10 29/32] ARM: vITS: handle INVALL command Andre Przywara
2017-06-02 17:27 ` Julien Grall
2017-05-26 17:35 ` [PATCH v10 30/32] ARM: vITS: increase mmio_count for each ITS Andre Przywara
2017-05-26 17:35 ` [PATCH v10 31/32] ARM: vITS: create and initialize virtual ITSes for Dom0 Andre Przywara
2017-06-02 17:31 ` Julien Grall
2017-05-26 17:35 ` [PATCH v10 32/32] ARM: vITS: create ITS subnodes for Dom0 DT Andre Przywara
2017-06-02 17:33 ` Julien Grall
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