From: Stefano Stabellini <sstabellini@kernel.org>
To: Julien Grall <julien.grall@arm.com>
Cc: sstabellini@kernel.org, wei.chen@arm.com, steve.capper@arm.com,
xen-devel@lists.xen.org, shannon.zhao@linaro.org,
shankerd@codeaurora.org
Subject: Re: [RFC 1/8] xen/arm: gic: Consolidate the IRQ affinity set in a single place
Date: Wed, 22 Jun 2016 11:46:46 +0100 (BST) [thread overview]
Message-ID: <alpine.DEB.2.10.1606221146400.2575@sstabellini-ThinkPad-X260> (raw)
In-Reply-To: <1465318123-3090-2-git-send-email-julien.grall@arm.com>
On Tue, 7 Jun 2016, Julien Grall wrote:
> The code to set the IRQ affinity is duplicated: once in
> gicv{2,3}_set_properties and the other is gicv{2,3}_irq_set_affinity.
>
> Remove the code from gicv{2,3}_set_properties and call directly the
> affinity set helper from the common code.
>
> Signed-off-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
> xen/arch/arm/gic-v2.c | 10 +---------
> xen/arch/arm/gic-v3.c | 10 ----------
> xen/arch/arm/gic.c | 3 ++-
> xen/include/asm-arm/gic.h | 1 -
> 4 files changed, 3 insertions(+), 21 deletions(-)
>
> diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
> index 450755f..90b07b3 100644
> --- a/xen/arch/arm/gic-v2.c
> +++ b/xen/arch/arm/gic-v2.c
> @@ -200,16 +200,10 @@ static unsigned int gicv2_read_irq(void)
> return (readl_gicc(GICC_IAR) & GICC_IA_IRQ);
> }
>
> -/*
> - * needs to be called with a valid cpu_mask, ie each cpu in the mask has
> - * already called gic_cpu_init
> - */
> static void gicv2_set_irq_properties(struct irq_desc *desc,
> - const cpumask_t *cpu_mask,
> - unsigned int priority)
> + unsigned int priority)
> {
> uint32_t cfg, actual, edgebit;
> - unsigned int mask = gicv2_cpu_mask(cpu_mask);
> unsigned int irq = desc->irq;
> unsigned int type = desc->arch.type;
>
> @@ -240,8 +234,6 @@ static void gicv2_set_irq_properties(struct irq_desc *desc,
> IRQ_TYPE_LEVEL_HIGH;
> }
>
> - /* Set target CPU mask (RAZ/WI on uniprocessor) */
> - writeb_gicd(mask, GICD_ITARGETSR + irq);
> /* Set priority */
> writeb_gicd(priority, GICD_IPRIORITYR + irq);
>
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index 9910877..c936c8a 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -472,13 +472,10 @@ static inline uint64_t gicv3_mpidr_to_affinity(int cpu)
> }
>
> static void gicv3_set_irq_properties(struct irq_desc *desc,
> - const cpumask_t *cpu_mask,
> unsigned int priority)
> {
> uint32_t cfg, actual, edgebit;
> - uint64_t affinity;
> void __iomem *base;
> - unsigned int cpu = gicv3_get_cpu_from_mask(cpu_mask);
> unsigned int irq = desc->irq;
> unsigned int type = desc->arch.type;
>
> @@ -516,13 +513,6 @@ static void gicv3_set_irq_properties(struct irq_desc *desc,
> IRQ_TYPE_LEVEL_HIGH;
> }
>
> - affinity = gicv3_mpidr_to_affinity(cpu);
> - /* Make sure we don't broadcast the interrupt */
> - affinity &= ~GICD_IROUTER_SPI_MODE_ANY;
> -
> - if ( irq >= NR_GIC_LOCAL_IRQS )
> - writeq_relaxed(affinity, (GICD + GICD_IROUTER + irq * 8));
> -
> /* Set priority */
> if ( irq < NR_GIC_LOCAL_IRQS )
> writeb_relaxed(priority, GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + irq);
> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
> index 2bfe4de..8a1087b 100644
> --- a/xen/arch/arm/gic.c
> +++ b/xen/arch/arm/gic.c
> @@ -106,7 +106,8 @@ static void gic_set_irq_properties(struct irq_desc *desc,
> const cpumask_t *cpu_mask,
> unsigned int priority)
> {
> - gic_hw_ops->set_irq_properties(desc, cpu_mask, priority);
> + gic_hw_ops->set_irq_properties(desc, priority);
> + desc->handler->set_affinity(desc, cpu_mask);
> }
>
> /* Program the GIC to route an interrupt to the host (i.e. Xen)
> diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
> index cd97bb2..b931f98 100644
> --- a/xen/include/asm-arm/gic.h
> +++ b/xen/include/asm-arm/gic.h
> @@ -331,7 +331,6 @@ struct gic_hw_operations {
> unsigned int (*read_irq)(void);
> /* Set IRQ property */
> void (*set_irq_properties)(struct irq_desc *desc,
> - const cpumask_t *cpu_mask,
> unsigned int priority);
> /* Send SGI */
> void (*send_SGI)(enum gic_sgi sgi, enum gic_sgi_mode irqmode,
> --
> 1.9.1
>
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next prev parent reply other threads:[~2016-06-22 10:46 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-07 16:48 [RFC 0/8] xen/arm: acpi: Support SPIs routing Julien Grall
2016-06-07 16:48 ` [RFC 1/8] xen/arm: gic: Consolidate the IRQ affinity set in a single place Julien Grall
2016-06-22 10:46 ` Stefano Stabellini [this message]
2016-06-07 16:48 ` [RFC 2/8] xen/arm: gic: Do not configure affinity for guest IRQ during routing Julien Grall
2016-06-22 10:54 ` Stefano Stabellini
2016-06-22 11:19 ` Julien Grall
2016-06-07 16:48 ` [RFC 3/8] xen/arm: gic: split set_irq_properties Julien Grall
2016-06-22 10:58 ` Stefano Stabellini
2016-06-07 16:48 ` [RFC 4/8] xen/arm: gic: set_type: Pass the type in parameter rather than in desc->arch.type Julien Grall
2016-06-22 11:25 ` Stefano Stabellini
2016-06-07 16:48 ` [RFC 5/8] xen/arm: gic: Document how gic_set_irq_type should be called Julien Grall
2016-06-22 11:00 ` Stefano Stabellini
2016-06-07 16:48 ` [RFC 6/8] Revert "xen/arm: warn the user that we cannot route SPIs to Dom0 on ACPI" Julien Grall
2016-06-22 11:01 ` Stefano Stabellini
2016-06-07 16:48 ` [RFC 7/8] xen/arm: Allow DOM0 to set the irq type when ACPI is inuse Julien Grall
2016-06-22 11:23 ` Stefano Stabellini
2016-06-22 11:46 ` Julien Grall
2016-06-22 11:49 ` Stefano Stabellini
2016-06-07 16:48 ` [RFC 8/8] xen/arm: acpi: route all unused IRQs to DOM0 Julien Grall
2016-06-22 11:44 ` Stefano Stabellini
2016-06-22 12:19 ` Julien Grall
2016-06-07 18:50 ` [RFC 0/8] xen/arm: acpi: Support SPIs routing Shanker Donthineni
2016-06-08 11:48 ` Shanker Donthineni
2016-06-08 11:49 ` Julien Grall
2016-06-08 12:11 ` Shanker Donthineni
2016-06-08 12:34 ` Julien Grall
2016-06-13 11:42 ` Julien Grall
2016-06-13 17:19 ` Shanker Donthineni
2016-06-13 17:20 ` Julien Grall
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