From: Jan Beulich <jbeulich@suse.com>
To: "Michał Leszczyński" <michal.leszczynski@cert.pl>
Cc: tamas.lengyel@intel.com, "Wei Liu" <wl@xen.org>,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
luwei.kang@intel.com, xen-devel@lists.xenproject.org,
"Roger Pau Monné" <roger.pau@citrix.com>
Subject: Re: [PATCH v4 01/10] x86/vmx: add Intel PT MSR definitions
Date: Tue, 30 Jun 2020 18:23:31 +0200 [thread overview]
Message-ID: <e18c7aa4-2340-85a8-9e17-64325fa99e5b@suse.com> (raw)
In-Reply-To: <2ff9ecee8367e814a29b17a34203bda0e3c48d74.1593519420.git.michal.leszczynski@cert.pl>
On 30.06.2020 14:33, Michał Leszczyński wrote:
> From: Michal Leszczynski <michal.leszczynski@cert.pl>
>
> Define constants related to Intel Processor Trace features.
>
> Signed-off-by: Michal Leszczynski <michal.leszczynski@cert.pl>
This needs re-basing onto current staging, now that Andrew's patch
to add the MSR numbers has gone in. Apart from this a couple of
cosmetic requests:
> --- a/xen/include/asm-x86/msr-index.h
> +++ b/xen/include/asm-x86/msr-index.h
> @@ -69,6 +69,43 @@
> #define MSR_MCU_OPT_CTRL 0x00000123
> #define MCU_OPT_CTRL_RNGDS_MITG_DIS (_AC(1, ULL) << 0)
>
> +/* Intel PT MSRs */
> +#define MSR_RTIT_OUTPUT_BASE 0x00000560
> +
> +#define MSR_RTIT_OUTPUT_MASK 0x00000561
> +
> +#define MSR_RTIT_CTL 0x00000570
> +#define RTIT_CTL_TRACEEN (_AC(1, ULL) << 0)
The right side is indented one space too many - see the similar
#define in context above.
> +#define RTIT_CTL_CYCEN (_AC(1, ULL) << 1)
> +#define RTIT_CTL_OS (_AC(1, ULL) << 2)
> +#define RTIT_CTL_USR (_AC(1, ULL) << 3)
> +#define RTIT_CTL_PWR_EVT_EN (_AC(1, ULL) << 4)
> +#define RTIT_CTL_FUP_ON_PTW (_AC(1, ULL) << 5)
> +#define RTIT_CTL_FABRIC_EN (_AC(1, ULL) << 6)
> +#define RTIT_CTL_CR3_FILTER (_AC(1, ULL) << 7)
> +#define RTIT_CTL_TOPA (_AC(1, ULL) << 8)
> +#define RTIT_CTL_MTC_EN (_AC(1, ULL) << 9)
> +#define RTIT_CTL_TSC_EN (_AC(1, ULL) << 10)
The double blanks on the earlier lines exist such that here you
can reduce to a single one. You'll also find examples of this
further up in the file.
> +#define RTIT_CTL_DIS_RETC (_AC(1, ULL) << 11)
> +#define RTIT_CTL_PTW_EN (_AC(1, ULL) << 12)
> +#define RTIT_CTL_BRANCH_EN (_AC(1, ULL) << 13)
> +#define RTIT_CTL_MTC_FREQ (_AC(0x0F, ULL) << 14)
0xf please (i.e. lower case and no random number of leading
zeros).
> +#define RTIT_CTL_CYC_THRESH (_AC(0x0F, ULL) << 19)
> +#define RTIT_CTL_PSB_FREQ (_AC(0x0F, ULL) << 24)
> +#define RTIT_CTL_ADDR(n) (_AC(0x0F, ULL) << (32 + (4 * (n))))
Strictly speaking we don't need the parentheses around the operands
of binary * here - in mathematics precedence between + and * is
well defined. (We do parenthesize certain other expressions, when
the precedence may not be as well known.)
Thanks, Jan
next prev parent reply other threads:[~2020-06-30 16:23 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-30 12:33 [PATCH v4 00/10] Implement support for external IPT monitoring Michał Leszczyński
2020-06-30 12:33 ` [PATCH v4 01/10] x86/vmx: add Intel PT MSR definitions Michał Leszczyński
2020-06-30 16:23 ` Jan Beulich [this message]
2020-06-30 17:37 ` Andrew Cooper
2020-06-30 18:03 ` Tamas K Lengyel
2020-06-30 18:27 ` Michał Leszczyński
2020-07-01 17:52 ` Andrew Cooper
2020-06-30 12:33 ` [PATCH v4 02/10] x86/vmx: add IPT cpu feature Michał Leszczyński
2020-07-01 9:49 ` Roger Pau Monné
2020-07-01 15:12 ` Julien Grall
2020-07-01 16:06 ` Andrew Cooper
2020-07-01 16:17 ` Julien Grall
2020-07-01 16:18 ` Julien Grall
2020-07-01 17:26 ` Andrew Cooper
2020-07-01 18:02 ` Julien Grall
2020-07-01 18:06 ` Andrew Cooper
2020-07-01 18:09 ` Julien Grall
2020-07-02 8:29 ` Jan Beulich
2020-07-02 8:42 ` Julien Grall
2020-07-02 8:50 ` Jan Beulich
2020-07-02 8:54 ` Julien Grall
2020-07-02 9:18 ` Jan Beulich
2020-07-02 9:57 ` Julien Grall
2020-07-02 13:30 ` Jan Beulich
2020-07-02 14:14 ` Julien Grall
2020-07-02 14:17 ` Jan Beulich
2020-07-02 14:31 ` Julien Grall
2020-07-02 20:28 ` Michał Leszczyński
2020-07-03 7:58 ` Julien Grall
2020-07-04 19:16 ` Michał Leszczyński
2020-07-01 21:42 ` Andrew Cooper
2020-07-02 8:10 ` Roger Pau Monné
2020-07-02 8:34 ` Jan Beulich
2020-07-02 20:29 ` Michał Leszczyński
2020-06-30 12:33 ` [PATCH v4 03/10] tools/libxl: add vmtrace_pt_size parameter Michał Leszczyński
2020-07-01 10:05 ` Roger Pau Monné
2020-07-02 9:00 ` Roger Pau Monné
2020-07-02 16:23 ` Michał Leszczyński
2020-07-03 9:44 ` Roger Pau Monné
2020-07-03 9:56 ` Jan Beulich
2020-07-03 10:11 ` Roger Pau Monné
2020-07-04 17:23 ` Julien Grall
2020-07-06 8:46 ` Jan Beulich
2020-07-07 8:44 ` Julien Grall
2020-07-07 9:10 ` Jan Beulich
2020-07-07 9:16 ` Julien Grall
2020-07-07 11:17 ` Michał Leszczyński
2020-07-07 11:21 ` Jan Beulich
2020-07-07 11:35 ` Michał Leszczyński
2020-07-02 10:24 ` Anthony PERARD
2020-07-04 17:48 ` Julien Grall
2020-06-30 12:33 ` [PATCH v4 04/10] x86/vmx: implement processor tracing for VMX Michał Leszczyński
2020-07-01 10:30 ` Roger Pau Monné
2020-06-30 12:33 ` [PATCH v4 05/10] common/domain: allocate vmtrace_pt_buffer Michał Leszczyński
2020-07-01 10:38 ` Roger Pau Monné
2020-07-01 15:35 ` Julien Grall
2020-06-30 12:33 ` [PATCH v4 06/10] memory: batch processing in acquire_resource() Michał Leszczyński
2020-07-01 10:46 ` Roger Pau Monné
2020-07-03 10:35 ` Julien Grall
2020-07-03 10:52 ` Paul Durrant
2020-07-03 11:17 ` Julien Grall
2020-07-03 11:22 ` Jan Beulich
2020-07-03 11:36 ` Julien Grall
2020-07-03 12:50 ` Jan Beulich
2020-07-03 11:40 ` Paul Durrant
2020-06-30 12:33 ` [PATCH v4 07/10] x86/mm: add vmtrace_buf resource type Michał Leszczyński
2020-07-01 10:52 ` Roger Pau Monné
2020-06-30 12:33 ` [PATCH v4 08/10] x86/domctl: add XEN_DOMCTL_vmtrace_op Michał Leszczyński
2020-07-01 11:00 ` Roger Pau Monné
2020-06-30 12:33 ` [PATCH v4 09/10] tools/libxc: add xc_vmtrace_* functions Michał Leszczyński
2020-07-21 10:52 ` Wei Liu
2020-06-30 12:33 ` [PATCH v4 10/10] tools/proctrace: add proctrace tool Michał Leszczyński
2020-07-02 15:10 ` Andrew Cooper
2020-07-21 10:52 ` Wei Liu
2020-06-30 12:48 ` [PATCH v4 00/10] Implement support for external IPT monitoring Hubert Jasudowicz
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