From: Jan Beulich <jbeulich@suse.com>
To: Roger Pau Monne <roger.pau@citrix.com>
Cc: Stefano Stabellini <sstabellini@kernel.org>,
Julien Grall <julien@xen.org>, Wei Liu <wl@xen.org>,
Andrew Cooper <andrew.cooper3@citrix.com>,
Ian Jackson <ian.jackson@eu.citrix.com>,
George Dunlap <george.dunlap@citrix.com>,
xen-devel@lists.xenproject.org
Subject: Re: [PATCH v3 2/2] x86/idle: prevent entering C6 with in service interrupts on Intel
Date: Mon, 18 May 2020 17:05:12 +0200 [thread overview]
Message-ID: <e9e337ae-295e-5577-3c6d-a42721190b07@suse.com> (raw)
In-Reply-To: <20200515135802.63853-3-roger.pau@citrix.com>
On 15.05.2020 15:58, Roger Pau Monne wrote:
> --- a/docs/misc/xen-command-line.pandoc
> +++ b/docs/misc/xen-command-line.pandoc
> @@ -652,6 +652,15 @@ Specify the size of the console debug trace buffer. By specifying `cpu:`
> additionally a trace buffer of the specified size is allocated per cpu.
> The debug trace feature is only enabled in debugging builds of Xen.
>
> +### disable-c6-errata
Hmm, yes please - a disable for errata! ;-)
How about "avoid-c6-errata", and then perhaps as a sub-option to
"cpuidle="? (If we really want a control for this in the first
place.)
> @@ -573,10 +574,40 @@ bool errata_c6_eoi_workaround(void)
> INTEL_FAM6_MODEL(0x2f),
> { }
> };
> + /*
> + * Errata BDX99, CLX30, SKX100, CFW125, BDF104, BDH85, BDM135, KWB131:
> + * A Pending Fixed Interrupt May Be Dispatched Before an Interrupt of
> + * The Same Priority Completes.
> + *
> + * Resuming from C6 Sleep-State, with Fixed Interrupts of the same
> + * priority queued (in the corresponding bits of the IRR and ISR APIC
> + * registers), the processor may dispatch the second interrupt (from
> + * the IRR bit) before the first interrupt has completed and written to
> + * the EOI register, causing the first interrupt to never complete.
> + */
> + const static struct x86_cpu_id isr_errata[] = {
Same nit as for patch 1 here.
Jan
next prev parent reply other threads:[~2020-05-18 15:05 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-15 13:58 [PATCH v3 0/2] x86/idle: fix for Intel ISR errata Roger Pau Monne
2020-05-15 13:58 ` [PATCH v3 1/2] x86/idle: rework C6 EOI workaround Roger Pau Monne
2020-05-18 14:48 ` Jan Beulich
2020-05-15 13:58 ` [PATCH v3 2/2] x86/idle: prevent entering C6 with in service interrupts on Intel Roger Pau Monne
2020-05-18 15:05 ` Jan Beulich [this message]
2020-05-18 15:45 ` Roger Pau Monné
2020-05-18 15:47 ` Jan Beulich
2020-05-20 18:38 ` Andrew Cooper
2020-05-20 21:30 ` Andrew Cooper
2020-05-21 8:45 ` Roger Pau Monné
2020-05-21 16:27 ` Andrew Cooper
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