From: Jerome Brunet <jbrunet@baylibre.com> To: Neil Armstrong <narmstrong@baylibre.com>, Carlo Caione <carlo@caione.org>, Kevin Hilman <khilman@baylibre.com> Cc: Jerome Brunet <jbrunet@baylibre.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/7] clk: meson: add clk-phase clock driver Date: Wed, 25 Apr 2018 18:32:59 +0200 [thread overview] Message-ID: <20180425163304.10852-3-jbrunet@baylibre.com> (raw) In-Reply-To: <20180425163304.10852-1-jbrunet@baylibre.com> Add a driver based meson clk-regmap to control clock phase on amlogic SoCs Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- drivers/clk/meson/Makefile | 1 + drivers/clk/meson/clk-phase.c | 63 +++++++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/clkc.h | 8 ++++++ 3 files changed, 72 insertions(+) create mode 100644 drivers/clk/meson/clk-phase.c diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index ffee82e60b7a..352fb848c406 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o +obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase.o obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o obj-$(CONFIG_COMMON_CLK_AXG) += axg.o diff --git a/drivers/clk/meson/clk-phase.c b/drivers/clk/meson/clk-phase.c new file mode 100644 index 000000000000..96e70497ef1b --- /dev/null +++ b/drivers/clk/meson/clk-phase.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 BayLibre, SAS. + * Author: Jerome Brunet <jbrunet@baylibre.com> + */ + +#include <linux/clk-provider.h> +#include "clkc.h" + +#define phase_step(_width) (360 / (1 << (_width))) + +static inline struct meson_clk_phase_data * +meson_clk_phase_data(struct clk_regmap *clk) +{ + return (struct meson_clk_phase_data *)clk->data; +} + +int meson_clk_degrees_from_val(unsigned int val, unsigned int width) +{ + return phase_step(width) * val; +} +EXPORT_SYMBOL_GPL(meson_clk_degrees_from_val); + +unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width) +{ + unsigned int val = DIV_ROUND_CLOSEST(degrees, phase_step(width)); + + /* + * This last calculation is here for cases when degrees is rounded + * to 360, in which case val == (1 << width). + */ + return val % (1 << width); +} +EXPORT_SYMBOL_GPL(meson_clk_degrees_to_val); + +static int meson_clk_phase_get_phase(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); + unsigned int val; + + val = meson_parm_read(clk->map, &phase->ph); + + return meson_clk_degrees_from_val(val, phase->ph.width); +} + +static int meson_clk_phase_set_phase(struct clk_hw *hw, int degrees) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); + unsigned int val; + + val = meson_clk_degrees_to_val(degrees, phase->ph.width); + meson_parm_write(clk->map, &phase->ph, val); + + return 0; +} + +const struct clk_ops meson_clk_phase_ops = { + .get_phase = meson_clk_phase_get_phase, + .set_phase = meson_clk_phase_set_phase, +}; +EXPORT_SYMBOL_GPL(meson_clk_phase_ops); diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 8fe73c4edca8..9a17d6705e0a 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -104,6 +104,13 @@ struct meson_clk_audio_div_data { u8 flags; }; +struct meson_clk_phase_data { + struct parm ph; +}; + +int meson_clk_degrees_from_val(unsigned int val, unsigned int width); +unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width); + #define MESON_GATE(_name, _reg, _bit) \ struct clk_regmap _name = { \ .data = &(struct clk_regmap_gate_data){ \ @@ -127,5 +134,6 @@ extern const struct clk_ops meson_clk_mpll_ro_ops; extern const struct clk_ops meson_clk_mpll_ops; extern const struct clk_ops meson_clk_audio_divider_ro_ops; extern const struct clk_ops meson_clk_audio_divider_ops; +extern const struct clk_ops meson_clk_phase_ops; #endif /* __CLKC_H */ -- 2.14.3
WARNING: multiple messages have this Message-ID (diff)
From: jbrunet@baylibre.com (Jerome Brunet) To: linus-amlogic@lists.infradead.org Subject: [PATCH 2/7] clk: meson: add clk-phase clock driver Date: Wed, 25 Apr 2018 18:32:59 +0200 [thread overview] Message-ID: <20180425163304.10852-3-jbrunet@baylibre.com> (raw) In-Reply-To: <20180425163304.10852-1-jbrunet@baylibre.com> Add a driver based meson clk-regmap to control clock phase on amlogic SoCs Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- drivers/clk/meson/Makefile | 1 + drivers/clk/meson/clk-phase.c | 63 +++++++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/clkc.h | 8 ++++++ 3 files changed, 72 insertions(+) create mode 100644 drivers/clk/meson/clk-phase.c diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index ffee82e60b7a..352fb848c406 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o +obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase.o obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o obj-$(CONFIG_COMMON_CLK_AXG) += axg.o diff --git a/drivers/clk/meson/clk-phase.c b/drivers/clk/meson/clk-phase.c new file mode 100644 index 000000000000..96e70497ef1b --- /dev/null +++ b/drivers/clk/meson/clk-phase.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 BayLibre, SAS. + * Author: Jerome Brunet <jbrunet@baylibre.com> + */ + +#include <linux/clk-provider.h> +#include "clkc.h" + +#define phase_step(_width) (360 / (1 << (_width))) + +static inline struct meson_clk_phase_data * +meson_clk_phase_data(struct clk_regmap *clk) +{ + return (struct meson_clk_phase_data *)clk->data; +} + +int meson_clk_degrees_from_val(unsigned int val, unsigned int width) +{ + return phase_step(width) * val; +} +EXPORT_SYMBOL_GPL(meson_clk_degrees_from_val); + +unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width) +{ + unsigned int val = DIV_ROUND_CLOSEST(degrees, phase_step(width)); + + /* + * This last calculation is here for cases when degrees is rounded + * to 360, in which case val == (1 << width). + */ + return val % (1 << width); +} +EXPORT_SYMBOL_GPL(meson_clk_degrees_to_val); + +static int meson_clk_phase_get_phase(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); + unsigned int val; + + val = meson_parm_read(clk->map, &phase->ph); + + return meson_clk_degrees_from_val(val, phase->ph.width); +} + +static int meson_clk_phase_set_phase(struct clk_hw *hw, int degrees) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); + unsigned int val; + + val = meson_clk_degrees_to_val(degrees, phase->ph.width); + meson_parm_write(clk->map, &phase->ph, val); + + return 0; +} + +const struct clk_ops meson_clk_phase_ops = { + .get_phase = meson_clk_phase_get_phase, + .set_phase = meson_clk_phase_set_phase, +}; +EXPORT_SYMBOL_GPL(meson_clk_phase_ops); diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 8fe73c4edca8..9a17d6705e0a 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -104,6 +104,13 @@ struct meson_clk_audio_div_data { u8 flags; }; +struct meson_clk_phase_data { + struct parm ph; +}; + +int meson_clk_degrees_from_val(unsigned int val, unsigned int width); +unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width); + #define MESON_GATE(_name, _reg, _bit) \ struct clk_regmap _name = { \ .data = &(struct clk_regmap_gate_data){ \ @@ -127,5 +134,6 @@ extern const struct clk_ops meson_clk_mpll_ro_ops; extern const struct clk_ops meson_clk_mpll_ops; extern const struct clk_ops meson_clk_audio_divider_ro_ops; extern const struct clk_ops meson_clk_audio_divider_ops; +extern const struct clk_ops meson_clk_phase_ops; #endif /* __CLKC_H */ -- 2.14.3
next prev parent reply other threads:[~2018-04-25 16:33 UTC|newest] Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-04-25 16:32 [PATCH 0/7] clk: meson: axg: add audio clock controller support Jerome Brunet 2018-04-25 16:32 ` Jerome Brunet 2018-04-25 16:32 ` [PATCH 1/7] clk: meson: clean-up meson clock configuration Jerome Brunet 2018-04-25 16:32 ` Jerome Brunet 2018-04-26 8:46 ` Neil Armstrong 2018-04-26 8:46 ` Neil Armstrong 2018-04-25 16:32 ` Jerome Brunet [this message] 2018-04-25 16:32 ` [PATCH 2/7] clk: meson: add clk-phase clock driver Jerome Brunet 2018-04-26 8:46 ` Neil Armstrong 2018-04-26 8:46 ` Neil Armstrong 2018-04-25 16:33 ` [PATCH 3/7] clk: meson: add triple phase " Jerome Brunet 2018-04-25 16:33 ` Jerome Brunet 2018-04-26 8:47 ` Neil Armstrong 2018-04-26 8:47 ` Neil Armstrong 2018-04-26 8:50 ` Neil Armstrong 2018-04-26 8:50 ` Neil Armstrong 2018-04-25 16:33 ` [PATCH 4/7] clk: meson: add axg audio sclk divider driver Jerome Brunet 2018-04-25 16:33 ` Jerome Brunet 2018-04-26 8:47 ` Neil Armstrong 2018-04-26 8:47 ` Neil Armstrong 2018-04-25 16:33 ` [PATCH 5/7] clk: meson: axg: export audio clock controller id bindings Jerome Brunet 2018-04-25 16:33 ` Jerome Brunet 2018-04-26 8:48 ` Neil Armstrong 2018-04-26 8:48 ` Neil Armstrong 2018-05-01 14:31 ` Rob Herring 2018-05-01 14:31 ` Rob Herring 2018-04-25 16:33 ` [PATCH 6/7] clk: meson: axg: document bindings for the audio clock controller Jerome Brunet 2018-04-25 16:33 ` Jerome Brunet 2018-05-01 14:37 ` Rob Herring 2018-05-01 14:37 ` Rob Herring 2018-05-14 14:16 ` Jerome Brunet 2018-05-14 14:16 ` Jerome Brunet 2018-05-14 14:16 ` Jerome Brunet 2018-04-25 16:33 ` [PATCH 7/7] clk: meson: axg: add the audio clock controller driver Jerome Brunet 2018-04-25 16:33 ` Jerome Brunet 2018-04-26 8:49 ` Neil Armstrong 2018-04-26 8:49 ` Neil Armstrong 2018-05-15 23:41 ` Stephen Boyd 2018-05-15 23:41 ` Stephen Boyd 2018-05-15 23:41 ` Stephen Boyd 2018-04-27 1:13 ` kbuild test robot 2018-04-27 1:13 ` kbuild test robot 2018-04-27 1:13 ` kbuild test robot
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20180425163304.10852-3-jbrunet@baylibre.com \ --to=jbrunet@baylibre.com \ --cc=carlo@caione.org \ --cc=devicetree@vger.kernel.org \ --cc=khilman@baylibre.com \ --cc=linux-amlogic@lists.infradead.org \ --cc=linux-clk@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=mturquette@baylibre.com \ --cc=narmstrong@baylibre.com \ --cc=sboyd@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.