From: Jerome Brunet <jbrunet@baylibre.com> To: Neil Armstrong <narmstrong@baylibre.com>, Carlo Caione <carlo@caione.org>, Kevin Hilman <khilman@baylibre.com> Cc: Jerome Brunet <jbrunet@baylibre.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/7] clk: meson: axg: document bindings for the audio clock controller Date: Wed, 25 Apr 2018 18:33:03 +0200 [thread overview] Message-ID: <20180425163304.10852-7-jbrunet@baylibre.com> (raw) In-Reply-To: <20180425163304.10852-1-jbrunet@baylibre.com> Add documentation for the device tree bindings of the audio clock controller of the A113 based SoCs Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- .../bindings/clock/amlogic,axg-audio-clkc.txt | 56 ++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt new file mode 100644 index 000000000000..1b989ceda567 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt @@ -0,0 +1,56 @@ +* Amlogic AXG Audio Clock Controllers + +The Amlogic AXG audio clock controller generates and supplies clock to the +other elements of the audio subsystem, such as fifos, i2s, spdif and pdm +devices. + +Required Properties: + +- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D +- reg : physical base address of the clock controller and length of + memory mapped region. +- clocks : a list of phandle + clock-specifier pairs for the clocks listed + in clock-names. +- clock-names : must contain the following: + * "pclk" - Main peripheral bus clock + may contain the following: + * "mst_in[0-7]" - 8 input plls to generate clock signals + * "slv_sclk[0-9]" - 10 slave bit clocks provided by external + components. + * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external + components. +- reset : phandle of the internal reset line +- #clock-cells : should be 1. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be +used in device tree sources. + +Example: + +clkc_audio: clock-controller { + compatible = "amlogic,axg-audio-clkc"; + reg = <0x0 0x0 0x0 0xb4>; + #clock-cells = <1>; + + clocks = <&clkc CLKID_AUDIO>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL3>, + <&clkc CLKID_HIFI_PLL>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_GP0_PLL>; + clock-names = "pclk", + "mst_in0", + "mst_in1", + "mst_in2", + "mst_in3", + "mst_in4", + "mst_in5", + "mst_in6", + "mst_in7"; + resets = <&reset RESET_AUDIO>; +}; -- 2.14.3
WARNING: multiple messages have this Message-ID (diff)
From: jbrunet@baylibre.com (Jerome Brunet) To: linus-amlogic@lists.infradead.org Subject: [PATCH 6/7] clk: meson: axg: document bindings for the audio clock controller Date: Wed, 25 Apr 2018 18:33:03 +0200 [thread overview] Message-ID: <20180425163304.10852-7-jbrunet@baylibre.com> (raw) In-Reply-To: <20180425163304.10852-1-jbrunet@baylibre.com> Add documentation for the device tree bindings of the audio clock controller of the A113 based SoCs Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- .../bindings/clock/amlogic,axg-audio-clkc.txt | 56 ++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt new file mode 100644 index 000000000000..1b989ceda567 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt @@ -0,0 +1,56 @@ +* Amlogic AXG Audio Clock Controllers + +The Amlogic AXG audio clock controller generates and supplies clock to the +other elements of the audio subsystem, such as fifos, i2s, spdif and pdm +devices. + +Required Properties: + +- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D +- reg : physical base address of the clock controller and length of + memory mapped region. +- clocks : a list of phandle + clock-specifier pairs for the clocks listed + in clock-names. +- clock-names : must contain the following: + * "pclk" - Main peripheral bus clock + may contain the following: + * "mst_in[0-7]" - 8 input plls to generate clock signals + * "slv_sclk[0-9]" - 10 slave bit clocks provided by external + components. + * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external + components. +- reset : phandle of the internal reset line +- #clock-cells : should be 1. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be +used in device tree sources. + +Example: + +clkc_audio: clock-controller { + compatible = "amlogic,axg-audio-clkc"; + reg = <0x0 0x0 0x0 0xb4>; + #clock-cells = <1>; + + clocks = <&clkc CLKID_AUDIO>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL3>, + <&clkc CLKID_HIFI_PLL>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_GP0_PLL>; + clock-names = "pclk", + "mst_in0", + "mst_in1", + "mst_in2", + "mst_in3", + "mst_in4", + "mst_in5", + "mst_in6", + "mst_in7"; + resets = <&reset RESET_AUDIO>; +}; -- 2.14.3
next prev parent reply other threads:[~2018-04-25 16:34 UTC|newest] Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-04-25 16:32 [PATCH 0/7] clk: meson: axg: add audio clock controller support Jerome Brunet 2018-04-25 16:32 ` Jerome Brunet 2018-04-25 16:32 ` [PATCH 1/7] clk: meson: clean-up meson clock configuration Jerome Brunet 2018-04-25 16:32 ` Jerome Brunet 2018-04-26 8:46 ` Neil Armstrong 2018-04-26 8:46 ` Neil Armstrong 2018-04-25 16:32 ` [PATCH 2/7] clk: meson: add clk-phase clock driver Jerome Brunet 2018-04-25 16:32 ` Jerome Brunet 2018-04-26 8:46 ` Neil Armstrong 2018-04-26 8:46 ` Neil Armstrong 2018-04-25 16:33 ` [PATCH 3/7] clk: meson: add triple phase " Jerome Brunet 2018-04-25 16:33 ` Jerome Brunet 2018-04-26 8:47 ` Neil Armstrong 2018-04-26 8:47 ` Neil Armstrong 2018-04-26 8:50 ` Neil Armstrong 2018-04-26 8:50 ` Neil Armstrong 2018-04-25 16:33 ` [PATCH 4/7] clk: meson: add axg audio sclk divider driver Jerome Brunet 2018-04-25 16:33 ` Jerome Brunet 2018-04-26 8:47 ` Neil Armstrong 2018-04-26 8:47 ` Neil Armstrong 2018-04-25 16:33 ` [PATCH 5/7] clk: meson: axg: export audio clock controller id bindings Jerome Brunet 2018-04-25 16:33 ` Jerome Brunet 2018-04-26 8:48 ` Neil Armstrong 2018-04-26 8:48 ` Neil Armstrong 2018-05-01 14:31 ` Rob Herring 2018-05-01 14:31 ` Rob Herring 2018-04-25 16:33 ` Jerome Brunet [this message] 2018-04-25 16:33 ` [PATCH 6/7] clk: meson: axg: document bindings for the audio clock controller Jerome Brunet 2018-05-01 14:37 ` Rob Herring 2018-05-01 14:37 ` Rob Herring 2018-05-14 14:16 ` Jerome Brunet 2018-05-14 14:16 ` Jerome Brunet 2018-05-14 14:16 ` Jerome Brunet 2018-04-25 16:33 ` [PATCH 7/7] clk: meson: axg: add the audio clock controller driver Jerome Brunet 2018-04-25 16:33 ` Jerome Brunet 2018-04-26 8:49 ` Neil Armstrong 2018-04-26 8:49 ` Neil Armstrong 2018-05-15 23:41 ` Stephen Boyd 2018-05-15 23:41 ` Stephen Boyd 2018-05-15 23:41 ` Stephen Boyd 2018-04-27 1:13 ` kbuild test robot 2018-04-27 1:13 ` kbuild test robot 2018-04-27 1:13 ` kbuild test robot
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