From: Mark Brown <broonie@kernel.org>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: John Garry <john.garry@huawei.com>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
tudor.ambarus@microchip.com,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
chenxiang66@hisilicon.com, Linuxarm <linuxarm@huawei.com>,
linux-spi <linux-spi@vger.kernel.org>,
Marek Vasut <marek.vasut@gmail.com>,
"open list:MEMORY TECHNOLOGY..." <linux-mtd@lists.infradead.org>,
Jiancheng Xue <xuejiancheng@hisilicon.com>,
fengsheng5@huawei.com,
Mika Westerberg <mika.westerberg@linux.intel.com>,
wanghuiqiang <wanghuiqiang@huawei.com>,
liusimin4@huawei.com
Subject: Re: [PATCH v2 2/3] spi: Add HiSilicon v3xx SPI NOR flash controller driver
Date: Mon, 13 Jan 2020 14:27:54 +0000 [thread overview]
Message-ID: <20200113142754.GL3897@sirena.org.uk> (raw)
In-Reply-To: <CAHp75VfepiiVFLLmCwdBS0Z6tmR+XKBaOLg1qPPuz1McLjS=4Q@mail.gmail.com>
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On Mon, Jan 13, 2020 at 04:17:32PM +0200, Andy Shevchenko wrote:
> On Mon, Jan 13, 2020 at 4:07 PM Mark Brown <broonie@kernel.org> wrote:
> > On Mon, Jan 13, 2020 at 01:01:06PM +0000, John Garry wrote:
> > > On 13/01/2020 11:42, Mark Brown wrote:
> > > > The idiomatic approach appears to be for individual board vendors
> > > > to allocate IDs, you do end up with multiple IDs from multiple
> > > > vendors for the same thing.
> > > But I am not sure how appropriate that same approach would be for some 3rd
> > > party memory part which we're simply wiring up on our board. Maybe it is.
> > It seems to be quite common for Intel reference designs to assign
> > Intel IDs to non-Intel parts on the board (which is where I
> > became aware of this practice).
> Basically vendor of component in question is responsible for ID, but
> it seems they simple don't care.
AFAICT a lot of the time it seems to be that whoever is writing
the software ends up assigning an ID, that may not be the silicon
vendor.
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WARNING: multiple messages have this Message-ID (diff)
From: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: Andy Shevchenko
<andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>,
Andy Shevchenko
<andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>,
tudor.ambarus-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org,
Linux Kernel Mailing List
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
chenxiang66-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org,
Linuxarm <linuxarm-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>,
linux-spi <linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
Marek Vasut <marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
"open list:MEMORY TECHNOLOGY..."
<linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
Jiancheng Xue
<xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>,
fengsheng5-hv44wF8Li93QT0dZR+AlfA@public.gmane.org,
Mika Westerberg
<mika.westerberg-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>,
wanghuiqiang
<wanghuiqiang-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>,
liusimin4-hv44wF8Li93QT0dZR+AlfA@public.gmane.org
Subject: Re: [PATCH v2 2/3] spi: Add HiSilicon v3xx SPI NOR flash controller driver
Date: Mon, 13 Jan 2020 14:27:54 +0000 [thread overview]
Message-ID: <20200113142754.GL3897@sirena.org.uk> (raw)
In-Reply-To: <CAHp75VfepiiVFLLmCwdBS0Z6tmR+XKBaOLg1qPPuz1McLjS=4Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
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On Mon, Jan 13, 2020 at 04:17:32PM +0200, Andy Shevchenko wrote:
> On Mon, Jan 13, 2020 at 4:07 PM Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> > On Mon, Jan 13, 2020 at 01:01:06PM +0000, John Garry wrote:
> > > On 13/01/2020 11:42, Mark Brown wrote:
> > > > The idiomatic approach appears to be for individual board vendors
> > > > to allocate IDs, you do end up with multiple IDs from multiple
> > > > vendors for the same thing.
> > > But I am not sure how appropriate that same approach would be for some 3rd
> > > party memory part which we're simply wiring up on our board. Maybe it is.
> > It seems to be quite common for Intel reference designs to assign
> > Intel IDs to non-Intel parts on the board (which is where I
> > became aware of this practice).
> Basically vendor of component in question is responsible for ID, but
> it seems they simple don't care.
AFAICT a lot of the time it seems to be that whoever is writing
the software ends up assigning an ID, that may not be the silicon
vendor.
[-- Attachment #2: signature.asc --]
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WARNING: multiple messages have this Message-ID (diff)
From: Mark Brown <broonie@kernel.org>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: liusimin4@huawei.com, chenxiang66@hisilicon.com,
John Garry <john.garry@huawei.com>,
linux-spi <linux-spi@vger.kernel.org>,
Linuxarm <linuxarm@huawei.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Marek Vasut <marek.vasut@gmail.com>,
"open list:MEMORY TECHNOLOGY..." <linux-mtd@lists.infradead.org>,
tudor.ambarus@microchip.com,
Jiancheng Xue <xuejiancheng@hisilicon.com>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
wanghuiqiang <wanghuiqiang@huawei.com>,
fengsheng5@huawei.com
Subject: Re: [PATCH v2 2/3] spi: Add HiSilicon v3xx SPI NOR flash controller driver
Date: Mon, 13 Jan 2020 14:27:54 +0000 [thread overview]
Message-ID: <20200113142754.GL3897@sirena.org.uk> (raw)
In-Reply-To: <CAHp75VfepiiVFLLmCwdBS0Z6tmR+XKBaOLg1qPPuz1McLjS=4Q@mail.gmail.com>
[-- Attachment #1.1: Type: text/plain, Size: 1008 bytes --]
On Mon, Jan 13, 2020 at 04:17:32PM +0200, Andy Shevchenko wrote:
> On Mon, Jan 13, 2020 at 4:07 PM Mark Brown <broonie@kernel.org> wrote:
> > On Mon, Jan 13, 2020 at 01:01:06PM +0000, John Garry wrote:
> > > On 13/01/2020 11:42, Mark Brown wrote:
> > > > The idiomatic approach appears to be for individual board vendors
> > > > to allocate IDs, you do end up with multiple IDs from multiple
> > > > vendors for the same thing.
> > > But I am not sure how appropriate that same approach would be for some 3rd
> > > party memory part which we're simply wiring up on our board. Maybe it is.
> > It seems to be quite common for Intel reference designs to assign
> > Intel IDs to non-Intel parts on the board (which is where I
> > became aware of this practice).
> Basically vendor of component in question is responsible for ID, but
> it seems they simple don't care.
AFAICT a lot of the time it seems to be that whoever is writing
the software ends up assigning an ID, that may not be the silicon
vendor.
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______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2020-01-13 14:28 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-09 14:08 [PATCH v2 0/3] HiSilicon v3xx SFC driver John Garry
2019-12-09 14:08 ` John Garry
2019-12-09 14:08 ` [PATCH v2 1/3] mtd: spi-nor: hisi-sfc: Try to provide some clarity on which SFC we are John Garry
2019-12-09 14:08 ` John Garry
2020-01-16 11:03 ` Tudor.Ambarus
2020-01-16 11:03 ` Tudor.Ambarus
2019-12-09 14:08 ` [PATCH v2 2/3] spi: Add HiSilicon v3xx SPI NOR flash controller driver John Garry
2019-12-09 14:08 ` John Garry
2020-01-09 15:54 ` John Garry
2020-01-09 15:54 ` John Garry
2020-01-09 21:28 ` Mark Brown
2020-01-09 21:28 ` Mark Brown
2020-01-10 11:55 ` John Garry
2020-01-10 11:55 ` John Garry
2020-01-10 11:55 ` John Garry
2020-01-10 14:07 ` Mark Brown
2020-01-10 14:07 ` Mark Brown
2020-01-10 14:07 ` Mark Brown
2020-01-10 14:58 ` John Garry
2020-01-10 14:58 ` John Garry
2020-01-10 15:12 ` Mark Brown
2020-01-10 15:12 ` Mark Brown
2020-01-10 16:09 ` John Garry
2020-01-10 16:09 ` John Garry
2020-01-10 19:31 ` Andy Shevchenko
2020-01-10 19:31 ` Andy Shevchenko
2020-01-10 19:31 ` Andy Shevchenko
2020-01-13 10:09 ` John Garry
2020-01-13 10:09 ` John Garry
2020-01-13 11:42 ` Mark Brown
2020-01-13 11:42 ` Mark Brown
2020-01-13 13:01 ` John Garry
2020-01-13 13:01 ` John Garry
2020-01-13 14:06 ` Mark Brown
2020-01-13 14:06 ` Mark Brown
2020-01-13 14:17 ` Andy Shevchenko
2020-01-13 14:17 ` Andy Shevchenko
2020-01-13 14:17 ` Andy Shevchenko
2020-01-13 14:27 ` Mark Brown [this message]
2020-01-13 14:27 ` Mark Brown
2020-01-13 14:27 ` Mark Brown
2020-01-13 14:34 ` Andy Shevchenko
2020-01-13 14:34 ` Andy Shevchenko
2020-01-13 14:34 ` Andy Shevchenko
2020-01-31 10:08 ` John Garry
2020-01-31 10:08 ` John Garry
2020-01-31 11:39 ` Andy Shevchenko
2020-01-31 11:39 ` Andy Shevchenko
2020-01-31 11:39 ` Andy Shevchenko
2020-01-31 12:03 ` John Garry
2020-01-31 12:03 ` John Garry
2020-01-31 12:03 ` John Garry
2020-01-31 15:46 ` Andy Shevchenko
2020-01-31 15:46 ` Andy Shevchenko
2020-01-31 15:46 ` Andy Shevchenko
2020-01-31 16:26 ` John Garry
2020-01-31 16:26 ` John Garry
2020-01-31 16:26 ` John Garry
2020-02-01 11:34 ` Mark Brown
2020-02-01 11:34 ` Mark Brown
2020-02-01 11:32 ` Mark Brown
2020-02-01 11:32 ` Mark Brown
2020-01-10 19:59 ` Applied "spi: Add HiSilicon v3xx SPI NOR flash controller driver" to the spi tree Mark Brown
2020-01-10 19:59 ` Mark Brown
2020-01-10 19:59 ` Mark Brown
2019-12-09 14:08 ` [PATCH v2 3/3] MAINTAINERS: Add a maintainer for the HiSilicon v3xx SFC driver John Garry
2019-12-09 14:08 ` John Garry
2020-01-10 19:59 ` Applied "MAINTAINERS: Add a maintainer for the HiSilicon v3xx SFC driver" to the spi tree Mark Brown
2020-01-10 19:59 ` Mark Brown
2020-01-10 19:59 ` Mark Brown
2019-12-16 14:52 ` [PATCH v2 0/3] HiSilicon v3xx SFC driver John Garry
2019-12-16 14:52 ` John Garry
2019-12-16 14:56 ` Mark Brown
2019-12-16 14:56 ` Mark Brown
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