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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, maz@kernel.org,
	catalin.marinas@arm.com, mark.rutland@arm.com,
	james.morse@arm.com, anshuman.khandual@arm.com,
	leo.yan@linaro.org, mike.leach@linaro.org,
	mathieu.poirier@linaro.org, will@kernel.org,
	lcherian@marvell.com, coresight@lists.linaro.org,
	Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v2 06/17] coresight: trbe: Allow driver to choose a different alignment
Date: Tue, 21 Sep 2021 14:41:10 +0100	[thread overview]
Message-ID: <20210921134121.2423546-7-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20210921134121.2423546-1-suzuki.poulose@arm.com>

The TRBE hardware mandates a minimum alignment for the TRBPTR_EL1,
advertised via the TRBIDR_EL1. This is used by the driver to
align the buffer write head. This patch allows the driver to
choose a different alignment from that of the hardware, by
decoupling the alignment tracking. This will be useful for
working around errata.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-trbe.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
index 27616eac24ba..f569010c672b 100644
--- a/drivers/hwtracing/coresight/coresight-trbe.c
+++ b/drivers/hwtracing/coresight/coresight-trbe.c
@@ -92,7 +92,8 @@ static unsigned long trbe_errata_cpucaps[TRBE_ERRATA_MAX] = {
 /*
  * struct trbe_cpudata: TRBE instance specific data
  * @trbe_flag		- TRBE dirty/access flag support
- * @tbre_align		- Actual TRBE alignment required for TRBPTR_EL1.
+ * @trbe_hw_align	- Actual TRBE alignment required for TRBPTR_EL1.
+ * @trbe_align		- Software alignment used for the TRBPTR_EL1,
  * @cpu			- CPU this TRBE belongs to.
  * @mode		- Mode of current operation. (perf/disabled)
  * @drvdata		- TRBE specific drvdata
@@ -100,6 +101,7 @@ static unsigned long trbe_errata_cpucaps[TRBE_ERRATA_MAX] = {
  */
 struct trbe_cpudata {
 	bool trbe_flag;
+	u64 trbe_hw_align;
 	u64 trbe_align;
 	int cpu;
 	enum cs_mode mode;
@@ -903,7 +905,7 @@ static ssize_t align_show(struct device *dev, struct device_attribute *attr, cha
 {
 	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
 
-	return sprintf(buf, "%llx\n", cpudata->trbe_align);
+	return sprintf(buf, "%llx\n", cpudata->trbe_hw_align);
 }
 static DEVICE_ATTR_RO(align);
 
@@ -991,13 +993,14 @@ static void arm_trbe_probe_cpu(void *info)
 		goto cpu_clear;
 	}
 
-	cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr);
-	if (cpudata->trbe_align > SZ_2K) {
+	cpudata->trbe_hw_align = 1ULL << get_trbe_address_align(trbidr);
+	if (cpudata->trbe_hw_align > SZ_2K) {
 		pr_err("Unsupported alignment on cpu %d\n", cpu);
 		goto cpu_clear;
 	}
 
 	trbe_check_errata(cpudata);
+	cpudata->trbe_align = cpudata->trbe_hw_align;
 	cpudata->trbe_flag = get_trbe_flag_update(trbidr);
 	cpudata->cpu = cpu;
 	cpudata->drvdata = drvdata;
-- 
2.24.1


WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, maz@kernel.org,
	catalin.marinas@arm.com, mark.rutland@arm.com,
	james.morse@arm.com, anshuman.khandual@arm.com,
	leo.yan@linaro.org, mike.leach@linaro.org,
	mathieu.poirier@linaro.org, will@kernel.org,
	lcherian@marvell.com, coresight@lists.linaro.org,
	Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v2 06/17] coresight: trbe: Allow driver to choose a different alignment
Date: Tue, 21 Sep 2021 14:41:10 +0100	[thread overview]
Message-ID: <20210921134121.2423546-7-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20210921134121.2423546-1-suzuki.poulose@arm.com>

The TRBE hardware mandates a minimum alignment for the TRBPTR_EL1,
advertised via the TRBIDR_EL1. This is used by the driver to
align the buffer write head. This patch allows the driver to
choose a different alignment from that of the hardware, by
decoupling the alignment tracking. This will be useful for
working around errata.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-trbe.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
index 27616eac24ba..f569010c672b 100644
--- a/drivers/hwtracing/coresight/coresight-trbe.c
+++ b/drivers/hwtracing/coresight/coresight-trbe.c
@@ -92,7 +92,8 @@ static unsigned long trbe_errata_cpucaps[TRBE_ERRATA_MAX] = {
 /*
  * struct trbe_cpudata: TRBE instance specific data
  * @trbe_flag		- TRBE dirty/access flag support
- * @tbre_align		- Actual TRBE alignment required for TRBPTR_EL1.
+ * @trbe_hw_align	- Actual TRBE alignment required for TRBPTR_EL1.
+ * @trbe_align		- Software alignment used for the TRBPTR_EL1,
  * @cpu			- CPU this TRBE belongs to.
  * @mode		- Mode of current operation. (perf/disabled)
  * @drvdata		- TRBE specific drvdata
@@ -100,6 +101,7 @@ static unsigned long trbe_errata_cpucaps[TRBE_ERRATA_MAX] = {
  */
 struct trbe_cpudata {
 	bool trbe_flag;
+	u64 trbe_hw_align;
 	u64 trbe_align;
 	int cpu;
 	enum cs_mode mode;
@@ -903,7 +905,7 @@ static ssize_t align_show(struct device *dev, struct device_attribute *attr, cha
 {
 	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
 
-	return sprintf(buf, "%llx\n", cpudata->trbe_align);
+	return sprintf(buf, "%llx\n", cpudata->trbe_hw_align);
 }
 static DEVICE_ATTR_RO(align);
 
@@ -991,13 +993,14 @@ static void arm_trbe_probe_cpu(void *info)
 		goto cpu_clear;
 	}
 
-	cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr);
-	if (cpudata->trbe_align > SZ_2K) {
+	cpudata->trbe_hw_align = 1ULL << get_trbe_address_align(trbidr);
+	if (cpudata->trbe_hw_align > SZ_2K) {
 		pr_err("Unsupported alignment on cpu %d\n", cpu);
 		goto cpu_clear;
 	}
 
 	trbe_check_errata(cpudata);
+	cpudata->trbe_align = cpudata->trbe_hw_align;
 	cpudata->trbe_flag = get_trbe_flag_update(trbidr);
 	cpudata->cpu = cpu;
 	cpudata->drvdata = drvdata;
-- 
2.24.1


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  parent reply	other threads:[~2021-09-21 13:41 UTC|newest]

Thread overview: 124+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-21 13:41 [PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose
2021-09-21 13:41 ` Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 01/17] coresight: trbe: Fix incorrect access of the sink specific data Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22  5:41   ` Anshuman Khandual
2021-09-22  5:41     ` Anshuman Khandual
2021-09-30 17:57   ` Mathieu Poirier
2021-09-30 17:57     ` Mathieu Poirier
2021-09-21 13:41 ` [PATCH v2 02/17] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22  6:47   ` Anshuman Khandual
2021-09-22  6:47     ` Anshuman Khandual
2021-10-05 16:46   ` Mathieu Poirier
2021-10-05 16:46     ` Mathieu Poirier
2021-09-21 13:41 ` [PATCH v2 03/17] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-30 17:54   ` Mathieu Poirier
2021-09-30 17:54     ` Mathieu Poirier
2021-10-01  8:36     ` Suzuki K Poulose
2021-10-01  8:36       ` Suzuki K Poulose
2021-10-01 15:15       ` Mathieu Poirier
2021-10-01 15:15         ` Mathieu Poirier
2021-10-01 15:22         ` Suzuki K Poulose
2021-10-01 15:22           ` Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 04/17] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 05/17] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-21 13:41 ` Suzuki K Poulose [this message]
2021-09-21 13:41   ` [PATCH v2 06/17] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 07/17] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22  6:57   ` Anshuman Khandual
2021-09-22  6:57     ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 08/17] arm64: Add erratum detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 09/17] coresight: trbe: Workaround TRBE errata " Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-23  6:13   ` Anshuman Khandual
2021-09-23  6:13     ` Anshuman Khandual
2021-09-28 10:40     ` Suzuki K Poulose
2021-09-28 10:40       ` Suzuki K Poulose
2021-10-01  4:21       ` Anshuman Khandual
2021-10-01  4:21         ` Anshuman Khandual
2021-10-01 17:15   ` Mathieu Poirier
2021-10-01 17:15     ` Mathieu Poirier
2021-10-04  8:46     ` Suzuki K Poulose
2021-10-04  8:46       ` Suzuki K Poulose
2021-10-04 16:47       ` Mathieu Poirier
2021-10-04 16:47         ` Mathieu Poirier
2021-09-21 13:41 ` [PATCH v2 10/17] arm64: Enable workaround for TRBE " Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22  7:23   ` Anshuman Khandual
2021-09-22  7:23     ` Anshuman Khandual
2021-09-22  8:11     ` Suzuki K Poulose
2021-09-22  8:11       ` Suzuki K Poulose
2021-10-01  4:35       ` Anshuman Khandual
2021-10-01  4:35         ` Anshuman Khandual
2021-10-07 16:09   ` Catalin Marinas
2021-10-07 16:09     ` Catalin Marinas
2021-09-21 13:41 ` [PATCH v2 11/17] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22  7:39   ` Anshuman Khandual
2021-09-22  7:39     ` Anshuman Khandual
2021-09-22 12:03     ` Suzuki K Poulose
2021-09-22 12:03       ` Suzuki K Poulose
2021-10-01  4:38       ` Anshuman Khandual
2021-10-01  4:38         ` Anshuman Khandual
2021-10-07 16:10   ` Catalin Marinas
2021-10-07 16:10     ` Catalin Marinas
2021-09-21 13:41 ` [PATCH v2 12/17] coresight: trbe: Add a helper to fetch cpudata from perf handle Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22  7:59   ` Anshuman Khandual
2021-09-22  7:59     ` Anshuman Khandual
2021-10-04 17:42   ` Mathieu Poirier
2021-10-04 17:42     ` Mathieu Poirier
2021-10-05 22:35     ` Suzuki K Poulose
2021-10-05 22:35       ` Suzuki K Poulose
2021-10-06 17:15       ` Mathieu Poirier
2021-10-06 17:15         ` Mathieu Poirier
2021-10-07  9:18         ` Suzuki K Poulose
2021-10-07  9:18           ` Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 13/17] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22  9:51   ` Anshuman Khandual
2021-09-22  9:51     ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 14/17] coresight: trbe: Make sure we have enough space Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22  9:58   ` Anshuman Khandual
2021-09-22  9:58     ` Anshuman Khandual
2021-09-22 10:16     ` Suzuki K Poulose
2021-09-22 10:16       ` Suzuki K Poulose
2021-10-01  4:40       ` Anshuman Khandual
2021-10-01  4:40         ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 15/17] arm64: Add erratum detection for TRBE write to out-of-range Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22 10:59   ` Anshuman Khandual
2021-09-22 10:59     ` Anshuman Khandual
2021-10-07 16:10   ` Catalin Marinas
2021-10-07 16:10     ` Catalin Marinas
2021-09-21 13:41 ` [PATCH v2 16/17] coresight: trbe: Work around write to out of range Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-23  3:15   ` Anshuman Khandual
2021-09-23  3:15     ` Anshuman Khandual
2021-09-28 10:32     ` Suzuki K Poulose
2021-09-28 10:32       ` Suzuki K Poulose
2021-10-01  4:56       ` Anshuman Khandual
2021-10-01  4:56         ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 17/17] arm64: Advertise TRBE erratum workaround for write to out-of-range address Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22 11:03   ` Anshuman Khandual
2021-09-22 11:03     ` Anshuman Khandual
2021-10-07 16:11   ` Catalin Marinas
2021-10-07 16:11     ` Catalin Marinas
2021-10-05 17:04 ` [PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds Mathieu Poirier
2021-10-05 17:04   ` Mathieu Poirier
2021-10-08  7:32 ` Will Deacon
2021-10-08  7:32   ` Will Deacon
2021-10-08  9:25   ` Suzuki K Poulose
2021-10-08  9:25     ` Suzuki K Poulose
2021-10-08  9:52     ` Will Deacon
2021-10-08  9:52       ` Will Deacon
2021-10-08  9:57       ` Suzuki K Poulose
2021-10-08  9:57         ` Suzuki K Poulose

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