From: Anshuman Khandual <anshuman.khandual@arm.com> To: Suzuki K Poulose <suzuki.poulose@arm.com>, linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, maz@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, james.morse@arm.com, leo.yan@linaro.org, mike.leach@linaro.org, mathieu.poirier@linaro.org, will@kernel.org, lcherian@marvell.com, coresight@lists.linaro.org Subject: Re: [PATCH v2 10/17] arm64: Enable workaround for TRBE overwrite in FILL mode Date: Wed, 22 Sep 2021 12:53:00 +0530 [thread overview] Message-ID: <8b23470b-da5c-c624-dc98-d30ab7c1be5d@arm.com> (raw) In-Reply-To: <20210921134121.2423546-11-suzuki.poulose@arm.com> On 9/21/21 7:11 PM, Suzuki K Poulose wrote: > Now that we have the work around implmented in the TRBE > driver, add the Kconfig entries and document the errata. > > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Anshuman Khandual <anshuman.khandual@arm.com> > Cc: Mathieu Poirier <mathieu.poirier@linaro.org> > Cc: Mike Leach <mike.leach@linaro.org> > Cc: Leo Yan <leo.yan@linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> > --- > Documentation/arm64/silicon-errata.rst | 4 +++ > arch/arm64/Kconfig | 39 ++++++++++++++++++++++++++ > 2 files changed, 43 insertions(+) > > diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst > index d410a47ffa57..2f99229d993c 100644 > --- a/Documentation/arm64/silicon-errata.rst > +++ b/Documentation/arm64/silicon-errata.rst > @@ -92,12 +92,16 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-N1 | #1349291 | N/A | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | MMU-500 | #841119,826419 | N/A | > +----------------+-----------------+-----------------+-----------------------------+ > +----------------+-----------------+-----------------+-----------------------------+ > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 077f2ec4eeb2..eac4030322df 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -666,6 +666,45 @@ config ARM64_ERRATUM_1508412 > > If unsure, say Y. > > +config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE > + bool > + > +config ARM64_ERRATUM_2119858 > + bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode" > + default y > + depends on CORESIGHT_TRBE > + select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE > + help > + This option adds the workaround for ARM Cortex-A710 erratum 2119858. > + > + Affected Cortex-A710 cores could overwrite upto 3 cache lines of trace > + data at the base of the buffer (ponited by TRBASER_EL1) in FILL mode in > + the event of a WRAP event. > + > + Work around the issue by always making sure we move the TRBPTR_EL1 by > + 256bytes before enabling the buffer and filling the first 256bytes of > + the buffer with ETM ignore packets upon disabling. > + > + If unsure, say Y. > + > +config ARM64_ERRATUM_2139208 > + bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" > + default y > + depends on CORESIGHT_TRBE > + select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE > + help > + This option adds the workaround for ARM Neoverse-N2 erratum 2139208. > + > + Affected Neoverse-N2 cores could overwrite upto 3 cache lines of trace > + data at the base of the buffer (ponited by TRBASER_EL1) in FILL mode in s/ponited/pointed > + the event of a WRAP event. > + > + Work around the issue by always making sure we move the TRBPTR_EL1 by > + 256bytes before enabling the buffer and filling the first 256bytes of > + the buffer with ETM ignore packets upon disabling. > + > + If unsure, say Y. > + > config CAVIUM_ERRATUM_22375 > bool "Cavium erratum 22375, 24313" > default y > The real errata problem description for both these erratums are exactly the same. Rather a more generalized description should be included for the ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, which abstracts out the problem and a corresponding solution that is implemented in the driver. This should also help us reduce current redundancy. ---------------------------------------------------------------------- Affected cores could overwrite upto 3 cache lines of trace data at the base of the buffer (pointed by TRBASER_EL1) in FILL mode in the event of a WRAP event. Work around the issue by always making sure we move the TRBPTR_EL1 by 256bytes before enabling the buffer and filling the first 256bytes of the buffer with ETM ignore packets upon disabling. ----------------------------------------------------------------------
WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com> To: Suzuki K Poulose <suzuki.poulose@arm.com>, linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, maz@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, james.morse@arm.com, leo.yan@linaro.org, mike.leach@linaro.org, mathieu.poirier@linaro.org, will@kernel.org, lcherian@marvell.com, coresight@lists.linaro.org Subject: Re: [PATCH v2 10/17] arm64: Enable workaround for TRBE overwrite in FILL mode Date: Wed, 22 Sep 2021 12:53:00 +0530 [thread overview] Message-ID: <8b23470b-da5c-c624-dc98-d30ab7c1be5d@arm.com> (raw) In-Reply-To: <20210921134121.2423546-11-suzuki.poulose@arm.com> On 9/21/21 7:11 PM, Suzuki K Poulose wrote: > Now that we have the work around implmented in the TRBE > driver, add the Kconfig entries and document the errata. > > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Anshuman Khandual <anshuman.khandual@arm.com> > Cc: Mathieu Poirier <mathieu.poirier@linaro.org> > Cc: Mike Leach <mike.leach@linaro.org> > Cc: Leo Yan <leo.yan@linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> > --- > Documentation/arm64/silicon-errata.rst | 4 +++ > arch/arm64/Kconfig | 39 ++++++++++++++++++++++++++ > 2 files changed, 43 insertions(+) > > diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst > index d410a47ffa57..2f99229d993c 100644 > --- a/Documentation/arm64/silicon-errata.rst > +++ b/Documentation/arm64/silicon-errata.rst > @@ -92,12 +92,16 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-N1 | #1349291 | N/A | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | MMU-500 | #841119,826419 | N/A | > +----------------+-----------------+-----------------+-----------------------------+ > +----------------+-----------------+-----------------+-----------------------------+ > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 077f2ec4eeb2..eac4030322df 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -666,6 +666,45 @@ config ARM64_ERRATUM_1508412 > > If unsure, say Y. > > +config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE > + bool > + > +config ARM64_ERRATUM_2119858 > + bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode" > + default y > + depends on CORESIGHT_TRBE > + select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE > + help > + This option adds the workaround for ARM Cortex-A710 erratum 2119858. > + > + Affected Cortex-A710 cores could overwrite upto 3 cache lines of trace > + data at the base of the buffer (ponited by TRBASER_EL1) in FILL mode in > + the event of a WRAP event. > + > + Work around the issue by always making sure we move the TRBPTR_EL1 by > + 256bytes before enabling the buffer and filling the first 256bytes of > + the buffer with ETM ignore packets upon disabling. > + > + If unsure, say Y. > + > +config ARM64_ERRATUM_2139208 > + bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" > + default y > + depends on CORESIGHT_TRBE > + select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE > + help > + This option adds the workaround for ARM Neoverse-N2 erratum 2139208. > + > + Affected Neoverse-N2 cores could overwrite upto 3 cache lines of trace > + data at the base of the buffer (ponited by TRBASER_EL1) in FILL mode in s/ponited/pointed > + the event of a WRAP event. > + > + Work around the issue by always making sure we move the TRBPTR_EL1 by > + 256bytes before enabling the buffer and filling the first 256bytes of > + the buffer with ETM ignore packets upon disabling. > + > + If unsure, say Y. > + > config CAVIUM_ERRATUM_22375 > bool "Cavium erratum 22375, 24313" > default y > The real errata problem description for both these erratums are exactly the same. Rather a more generalized description should be included for the ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, which abstracts out the problem and a corresponding solution that is implemented in the driver. This should also help us reduce current redundancy. ---------------------------------------------------------------------- Affected cores could overwrite upto 3 cache lines of trace data at the base of the buffer (pointed by TRBASER_EL1) in FILL mode in the event of a WRAP event. Work around the issue by always making sure we move the TRBPTR_EL1 by 256bytes before enabling the buffer and filling the first 256bytes of the buffer with ETM ignore packets upon disabling. ---------------------------------------------------------------------- _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-09-22 7:21 UTC|newest] Thread overview: 124+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-21 13:41 [PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-21 13:41 ` [PATCH v2 01/17] coresight: trbe: Fix incorrect access of the sink specific data Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 5:41 ` Anshuman Khandual 2021-09-22 5:41 ` Anshuman Khandual 2021-09-30 17:57 ` Mathieu Poirier 2021-09-30 17:57 ` Mathieu Poirier 2021-09-21 13:41 ` [PATCH v2 02/17] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 6:47 ` Anshuman Khandual 2021-09-22 6:47 ` Anshuman Khandual 2021-10-05 16:46 ` Mathieu Poirier 2021-10-05 16:46 ` Mathieu Poirier 2021-09-21 13:41 ` [PATCH v2 03/17] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-30 17:54 ` Mathieu Poirier 2021-09-30 17:54 ` Mathieu Poirier 2021-10-01 8:36 ` Suzuki K Poulose 2021-10-01 8:36 ` Suzuki K Poulose 2021-10-01 15:15 ` Mathieu Poirier 2021-10-01 15:15 ` Mathieu Poirier 2021-10-01 15:22 ` Suzuki K Poulose 2021-10-01 15:22 ` Suzuki K Poulose 2021-09-21 13:41 ` [PATCH v2 04/17] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-21 13:41 ` [PATCH v2 05/17] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-21 13:41 ` [PATCH v2 06/17] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-21 13:41 ` [PATCH v2 07/17] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 6:57 ` Anshuman Khandual 2021-09-22 6:57 ` Anshuman Khandual 2021-09-21 13:41 ` [PATCH v2 08/17] arm64: Add erratum detection for TRBE overwrite in FILL mode Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-21 13:41 ` [PATCH v2 09/17] coresight: trbe: Workaround TRBE errata " Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-23 6:13 ` Anshuman Khandual 2021-09-23 6:13 ` Anshuman Khandual 2021-09-28 10:40 ` Suzuki K Poulose 2021-09-28 10:40 ` Suzuki K Poulose 2021-10-01 4:21 ` Anshuman Khandual 2021-10-01 4:21 ` Anshuman Khandual 2021-10-01 17:15 ` Mathieu Poirier 2021-10-01 17:15 ` Mathieu Poirier 2021-10-04 8:46 ` Suzuki K Poulose 2021-10-04 8:46 ` Suzuki K Poulose 2021-10-04 16:47 ` Mathieu Poirier 2021-10-04 16:47 ` Mathieu Poirier 2021-09-21 13:41 ` [PATCH v2 10/17] arm64: Enable workaround for TRBE " Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 7:23 ` Anshuman Khandual [this message] 2021-09-22 7:23 ` Anshuman Khandual 2021-09-22 8:11 ` Suzuki K Poulose 2021-09-22 8:11 ` Suzuki K Poulose 2021-10-01 4:35 ` Anshuman Khandual 2021-10-01 4:35 ` Anshuman Khandual 2021-10-07 16:09 ` Catalin Marinas 2021-10-07 16:09 ` Catalin Marinas 2021-09-21 13:41 ` [PATCH v2 11/17] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 7:39 ` Anshuman Khandual 2021-09-22 7:39 ` Anshuman Khandual 2021-09-22 12:03 ` Suzuki K Poulose 2021-09-22 12:03 ` Suzuki K Poulose 2021-10-01 4:38 ` Anshuman Khandual 2021-10-01 4:38 ` Anshuman Khandual 2021-10-07 16:10 ` Catalin Marinas 2021-10-07 16:10 ` Catalin Marinas 2021-09-21 13:41 ` [PATCH v2 12/17] coresight: trbe: Add a helper to fetch cpudata from perf handle Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 7:59 ` Anshuman Khandual 2021-09-22 7:59 ` Anshuman Khandual 2021-10-04 17:42 ` Mathieu Poirier 2021-10-04 17:42 ` Mathieu Poirier 2021-10-05 22:35 ` Suzuki K Poulose 2021-10-05 22:35 ` Suzuki K Poulose 2021-10-06 17:15 ` Mathieu Poirier 2021-10-06 17:15 ` Mathieu Poirier 2021-10-07 9:18 ` Suzuki K Poulose 2021-10-07 9:18 ` Suzuki K Poulose 2021-09-21 13:41 ` [PATCH v2 13/17] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 9:51 ` Anshuman Khandual 2021-09-22 9:51 ` Anshuman Khandual 2021-09-21 13:41 ` [PATCH v2 14/17] coresight: trbe: Make sure we have enough space Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 9:58 ` Anshuman Khandual 2021-09-22 9:58 ` Anshuman Khandual 2021-09-22 10:16 ` Suzuki K Poulose 2021-09-22 10:16 ` Suzuki K Poulose 2021-10-01 4:40 ` Anshuman Khandual 2021-10-01 4:40 ` Anshuman Khandual 2021-09-21 13:41 ` [PATCH v2 15/17] arm64: Add erratum detection for TRBE write to out-of-range Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 10:59 ` Anshuman Khandual 2021-09-22 10:59 ` Anshuman Khandual 2021-10-07 16:10 ` Catalin Marinas 2021-10-07 16:10 ` Catalin Marinas 2021-09-21 13:41 ` [PATCH v2 16/17] coresight: trbe: Work around write to out of range Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-23 3:15 ` Anshuman Khandual 2021-09-23 3:15 ` Anshuman Khandual 2021-09-28 10:32 ` Suzuki K Poulose 2021-09-28 10:32 ` Suzuki K Poulose 2021-10-01 4:56 ` Anshuman Khandual 2021-10-01 4:56 ` Anshuman Khandual 2021-09-21 13:41 ` [PATCH v2 17/17] arm64: Advertise TRBE erratum workaround for write to out-of-range address Suzuki K Poulose 2021-09-21 13:41 ` Suzuki K Poulose 2021-09-22 11:03 ` Anshuman Khandual 2021-09-22 11:03 ` Anshuman Khandual 2021-10-07 16:11 ` Catalin Marinas 2021-10-07 16:11 ` Catalin Marinas 2021-10-05 17:04 ` [PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds Mathieu Poirier 2021-10-05 17:04 ` Mathieu Poirier 2021-10-08 7:32 ` Will Deacon 2021-10-08 7:32 ` Will Deacon 2021-10-08 9:25 ` Suzuki K Poulose 2021-10-08 9:25 ` Suzuki K Poulose 2021-10-08 9:52 ` Will Deacon 2021-10-08 9:52 ` Will Deacon 2021-10-08 9:57 ` Suzuki K Poulose 2021-10-08 9:57 ` Suzuki K Poulose
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