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From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, maz@kernel.org,
	catalin.marinas@arm.com, mark.rutland@arm.com,
	james.morse@arm.com, leo.yan@linaro.org, mike.leach@linaro.org,
	mathieu.poirier@linaro.org, will@kernel.org,
	lcherian@marvell.com, coresight@lists.linaro.org
Subject: Re: [PATCH v2 13/17] coresight: trbe: Add a helper to determine the minimum buffer size
Date: Wed, 22 Sep 2021 15:21:49 +0530	[thread overview]
Message-ID: <586a307e-a51d-d176-b9f9-fc730278317e@arm.com> (raw)
In-Reply-To: <20210921134121.2423546-14-suzuki.poulose@arm.com>



On 9/21/21 7:11 PM, Suzuki K Poulose wrote:
> For the TRBE to operate, we need a minimum space available to collect
> meaningful trace session. This is currently a few bytes, but we may need
> to extend this for working around errata. So, abstract this into a helper
> function.
> 
> Cc: Anshuman Khandual <anshuman.khandual@arm.com>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Leo Yan <leo.yan@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-trbe.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> index 797d978f9fa7..3373f4e2183b 100644
> --- a/drivers/hwtracing/coresight/coresight-trbe.c
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -277,6 +277,11 @@ trbe_handle_to_cpudata(struct perf_output_handle *handle)
>  	return buf->cpudata;
>  }
>  
> +static u64 trbe_min_trace_buf_size(struct perf_output_handle *handle)
> +{
> +	return TRBE_TRACE_MIN_BUF_SIZE;
> +}

Assuming that struct perf_output_handle could provide all the
required support for a variable minimum trace buffer length.

Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>

> +
>  /*
>   * TRBE Limit Calculation
>   *
> @@ -447,7 +452,7 @@ static unsigned long trbe_normal_offset(struct perf_output_handle *handle)
>  	 * have space for a meaningful run, we rather pad it
>  	 * and start fresh.
>  	 */
> -	if (limit && (limit - head < TRBE_TRACE_MIN_BUF_SIZE)) {
> +	if (limit && ((limit - head) < trbe_min_trace_buf_size(handle))) {
>  		trbe_pad_buf(handle, limit - head);
>  		limit = __trbe_normal_offset(handle);
>  	}
> 

WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, maz@kernel.org,
	catalin.marinas@arm.com, mark.rutland@arm.com,
	james.morse@arm.com, leo.yan@linaro.org, mike.leach@linaro.org,
	mathieu.poirier@linaro.org, will@kernel.org,
	lcherian@marvell.com, coresight@lists.linaro.org
Subject: Re: [PATCH v2 13/17] coresight: trbe: Add a helper to determine the minimum buffer size
Date: Wed, 22 Sep 2021 15:21:49 +0530	[thread overview]
Message-ID: <586a307e-a51d-d176-b9f9-fc730278317e@arm.com> (raw)
In-Reply-To: <20210921134121.2423546-14-suzuki.poulose@arm.com>



On 9/21/21 7:11 PM, Suzuki K Poulose wrote:
> For the TRBE to operate, we need a minimum space available to collect
> meaningful trace session. This is currently a few bytes, but we may need
> to extend this for working around errata. So, abstract this into a helper
> function.
> 
> Cc: Anshuman Khandual <anshuman.khandual@arm.com>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Leo Yan <leo.yan@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-trbe.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> index 797d978f9fa7..3373f4e2183b 100644
> --- a/drivers/hwtracing/coresight/coresight-trbe.c
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -277,6 +277,11 @@ trbe_handle_to_cpudata(struct perf_output_handle *handle)
>  	return buf->cpudata;
>  }
>  
> +static u64 trbe_min_trace_buf_size(struct perf_output_handle *handle)
> +{
> +	return TRBE_TRACE_MIN_BUF_SIZE;
> +}

Assuming that struct perf_output_handle could provide all the
required support for a variable minimum trace buffer length.

Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>

> +
>  /*
>   * TRBE Limit Calculation
>   *
> @@ -447,7 +452,7 @@ static unsigned long trbe_normal_offset(struct perf_output_handle *handle)
>  	 * have space for a meaningful run, we rather pad it
>  	 * and start fresh.
>  	 */
> -	if (limit && (limit - head < TRBE_TRACE_MIN_BUF_SIZE)) {
> +	if (limit && ((limit - head) < trbe_min_trace_buf_size(handle))) {
>  		trbe_pad_buf(handle, limit - head);
>  		limit = __trbe_normal_offset(handle);
>  	}
> 

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  reply	other threads:[~2021-09-22  9:51 UTC|newest]

Thread overview: 124+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-21 13:41 [PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose
2021-09-21 13:41 ` Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 01/17] coresight: trbe: Fix incorrect access of the sink specific data Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22  5:41   ` Anshuman Khandual
2021-09-22  5:41     ` Anshuman Khandual
2021-09-30 17:57   ` Mathieu Poirier
2021-09-30 17:57     ` Mathieu Poirier
2021-09-21 13:41 ` [PATCH v2 02/17] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22  6:47   ` Anshuman Khandual
2021-09-22  6:47     ` Anshuman Khandual
2021-10-05 16:46   ` Mathieu Poirier
2021-10-05 16:46     ` Mathieu Poirier
2021-09-21 13:41 ` [PATCH v2 03/17] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-30 17:54   ` Mathieu Poirier
2021-09-30 17:54     ` Mathieu Poirier
2021-10-01  8:36     ` Suzuki K Poulose
2021-10-01  8:36       ` Suzuki K Poulose
2021-10-01 15:15       ` Mathieu Poirier
2021-10-01 15:15         ` Mathieu Poirier
2021-10-01 15:22         ` Suzuki K Poulose
2021-10-01 15:22           ` Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 04/17] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 05/17] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 06/17] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 07/17] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22  6:57   ` Anshuman Khandual
2021-09-22  6:57     ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 08/17] arm64: Add erratum detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 09/17] coresight: trbe: Workaround TRBE errata " Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-23  6:13   ` Anshuman Khandual
2021-09-23  6:13     ` Anshuman Khandual
2021-09-28 10:40     ` Suzuki K Poulose
2021-09-28 10:40       ` Suzuki K Poulose
2021-10-01  4:21       ` Anshuman Khandual
2021-10-01  4:21         ` Anshuman Khandual
2021-10-01 17:15   ` Mathieu Poirier
2021-10-01 17:15     ` Mathieu Poirier
2021-10-04  8:46     ` Suzuki K Poulose
2021-10-04  8:46       ` Suzuki K Poulose
2021-10-04 16:47       ` Mathieu Poirier
2021-10-04 16:47         ` Mathieu Poirier
2021-09-21 13:41 ` [PATCH v2 10/17] arm64: Enable workaround for TRBE " Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22  7:23   ` Anshuman Khandual
2021-09-22  7:23     ` Anshuman Khandual
2021-09-22  8:11     ` Suzuki K Poulose
2021-09-22  8:11       ` Suzuki K Poulose
2021-10-01  4:35       ` Anshuman Khandual
2021-10-01  4:35         ` Anshuman Khandual
2021-10-07 16:09   ` Catalin Marinas
2021-10-07 16:09     ` Catalin Marinas
2021-09-21 13:41 ` [PATCH v2 11/17] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22  7:39   ` Anshuman Khandual
2021-09-22  7:39     ` Anshuman Khandual
2021-09-22 12:03     ` Suzuki K Poulose
2021-09-22 12:03       ` Suzuki K Poulose
2021-10-01  4:38       ` Anshuman Khandual
2021-10-01  4:38         ` Anshuman Khandual
2021-10-07 16:10   ` Catalin Marinas
2021-10-07 16:10     ` Catalin Marinas
2021-09-21 13:41 ` [PATCH v2 12/17] coresight: trbe: Add a helper to fetch cpudata from perf handle Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22  7:59   ` Anshuman Khandual
2021-09-22  7:59     ` Anshuman Khandual
2021-10-04 17:42   ` Mathieu Poirier
2021-10-04 17:42     ` Mathieu Poirier
2021-10-05 22:35     ` Suzuki K Poulose
2021-10-05 22:35       ` Suzuki K Poulose
2021-10-06 17:15       ` Mathieu Poirier
2021-10-06 17:15         ` Mathieu Poirier
2021-10-07  9:18         ` Suzuki K Poulose
2021-10-07  9:18           ` Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 13/17] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22  9:51   ` Anshuman Khandual [this message]
2021-09-22  9:51     ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 14/17] coresight: trbe: Make sure we have enough space Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22  9:58   ` Anshuman Khandual
2021-09-22  9:58     ` Anshuman Khandual
2021-09-22 10:16     ` Suzuki K Poulose
2021-09-22 10:16       ` Suzuki K Poulose
2021-10-01  4:40       ` Anshuman Khandual
2021-10-01  4:40         ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 15/17] arm64: Add erratum detection for TRBE write to out-of-range Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22 10:59   ` Anshuman Khandual
2021-09-22 10:59     ` Anshuman Khandual
2021-10-07 16:10   ` Catalin Marinas
2021-10-07 16:10     ` Catalin Marinas
2021-09-21 13:41 ` [PATCH v2 16/17] coresight: trbe: Work around write to out of range Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-23  3:15   ` Anshuman Khandual
2021-09-23  3:15     ` Anshuman Khandual
2021-09-28 10:32     ` Suzuki K Poulose
2021-09-28 10:32       ` Suzuki K Poulose
2021-10-01  4:56       ` Anshuman Khandual
2021-10-01  4:56         ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 17/17] arm64: Advertise TRBE erratum workaround for write to out-of-range address Suzuki K Poulose
2021-09-21 13:41   ` Suzuki K Poulose
2021-09-22 11:03   ` Anshuman Khandual
2021-09-22 11:03     ` Anshuman Khandual
2021-10-07 16:11   ` Catalin Marinas
2021-10-07 16:11     ` Catalin Marinas
2021-10-05 17:04 ` [PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds Mathieu Poirier
2021-10-05 17:04   ` Mathieu Poirier
2021-10-08  7:32 ` Will Deacon
2021-10-08  7:32   ` Will Deacon
2021-10-08  9:25   ` Suzuki K Poulose
2021-10-08  9:25     ` Suzuki K Poulose
2021-10-08  9:52     ` Will Deacon
2021-10-08  9:52       ` Will Deacon
2021-10-08  9:57       ` Suzuki K Poulose
2021-10-08  9:57         ` Suzuki K Poulose

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