From: Aradhya Bhatia <a-bhatia1@ti.com>
To: Jyri Sarha <jyri.sarha@iki.fi>, Tomi Valkeinen <tomba@kernel.org>,
Vignesh Raghavendra <vigneshr@ti.com>, Nishanth Menon <nm@ti.com>
Cc: DRI Development <dri-devel@lists.freedesktop.org>,
Devicetree <devicetree@vger.kernel.org>,
Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>,
Linux Kernel <linux-kernel@vger.kernel.org>,
Nikhil Devshatwar <nikhil.nd@ti.com>,
Aradhya Bhatia <a-bhatia1@ti.com>
Subject: [PATCH 2/2] arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
Date: Tue, 19 Apr 2022 12:33:02 +0530 [thread overview]
Message-ID: <20220419070302.16502-3-a-bhatia1@ti.com> (raw)
In-Reply-To: <20220419070302.16502-1-a-bhatia1@ti.com>
The DSS IP on the ti-am65x soc supports an additional register space
named "common1". Further, it services a maximum of 2 interrupts.
Add the missing register space "common1" and the additional interrupt in
the dss DT node .
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index e749343acced..1bafa3a98e71 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -830,13 +830,14 @@ csi2_0: port@0 {
dss: dss@4a00000 {
compatible = "ti,am65x-dss";
reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
+ <0x0 0x04a01000 0x0 0x1000>, /* common1 */
<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
<0x0 0x04a06000 0x0 0x1000>, /* vid */
<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
- reg-names = "common", "vidl1", "vid",
+ reg-names = "common", "common1", "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2";
ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
@@ -856,7 +857,8 @@ dss: dss@4a00000 {
assigned-clocks = <&k3_clks 67 2>;
assigned-clock-parents = <&k3_clks 67 5>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
dma-coherent;
--
2.35.3
WARNING: multiple messages have this Message-ID (diff)
From: Aradhya Bhatia <a-bhatia1@ti.com>
To: Jyri Sarha <jyri.sarha@iki.fi>, Tomi Valkeinen <tomba@kernel.org>,
Vignesh Raghavendra <vigneshr@ti.com>, Nishanth Menon <nm@ti.com>
Cc: Devicetree <devicetree@vger.kernel.org>,
Aradhya Bhatia <a-bhatia1@ti.com>,
Linux Kernel <linux-kernel@vger.kernel.org>,
DRI Development <dri-devel@lists.freedesktop.org>,
Nikhil Devshatwar <nikhil.nd@ti.com>,
Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
Subject: [PATCH 2/2] arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
Date: Tue, 19 Apr 2022 12:33:02 +0530 [thread overview]
Message-ID: <20220419070302.16502-3-a-bhatia1@ti.com> (raw)
In-Reply-To: <20220419070302.16502-1-a-bhatia1@ti.com>
The DSS IP on the ti-am65x soc supports an additional register space
named "common1". Further, it services a maximum of 2 interrupts.
Add the missing register space "common1" and the additional interrupt in
the dss DT node .
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index e749343acced..1bafa3a98e71 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -830,13 +830,14 @@ csi2_0: port@0 {
dss: dss@4a00000 {
compatible = "ti,am65x-dss";
reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
+ <0x0 0x04a01000 0x0 0x1000>, /* common1 */
<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
<0x0 0x04a06000 0x0 0x1000>, /* vid */
<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
- reg-names = "common", "vidl1", "vid",
+ reg-names = "common", "common1", "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2";
ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
@@ -856,7 +857,8 @@ dss: dss@4a00000 {
assigned-clocks = <&k3_clks 67 2>;
assigned-clock-parents = <&k3_clks 67 5>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
dma-coherent;
--
2.35.3
WARNING: multiple messages have this Message-ID (diff)
From: Aradhya Bhatia <a-bhatia1@ti.com>
To: Jyri Sarha <jyri.sarha@iki.fi>, Tomi Valkeinen <tomba@kernel.org>,
Vignesh Raghavendra <vigneshr@ti.com>, Nishanth Menon <nm@ti.com>
Cc: DRI Development <dri-devel@lists.freedesktop.org>,
Devicetree <devicetree@vger.kernel.org>,
Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>,
Linux Kernel <linux-kernel@vger.kernel.org>,
Nikhil Devshatwar <nikhil.nd@ti.com>,
Aradhya Bhatia <a-bhatia1@ti.com>
Subject: [PATCH 2/2] arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
Date: Tue, 19 Apr 2022 12:33:02 +0530 [thread overview]
Message-ID: <20220419070302.16502-3-a-bhatia1@ti.com> (raw)
In-Reply-To: <20220419070302.16502-1-a-bhatia1@ti.com>
The DSS IP on the ti-am65x soc supports an additional register space
named "common1". Further, it services a maximum of 2 interrupts.
Add the missing register space "common1" and the additional interrupt in
the dss DT node .
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index e749343acced..1bafa3a98e71 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -830,13 +830,14 @@ csi2_0: port@0 {
dss: dss@4a00000 {
compatible = "ti,am65x-dss";
reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
+ <0x0 0x04a01000 0x0 0x1000>, /* common1 */
<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
<0x0 0x04a06000 0x0 0x1000>, /* vid */
<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
- reg-names = "common", "vidl1", "vid",
+ reg-names = "common", "common1", "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2";
ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
@@ -856,7 +857,8 @@ dss: dss@4a00000 {
assigned-clocks = <&k3_clks 67 2>;
assigned-clock-parents = <&k3_clks 67 5>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
dma-coherent;
--
2.35.3
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next prev parent reply other threads:[~2022-04-19 7:04 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-19 7:03 [PATCH 0/2] Update register & interrupt info in am65x DSS Aradhya Bhatia
2022-04-19 7:03 ` Aradhya Bhatia
2022-04-19 7:03 ` Aradhya Bhatia
2022-04-19 7:03 ` [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt Aradhya Bhatia
2022-04-19 7:03 ` [PATCH 1/2] dt-bindings: display: ti, am65x-dss: " Aradhya Bhatia
2022-04-19 7:03 ` Aradhya Bhatia
2022-04-19 12:12 ` Rob Herring
2022-04-19 12:12 ` Rob Herring
2022-04-19 12:12 ` [PATCH 1/2] dt-bindings: display: ti,am65x-dss: " Rob Herring
2022-04-19 12:40 ` Nishanth Menon
2022-04-19 12:40 ` Nishanth Menon
2022-04-19 12:40 ` Nishanth Menon
2022-04-19 14:20 ` Rob Herring
2022-04-19 14:20 ` Rob Herring
2022-04-19 14:20 ` Rob Herring
2022-04-20 7:05 ` Tomi Valkeinen
2022-04-20 7:05 ` Tomi Valkeinen
2022-04-20 7:05 ` Tomi Valkeinen
2022-04-20 21:30 ` Rob Herring
2022-04-20 21:30 ` Rob Herring
2022-04-20 21:30 ` Rob Herring
2022-04-19 7:03 ` Aradhya Bhatia [this message]
2022-04-19 7:03 ` [PATCH 2/2] arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node Aradhya Bhatia
2022-04-19 7:03 ` Aradhya Bhatia
2022-04-19 12:06 ` [PATCH 0/2] Update register & interrupt info in am65x DSS Tomi Valkeinen
2022-04-19 12:06 ` Tomi Valkeinen
2022-04-19 12:06 ` Tomi Valkeinen
2022-04-19 17:29 ` Aradhya Bhatia
2022-04-19 17:29 ` Aradhya Bhatia
2022-04-19 17:29 ` Aradhya Bhatia
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