From: Aradhya Bhatia <a-bhatia1@ti.com>
To: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>,
Rob Herring <robh@kernel.org>, Nishanth Menon <nm@ti.com>
Cc: Jyri Sarha <jyri.sarha@iki.fi>,
Vignesh Raghavendra <vigneshr@ti.com>,
DRI Development <dri-devel@lists.freedesktop.org>,
Devicetree <devicetree@vger.kernel.org>,
Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>,
Linux Kernel <linux-kernel@vger.kernel.org>,
Nikhil Devshatwar <nikhil.nd@ti.com>
Subject: Re: [PATCH 0/2] Update register & interrupt info in am65x DSS
Date: Tue, 19 Apr 2022 22:59:54 +0530 [thread overview]
Message-ID: <b4712133-1694-4f3a-a790-263118717715@ti.com> (raw)
In-Reply-To: <9e848e84-a31f-98ec-ed6b-c1dce022723b@ideasonboard.com>
On 19/04/22 17:36, Tomi Valkeinen wrote:
> On 19/04/2022 10:03, Aradhya Bhatia wrote:
>> The Display SubSystem IP on the ti's am65x soc has an additional
>> register space "common1" and services a maximum of 2 interrupts.
>>
>> The first patch in the series adds the required updates to the yaml
>> file. The second patch then reflects the yaml updates in the DSS DT
>> node of am65x soc.
>>
>> Aradhya Bhatia (2):
>> dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
>> arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
>>
>> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
>> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++--
>> 2 files changed, 11 insertions(+), 5 deletions(-)
>>
>
> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
>
> How are you planning to use the common1 area?
Tomi, Nishanth,
Thank you for taking out time to review this.
The DSS IP is such that it services 2 interrupts in case people want to
use DSS from 2 SW entities (2nd VM or 2nd core). The regions "common" &
"common1" cater registers for managing these 2 interrupts.
Historically, on linux, only 1 interrupt and hence only the "common"
region has been used. Therefore, the "common1" region is not actually
required.
The patches, thus, can be ignored.
Rob,
Thank you for pointing out the mistakes I have made. I will be more
careful about them going further.
>
> Tomi
Regards
Aradhya Bhatia
WARNING: multiple messages have this Message-ID (diff)
From: Aradhya Bhatia <a-bhatia1@ti.com>
To: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>,
Rob Herring <robh@kernel.org>, Nishanth Menon <nm@ti.com>
Cc: Devicetree <devicetree@vger.kernel.org>,
Vignesh Raghavendra <vigneshr@ti.com>,
Linux Kernel <linux-kernel@vger.kernel.org>,
DRI Development <dri-devel@lists.freedesktop.org>,
Jyri Sarha <jyri.sarha@iki.fi>,
Nikhil Devshatwar <nikhil.nd@ti.com>,
Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 0/2] Update register & interrupt info in am65x DSS
Date: Tue, 19 Apr 2022 22:59:54 +0530 [thread overview]
Message-ID: <b4712133-1694-4f3a-a790-263118717715@ti.com> (raw)
In-Reply-To: <9e848e84-a31f-98ec-ed6b-c1dce022723b@ideasonboard.com>
On 19/04/22 17:36, Tomi Valkeinen wrote:
> On 19/04/2022 10:03, Aradhya Bhatia wrote:
>> The Display SubSystem IP on the ti's am65x soc has an additional
>> register space "common1" and services a maximum of 2 interrupts.
>>
>> The first patch in the series adds the required updates to the yaml
>> file. The second patch then reflects the yaml updates in the DSS DT
>> node of am65x soc.
>>
>> Aradhya Bhatia (2):
>> dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
>> arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
>>
>> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
>> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++--
>> 2 files changed, 11 insertions(+), 5 deletions(-)
>>
>
> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
>
> How are you planning to use the common1 area?
Tomi, Nishanth,
Thank you for taking out time to review this.
The DSS IP is such that it services 2 interrupts in case people want to
use DSS from 2 SW entities (2nd VM or 2nd core). The regions "common" &
"common1" cater registers for managing these 2 interrupts.
Historically, on linux, only 1 interrupt and hence only the "common"
region has been used. Therefore, the "common1" region is not actually
required.
The patches, thus, can be ignored.
Rob,
Thank you for pointing out the mistakes I have made. I will be more
careful about them going further.
>
> Tomi
Regards
Aradhya Bhatia
WARNING: multiple messages have this Message-ID (diff)
From: Aradhya Bhatia <a-bhatia1@ti.com>
To: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>,
Rob Herring <robh@kernel.org>, Nishanth Menon <nm@ti.com>
Cc: Jyri Sarha <jyri.sarha@iki.fi>,
Vignesh Raghavendra <vigneshr@ti.com>,
DRI Development <dri-devel@lists.freedesktop.org>,
Devicetree <devicetree@vger.kernel.org>,
Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>,
Linux Kernel <linux-kernel@vger.kernel.org>,
Nikhil Devshatwar <nikhil.nd@ti.com>
Subject: Re: [PATCH 0/2] Update register & interrupt info in am65x DSS
Date: Tue, 19 Apr 2022 22:59:54 +0530 [thread overview]
Message-ID: <b4712133-1694-4f3a-a790-263118717715@ti.com> (raw)
In-Reply-To: <9e848e84-a31f-98ec-ed6b-c1dce022723b@ideasonboard.com>
On 19/04/22 17:36, Tomi Valkeinen wrote:
> On 19/04/2022 10:03, Aradhya Bhatia wrote:
>> The Display SubSystem IP on the ti's am65x soc has an additional
>> register space "common1" and services a maximum of 2 interrupts.
>>
>> The first patch in the series adds the required updates to the yaml
>> file. The second patch then reflects the yaml updates in the DSS DT
>> node of am65x soc.
>>
>> Aradhya Bhatia (2):
>> dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
>> arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
>>
>> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
>> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++--
>> 2 files changed, 11 insertions(+), 5 deletions(-)
>>
>
> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
>
> How are you planning to use the common1 area?
Tomi, Nishanth,
Thank you for taking out time to review this.
The DSS IP is such that it services 2 interrupts in case people want to
use DSS from 2 SW entities (2nd VM or 2nd core). The regions "common" &
"common1" cater registers for managing these 2 interrupts.
Historically, on linux, only 1 interrupt and hence only the "common"
region has been used. Therefore, the "common1" region is not actually
required.
The patches, thus, can be ignored.
Rob,
Thank you for pointing out the mistakes I have made. I will be more
careful about them going further.
>
> Tomi
Regards
Aradhya Bhatia
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next prev parent reply other threads:[~2022-04-19 17:30 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-19 7:03 [PATCH 0/2] Update register & interrupt info in am65x DSS Aradhya Bhatia
2022-04-19 7:03 ` Aradhya Bhatia
2022-04-19 7:03 ` Aradhya Bhatia
2022-04-19 7:03 ` [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt Aradhya Bhatia
2022-04-19 7:03 ` [PATCH 1/2] dt-bindings: display: ti, am65x-dss: " Aradhya Bhatia
2022-04-19 7:03 ` Aradhya Bhatia
2022-04-19 12:12 ` Rob Herring
2022-04-19 12:12 ` Rob Herring
2022-04-19 12:12 ` [PATCH 1/2] dt-bindings: display: ti,am65x-dss: " Rob Herring
2022-04-19 12:40 ` Nishanth Menon
2022-04-19 12:40 ` Nishanth Menon
2022-04-19 12:40 ` Nishanth Menon
2022-04-19 14:20 ` Rob Herring
2022-04-19 14:20 ` Rob Herring
2022-04-19 14:20 ` Rob Herring
2022-04-20 7:05 ` Tomi Valkeinen
2022-04-20 7:05 ` Tomi Valkeinen
2022-04-20 7:05 ` Tomi Valkeinen
2022-04-20 21:30 ` Rob Herring
2022-04-20 21:30 ` Rob Herring
2022-04-20 21:30 ` Rob Herring
2022-04-19 7:03 ` [PATCH 2/2] arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node Aradhya Bhatia
2022-04-19 7:03 ` Aradhya Bhatia
2022-04-19 7:03 ` Aradhya Bhatia
2022-04-19 12:06 ` [PATCH 0/2] Update register & interrupt info in am65x DSS Tomi Valkeinen
2022-04-19 12:06 ` Tomi Valkeinen
2022-04-19 12:06 ` Tomi Valkeinen
2022-04-19 17:29 ` Aradhya Bhatia [this message]
2022-04-19 17:29 ` Aradhya Bhatia
2022-04-19 17:29 ` Aradhya Bhatia
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