From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, Bjorn Andersson <bjorn.andersson@linaro.org>, Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, Abhinav Kumar <abhinavk@codeaurora.org> Cc: Stephen Boyd <sboyd@kernel.org>, David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: Re: [PATCH] drm/msm: Initialize MDSS irq domain at probe time Date: Fri, 3 Dec 2021 16:14:33 +0300 [thread overview] Message-ID: <4cb2fd68-6917-3ac3-f387-7cecb07177f3@linaro.org> (raw) In-Reply-To: <21fe6cf4-3cef-91e1-7bf7-b94ac223e7c5@collabora.com> On 03/12/2021 13:43, AngeloGioacchino Del Regno wrote: > Il 01/12/21 21:20, Dmitry Baryshkov ha scritto: >> Since commit 8f59ee9a570c ("drm/msm/dsi: Adjust probe order"), the >> DSI host gets initialized earlier, but this caused unability to probe >> the entire stack of components because they all depend on interrupts >> coming from the main `mdss` node (mdp5, or dpu1). >> >> To fix this issue, move mdss device initialization (which include irq >> domain setup) to msm_mdev_probe() time, as to make sure that the >> interrupt controller is available before dsi and/or other components try >> to initialize, finally satisfying the dependency. >> >> Fixes: 8f59ee9a570c ("drm/msm/dsi: Adjust probe order") >> Co-Developed-By: AngeloGioacchino Del Regno >> <angelogioacchino.delregno@collabora.com> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> --- >> >> When checking your patch, I noticed that IRQ domain is created before >> respective MDSS clocks are enabled. This does not look like causing any >> issues at this time, but it did not look good. So I started moving >> clocks parsing to early_init() callbacks. And at some point it looked >> like we can drop the init()/destroy() callbacks in favour of >> early_init() and remove(). Which promted me to move init()/destroy() in >> place of early_init()/remove() with few minor fixes here and there. >> > > > Hey Dmitry, > I wanted to make the least amount of changes to Rob's logic... I know that > the clocks aren't up before registering the domain, but my logic was > implying > that if the handlers aren't registered, then there's no interrupt > coming, hence > no risk of getting issues. Same if the hardware is down, you can't get any > interrupt, because it can't generate any (but if bootloader leaves it > up.. eh.) We can get spurious interrupts for any reason, which puts us at risk of peeking into unpowered registers. So, while your approach was working, it did not seem fully correct. > > I recognize that such approach is "fragile enough", lastly, I agree with > this > patch which is, in the end, something that is in the middle between my > first > and last approach. > > I've tested this one on trogdor-lazor-limozeen and seems to be working > in an > analogous way to my v2/v3, so on my side it's validated. > > > Let's go for this one! > How do we proceeed now? Are you sending a new series with the new > patches, or > should I? I'll run a few more tests and then I'll probably include both patches into the next series to be sent to Rob. > > Also, I don't think this is relevant, since I'm in co-dev, but in case > it is: > Tested-by: AngeloGioacchino Del Regno > <angelogioacchino.delregno@collabora.com> > > P.S.: Sorry for the 1-day delay, got busy with other tasks! No problem, it was just single day, no worries. -- With best wishes Dmitry
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, Bjorn Andersson <bjorn.andersson@linaro.org>, Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, Abhinav Kumar <abhinavk@codeaurora.org> Cc: Stephen Boyd <sboyd@kernel.org>, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie <airlied@linux.ie>, freedreno@lists.freedesktop.org Subject: Re: [PATCH] drm/msm: Initialize MDSS irq domain at probe time Date: Fri, 3 Dec 2021 16:14:33 +0300 [thread overview] Message-ID: <4cb2fd68-6917-3ac3-f387-7cecb07177f3@linaro.org> (raw) In-Reply-To: <21fe6cf4-3cef-91e1-7bf7-b94ac223e7c5@collabora.com> On 03/12/2021 13:43, AngeloGioacchino Del Regno wrote: > Il 01/12/21 21:20, Dmitry Baryshkov ha scritto: >> Since commit 8f59ee9a570c ("drm/msm/dsi: Adjust probe order"), the >> DSI host gets initialized earlier, but this caused unability to probe >> the entire stack of components because they all depend on interrupts >> coming from the main `mdss` node (mdp5, or dpu1). >> >> To fix this issue, move mdss device initialization (which include irq >> domain setup) to msm_mdev_probe() time, as to make sure that the >> interrupt controller is available before dsi and/or other components try >> to initialize, finally satisfying the dependency. >> >> Fixes: 8f59ee9a570c ("drm/msm/dsi: Adjust probe order") >> Co-Developed-By: AngeloGioacchino Del Regno >> <angelogioacchino.delregno@collabora.com> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> --- >> >> When checking your patch, I noticed that IRQ domain is created before >> respective MDSS clocks are enabled. This does not look like causing any >> issues at this time, but it did not look good. So I started moving >> clocks parsing to early_init() callbacks. And at some point it looked >> like we can drop the init()/destroy() callbacks in favour of >> early_init() and remove(). Which promted me to move init()/destroy() in >> place of early_init()/remove() with few minor fixes here and there. >> > > > Hey Dmitry, > I wanted to make the least amount of changes to Rob's logic... I know that > the clocks aren't up before registering the domain, but my logic was > implying > that if the handlers aren't registered, then there's no interrupt > coming, hence > no risk of getting issues. Same if the hardware is down, you can't get any > interrupt, because it can't generate any (but if bootloader leaves it > up.. eh.) We can get spurious interrupts for any reason, which puts us at risk of peeking into unpowered registers. So, while your approach was working, it did not seem fully correct. > > I recognize that such approach is "fragile enough", lastly, I agree with > this > patch which is, in the end, something that is in the middle between my > first > and last approach. > > I've tested this one on trogdor-lazor-limozeen and seems to be working > in an > analogous way to my v2/v3, so on my side it's validated. > > > Let's go for this one! > How do we proceeed now? Are you sending a new series with the new > patches, or > should I? I'll run a few more tests and then I'll probably include both patches into the next series to be sent to Rob. > > Also, I don't think this is relevant, since I'm in co-dev, but in case > it is: > Tested-by: AngeloGioacchino Del Regno > <angelogioacchino.delregno@collabora.com> > > P.S.: Sorry for the 1-day delay, got busy with other tasks! No problem, it was just single day, no worries. -- With best wishes Dmitry
next prev parent reply other threads:[~2021-12-03 13:14 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-01 10:52 [PATCH v3 0/2] drm/msm: Fix dsi/bridge probe AngeloGioacchino Del Regno 2021-12-01 10:52 ` AngeloGioacchino Del Regno 2021-12-01 10:52 ` [PATCH v3 1/2] drm/msm: Allocate msm_drm_private early and pass it as driver data AngeloGioacchino Del Regno 2021-12-01 10:52 ` AngeloGioacchino Del Regno 2021-12-01 10:52 ` [PATCH v3 2/2] drm/msm: Initialize MDSS irq domain at probe time AngeloGioacchino Del Regno 2021-12-01 10:52 ` AngeloGioacchino Del Regno 2021-12-01 20:20 ` [PATCH] " Dmitry Baryshkov 2021-12-01 20:20 ` Dmitry Baryshkov 2021-12-03 10:43 ` AngeloGioacchino Del Regno 2021-12-03 10:43 ` AngeloGioacchino Del Regno 2021-12-03 13:14 ` Dmitry Baryshkov [this message] 2021-12-03 13:14 ` Dmitry Baryshkov 2021-12-03 13:17 ` AngeloGioacchino Del Regno 2021-12-03 13:17 ` AngeloGioacchino Del Regno -- strict thread matches above, loose matches on Subject: below -- 2021-11-25 15:09 AngeloGioacchino Del Regno 2021-11-25 15:09 ` AngeloGioacchino Del Regno 2021-11-25 15:23 ` Dmitry Baryshkov 2021-11-25 15:23 ` Dmitry Baryshkov 2021-11-25 22:39 ` Dmitry Baryshkov 2021-11-25 22:39 ` Dmitry Baryshkov 2021-11-26 0:06 ` Dmitry Baryshkov 2021-11-26 0:06 ` Dmitry Baryshkov 2021-11-26 9:26 ` AngeloGioacchino Del Regno 2021-11-26 9:26 ` AngeloGioacchino Del Regno 2021-11-26 21:12 ` Dmitry Baryshkov 2021-11-26 21:12 ` Dmitry Baryshkov 2021-11-26 16:08 ` AngeloGioacchino Del Regno 2021-11-26 16:08 ` AngeloGioacchino Del Regno 2021-11-29 2:20 ` Dmitry Baryshkov 2021-11-29 2:20 ` Dmitry Baryshkov 2021-11-29 14:14 ` AngeloGioacchino Del Regno 2021-11-29 14:14 ` AngeloGioacchino Del Regno 2021-11-29 14:53 ` Dmitry Baryshkov 2021-11-29 14:53 ` Dmitry Baryshkov 2021-11-29 14:56 ` AngeloGioacchino Del Regno 2021-11-29 14:56 ` AngeloGioacchino Del Regno
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