* [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4
@ 2019-03-16 1:19 Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 01/12] riscv: pmp: Log pmp access errors as guest errors Alistair Francis
` (12 more replies)
0 siblings, 13 replies; 17+ messages in thread
From: Alistair Francis @ 2019-03-16 1:19 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
v3:
- Add a patch to remove some dead code
- Rebase on master
v2:
- Add a patch for SiFive U SMP support
- Rebase on master
Alistair Francis (3):
riscv: pmp: Log pmp access errors as guest errors
riscv: sifive_u: Allow up to 4 CPUs to be created
target/riscv: Remove unused struct
Kito Cheng (1):
RISC-V: linux-user support for RVE ABI
Michael Clark (8):
RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
RISC-V: Allow interrupt controllers to claim interrupts
RISC-V: Remove unnecessary disassembler constraints
elf: Add RISC-V PSABI ELF header defines
RISC-V: Change local interrupts from edge to level
RISC-V: Add support for vectored interrupts
RISC-V: Convert trap debugging to trace events
RISC-V: Update load reservation comment in do_interrupt
Makefile.objs | 1 +
disas/riscv.c | 138 -----------------------------
hw/riscv/sifive_plic.c | 19 +++-
hw/riscv/sifive_u.c | 5 +-
include/elf.h | 10 +++
linux-user/riscv/cpu_loop.c | 15 +++-
target/riscv/cpu.c | 6 --
target/riscv/cpu.h | 6 ++
target/riscv/cpu_helper.c | 168 +++++++++++++++---------------------
target/riscv/cpu_user.h | 3 +-
target/riscv/csr.c | 22 ++---
target/riscv/pmp.c | 20 +++--
target/riscv/trace-events | 2 +
13 files changed, 148 insertions(+), 267 deletions(-)
create mode 100644 target/riscv/trace-events
--
2.21.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Qemu-riscv] [PATCH v1 01/12] riscv: pmp: Log pmp access errors as guest errors
2019-03-16 1:19 [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
@ 2019-03-16 1:20 ` Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 02/12] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC Alistair Francis
` (11 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2019-03-16 1:20 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 20 +++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 15a5366616..b11c4ae22f 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -113,10 +113,11 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
env->pmp_state.pmp[pmp_index].cfg_reg = val;
pmp_update_rule(env, pmp_index);
} else {
- PMP_DEBUG("ignoring write - locked");
+ qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
}
} else {
- PMP_DEBUG("ignoring write - out of bounds");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "ignoring pmpcfg write - out of bounds\n");
}
}
@@ -249,7 +250,8 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
/* partially inside */
if ((s + e) == 1) {
- PMP_DEBUG("pmp violation - access is partially inside");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "pmp violation - access is partially inside\n");
ret = 0;
break;
}
@@ -306,7 +308,8 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
env->mhartid, reg_index, val);
if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {
- PMP_DEBUG("ignoring write - incorrect address");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "ignoring pmpcfg write - incorrect address\n");
return;
}
@@ -353,10 +356,12 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
env->pmp_state.pmp[addr_index].addr_reg = val;
pmp_update_rule(env, addr_index);
} else {
- PMP_DEBUG("ignoring write - locked");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "ignoring pmpaddr write - locked\n");
}
} else {
- PMP_DEBUG("ignoring write - out of bounds");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "ignoring pmpaddr write - out of bounds\n");
}
}
@@ -372,7 +377,8 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
if (addr_index < MAX_RISCV_PMPS) {
return env->pmp_state.pmp[addr_index].addr_reg;
} else {
- PMP_DEBUG("ignoring read - out of bounds");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "ignoring pmpaddr read - out of bounds\n");
return 0;
}
}
--
2.21.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-riscv] [PATCH v1 02/12] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
2019-03-16 1:19 [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 01/12] riscv: pmp: Log pmp access errors as guest errors Alistair Francis
@ 2019-03-16 1:20 ` Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 03/12] RISC-V: Allow interrupt controllers to claim interrupts Alistair Francis
` (10 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2019-03-16 1:20 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
From: Michael Clark <mjc@sifive.com>
The mode variable only uses the lower 4-bits (M,H,S,U) so
replace the GCC specific __builtin_popcount with ctpop8.
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_plic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index d12ec3fc9a..b859f919a7 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -383,7 +383,7 @@ static void parse_hart_config(SiFivePLICState *plic)
p = plic->hart_config;
while ((c = *p++)) {
if (c == ',') {
- addrid += __builtin_popcount(modes);
+ addrid += ctpop8(modes);
modes = 0;
hartid++;
} else {
@@ -397,7 +397,7 @@ static void parse_hart_config(SiFivePLICState *plic)
}
}
if (modes) {
- addrid += __builtin_popcount(modes);
+ addrid += ctpop8(modes);
}
hartid++;
--
2.21.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-riscv] [PATCH v1 03/12] RISC-V: Allow interrupt controllers to claim interrupts
2019-03-16 1:19 [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 01/12] riscv: pmp: Log pmp access errors as guest errors Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 02/12] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC Alistair Francis
@ 2019-03-16 1:20 ` Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 04/12] RISC-V: Remove unnecessary disassembler constraints Alistair Francis
` (9 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2019-03-16 1:20 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
From: Michael Clark <mjc@sifive.com>
We can't allow the supervisor to control SEIP as this would allow the
supervisor to clear a pending external interrupt which will result in
lost a interrupt in the case a PLIC is attached. The SEIP bit must be
hardware controlled when a PLIC is attached.
This logic was previously hard-coded so SEIP was always masked even
if no PLIC was attached. This patch adds riscv_cpu_claim_interrupts
so that the PLIC can register control of SEIP. In the case of models
without a PLIC (spike), the SEIP bit remains software controlled.
This interface allows for hardware control of supervisor timer and
software interrupts by other interrupt controller models.
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_plic.c | 15 +++++++++++++++
target/riscv/cpu.h | 2 ++
target/riscv/cpu_helper.c | 11 +++++++++++
target/riscv/csr.c | 10 ++--------
4 files changed, 30 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index b859f919a7..1c703e1a37 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -23,6 +23,7 @@
#include "qemu/error-report.h"
#include "hw/sysbus.h"
#include "target/riscv/cpu.h"
+#include "sysemu/sysemu.h"
#include "hw/riscv/sifive_plic.h"
#define RISCV_DEBUG_PLIC 0
@@ -431,6 +432,7 @@ static void sifive_plic_irq_request(void *opaque, int irq, int level)
static void sifive_plic_realize(DeviceState *dev, Error **errp)
{
SiFivePLICState *plic = SIFIVE_PLIC(dev);
+ int i;
memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,
TYPE_SIFIVE_PLIC, plic->aperture_size);
@@ -443,6 +445,19 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
+
+ /* We can't allow the supervisor to control SEIP as this would allow the
+ * supervisor to clear a pending external interrupt which will result in
+ * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
+ * hardware controlled when a PLIC is attached.
+ */
+ for (i = 0; i < smp_cpus; i++) {
+ RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
+ if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
+ error_report("SEIP already claimed");
+ exit(1);
+ }
+ }
}
static void sifive_plic_class_init(ObjectClass *klass, void *data)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5c2aebf132..a0b3c22dec 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -140,6 +140,7 @@ struct CPURISCVState {
* mip is 32-bits to allow atomic_read on 32-bit hosts.
*/
uint32_t mip;
+ uint32_t miclaim;
target_ulong mie;
target_ulong mideleg;
@@ -263,6 +264,7 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
#define cpu_mmu_index riscv_cpu_mmu_index
#ifndef CONFIG_USER_ONLY
+int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
#endif
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index f49e98ed59..555756d40c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -72,6 +72,17 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
#if !defined(CONFIG_USER_ONLY)
+int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
+{
+ CPURISCVState *env = &cpu->env;
+ if (env->miclaim & interrupts) {
+ return -1;
+ } else {
+ env->miclaim |= interrupts;
+ return 0;
+ }
+}
+
/* iothread_mutex must be held */
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
{
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 960d2b0aa9..938c10897c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -550,16 +550,10 @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
RISCVCPU *cpu = riscv_env_get_cpu(env);
- target_ulong mask = write_mask & delegable_ints;
+ /* Allow software control of delegable interrupts not claimed by hardware */
+ target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
uint32_t old_mip;
- /* We can't allow the supervisor to control SEIP as this would allow the
- * supervisor to clear a pending external interrupt which will result in
- * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
- * hardware controlled when a PLIC is attached. This should be an option
- * for CPUs with software-delegated Supervisor External Interrupts. */
- mask &= ~MIP_SEIP;
-
if (mask) {
qemu_mutex_lock_iothread();
old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
--
2.21.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-riscv] [PATCH v1 04/12] RISC-V: Remove unnecessary disassembler constraints
2019-03-16 1:19 [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
` (2 preceding siblings ...)
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 03/12] RISC-V: Allow interrupt controllers to claim interrupts Alistair Francis
@ 2019-03-16 1:20 ` Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 05/12] elf: Add RISC-V PSABI ELF header defines Alistair Francis
` (8 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2019-03-16 1:20 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
From: Michael Clark <mjc@sifive.com>
Remove machine generated constraints that are not
referenced by the pseudo-instruction constraints.
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 138 --------------------------------------------------
1 file changed, 138 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 7fd1019623..27546dd790 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -87,33 +87,10 @@ typedef enum {
typedef enum {
rvc_end,
- rvc_simm_6,
- rvc_imm_6,
- rvc_imm_7,
- rvc_imm_8,
- rvc_imm_9,
- rvc_imm_10,
- rvc_imm_12,
- rvc_imm_18,
- rvc_imm_nz,
- rvc_imm_x2,
- rvc_imm_x4,
- rvc_imm_x8,
- rvc_imm_x16,
- rvc_rd_b3,
- rvc_rs1_b3,
- rvc_rs2_b3,
- rvc_rd_eq_rs1,
rvc_rd_eq_ra,
- rvc_rd_eq_sp,
rvc_rd_eq_x0,
- rvc_rs1_eq_sp,
rvc_rs1_eq_x0,
rvc_rs2_eq_x0,
- rvc_rd_ne_x0_x2,
- rvc_rd_ne_x0,
- rvc_rs1_ne_x0,
- rvc_rs2_ne_x0,
rvc_rs2_eq_rs1,
rvc_rs1_eq_ra,
rvc_imm_eq_zero,
@@ -2522,111 +2499,16 @@ static bool check_constraints(rv_decode *dec, const rvc_constraint *c)
uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2;
while (*c != rvc_end) {
switch (*c) {
- case rvc_simm_6:
- if (!(imm >= -32 && imm < 32)) {
- return false;
- }
- break;
- case rvc_imm_6:
- if (!(imm <= 63)) {
- return false;
- }
- break;
- case rvc_imm_7:
- if (!(imm <= 127)) {
- return false;
- }
- break;
- case rvc_imm_8:
- if (!(imm <= 255)) {
- return false;
- }
- break;
- case rvc_imm_9:
- if (!(imm <= 511)) {
- return false;
- }
- break;
- case rvc_imm_10:
- if (!(imm <= 1023)) {
- return false;
- }
- break;
- case rvc_imm_12:
- if (!(imm <= 4095)) {
- return false;
- }
- break;
- case rvc_imm_18:
- if (!(imm <= 262143)) {
- return false;
- }
- break;
- case rvc_imm_nz:
- if (!(imm != 0)) {
- return false;
- }
- break;
- case rvc_imm_x2:
- if (!((imm & 0b1) == 0)) {
- return false;
- }
- break;
- case rvc_imm_x4:
- if (!((imm & 0b11) == 0)) {
- return false;
- }
- break;
- case rvc_imm_x8:
- if (!((imm & 0b111) == 0)) {
- return false;
- }
- break;
- case rvc_imm_x16:
- if (!((imm & 0b1111) == 0)) {
- return false;
- }
- break;
- case rvc_rd_b3:
- if (!(rd >= 8 && rd <= 15)) {
- return false;
- }
- break;
- case rvc_rs1_b3:
- if (!(rs1 >= 8 && rs1 <= 15)) {
- return false;
- }
- break;
- case rvc_rs2_b3:
- if (!(rs2 >= 8 && rs2 <= 15)) {
- return false;
- }
- break;
- case rvc_rd_eq_rs1:
- if (!(rd == rs1)) {
- return false;
- }
- break;
case rvc_rd_eq_ra:
if (!(rd == 1)) {
return false;
}
break;
- case rvc_rd_eq_sp:
- if (!(rd == 2)) {
- return false;
- }
- break;
case rvc_rd_eq_x0:
if (!(rd == 0)) {
return false;
}
break;
- case rvc_rs1_eq_sp:
- if (!(rs1 == 2)) {
- return false;
- }
- break;
case rvc_rs1_eq_x0:
if (!(rs1 == 0)) {
return false;
@@ -2637,26 +2519,6 @@ static bool check_constraints(rv_decode *dec, const rvc_constraint *c)
return false;
}
break;
- case rvc_rd_ne_x0_x2:
- if (!(rd != 0 && rd != 2)) {
- return false;
- }
- break;
- case rvc_rd_ne_x0:
- if (!(rd != 0)) {
- return false;
- }
- break;
- case rvc_rs1_ne_x0:
- if (!(rs1 != 0)) {
- return false;
- }
- break;
- case rvc_rs2_ne_x0:
- if (!(rs2 != 0)) {
- return false;
- }
- break;
case rvc_rs2_eq_rs1:
if (!(rs2 == rs1)) {
return false;
--
2.21.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-riscv] [PATCH v1 05/12] elf: Add RISC-V PSABI ELF header defines
2019-03-16 1:19 [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
` (3 preceding siblings ...)
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 04/12] RISC-V: Remove unnecessary disassembler constraints Alistair Francis
@ 2019-03-16 1:20 ` Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 06/12] RISC-V: linux-user support for RVE ABI Alistair Francis
` (7 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2019-03-16 1:20 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
From: Michael Clark <mjc@sifive.com>
Refer to the RISC-V PSABI specification for details:
- https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
Cc: Michael Tokarev <mjt@tls.msk.ru>
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/elf.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index b35347eee7..ea7708a4ea 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -1393,6 +1393,16 @@ typedef struct {
#define R_RISCV_SET16 55
#define R_RISCV_SET32 56
+/* RISC-V ELF Flags. */
+#define EF_RISCV_RVC 0x0001
+#define EF_RISCV_FLOAT_ABI 0x0006
+#define EF_RISCV_FLOAT_ABI_SOFT 0x0000
+#define EF_RISCV_FLOAT_ABI_SINGLE 0x0002
+#define EF_RISCV_FLOAT_ABI_DOUBLE 0x0004
+#define EF_RISCV_FLOAT_ABI_QUAD 0x0006
+#define EF_RISCV_RVE 0x0008
+#define EF_RISCV_TSO 0x0010
+
typedef struct elf32_rel {
Elf32_Addr r_offset;
Elf32_Word r_info;
--
2.21.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-riscv] [PATCH v1 06/12] RISC-V: linux-user support for RVE ABI
2019-03-16 1:19 [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
` (4 preceding siblings ...)
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 05/12] elf: Add RISC-V PSABI ELF header defines Alistair Francis
@ 2019-03-16 1:20 ` Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 07/12] RISC-V: Change local interrupts from edge to level Alistair Francis
` (6 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2019-03-16 1:20 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
From: Kito Cheng <kito.cheng@gmail.com>
This change checks elf_flags for EF_RISCV_RVE and if
present uses the RVE linux syscall ABI which uses t0
for the syscall number instead of a7.
Warn and exit if a non-RVE ABI binary is run on a
cpu with the RVE extension as it is incompatible.
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Co-authored-by: Kito Cheng <kito.cheng@gmail.com>
Co-authored-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
linux-user/riscv/cpu_loop.c | 15 ++++++++++++++-
target/riscv/cpu.h | 4 ++++
target/riscv/cpu_user.h | 3 ++-
3 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
index 4cf3e94632..a9bac4ca79 100644
--- a/linux-user/riscv/cpu_loop.c
+++ b/linux-user/riscv/cpu_loop.c
@@ -18,8 +18,10 @@
*/
#include "qemu/osdep.h"
+#include "qemu/error-report.h"
#include "qemu.h"
#include "cpu_loop-common.h"
+#include "elf.h"
void cpu_loop(CPURISCVState *env)
{
@@ -53,7 +55,8 @@ void cpu_loop(CPURISCVState *env)
ret = 0;
} else {
ret = do_syscall(env,
- env->gpr[xA7],
+ env->gpr[(env->elf_flags & EF_RISCV_RVE)
+ ? xT0 : xA7],
env->gpr[xA0],
env->gpr[xA1],
env->gpr[xA2],
@@ -113,6 +116,16 @@ void cpu_loop(CPURISCVState *env)
void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
{
+ CPUState *cpu = ENV_GET_CPU(env);
+ TaskState *ts = cpu->opaque;
+ struct image_info *info = ts->info;
+
env->pc = regs->sepc;
env->gpr[xSP] = regs->sp;
+ env->elf_flags = info->elf_flags;
+
+ if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
+ error_report("Incompatible ELF: RVE cpu requires RVE ABI binary");
+ exit(EXIT_FAILURE);
+ }
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a0b3c22dec..8e4b5cfe26 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -123,6 +123,10 @@ struct CPURISCVState {
uint32_t features;
+#ifdef CONFIG_USER_ONLY
+ uint32_t elf_flags;
+#endif
+
#ifndef CONFIG_USER_ONLY
target_ulong priv;
target_ulong resetvec;
diff --git a/target/riscv/cpu_user.h b/target/riscv/cpu_user.h
index c2199610ab..52d380aa98 100644
--- a/target/riscv/cpu_user.h
+++ b/target/riscv/cpu_user.h
@@ -10,4 +10,5 @@
#define xA4 14
#define xA5 15
#define xA6 16
-#define xA7 17 /* syscall number goes here */
+#define xA7 17 /* syscall number for RVI ABI */
+#define xT0 5 /* syscall number for RVE ABI */
--
2.21.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-riscv] [PATCH v1 07/12] RISC-V: Change local interrupts from edge to level
2019-03-16 1:19 [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
` (5 preceding siblings ...)
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 06/12] RISC-V: linux-user support for RVE ABI Alistair Francis
@ 2019-03-16 1:20 ` Alistair Francis
2019-03-16 1:21 ` [Qemu-riscv] [PATCH v1 08/12] RISC-V: Add support for vectored interrupts Alistair Francis
` (5 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2019-03-16 1:20 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
From: Michael Clark <mjc@sifive.com>
This effectively changes riscv_cpu_update_mip
from edge to level. i.e. cpu_interrupt or
cpu_reset_interrupt are called regardless of
the current interrupt level.
Fixes WFI doesn't return when a IPI is issued:
- https://github.com/riscv/riscv-qemu/issues/132
To test:
1) Apply RISC-V Linux CPU hotplug patch:
- http://lists.infradead.org/pipermail/linux-riscv/2018-May/000603.html
2) Enable CONFIG_CPU_HOTPLUG in linux .config
3) Try to offline and online cpus:
echo 1 > /sys/devices/system/cpu/cpu2/online
echo 0 > /sys/devices/system/cpu/cpu2/online
echo 1 > /sys/devices/system/cpu/cpu2/online
Reported-by: Atish Patra <atishp04@gmail.com>
Cc: Atish Patra <atishp04@gmail.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 555756d40c..073bdcfe74 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -95,9 +95,9 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
cmp = atomic_cmpxchg(&env->mip, old, new);
} while (old != cmp);
- if (new && !old) {
+ if (new) {
cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
- } else if (!new && old) {
+ } else {
cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
}
--
2.21.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-riscv] [PATCH v1 08/12] RISC-V: Add support for vectored interrupts
2019-03-16 1:19 [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
` (6 preceding siblings ...)
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 07/12] RISC-V: Change local interrupts from edge to level Alistair Francis
@ 2019-03-16 1:21 ` Alistair Francis
2019-03-16 1:21 ` [Qemu-riscv] [PATCH v1 09/12] RISC-V: Convert trap debugging to trace events Alistair Francis
` (4 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2019-03-16 1:21 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
From: Michael Clark <mjc@sifive.com>
If vectored interrupts are enabled (bits[1:0]
of mtvec/stvec == 1) then use the following
logic for trap entry address calculation:
pc = mtvec + cause * 4
In addition to adding support for vectored interrupts
this patch simplifies the interrupt delivery logic
by making sync/async cause decoding and encoding
steps distinct.
The cause code and the sign bit indicating sync/async
is split at the beginning of the function and fixed
cause is renamed to cause. The MSB setting for async
traps is delayed until setting mcause/scause to allow
redundant variables to be eliminated. Some variables
are renamed for conciseness and moved so that decls
are at the start of the block.
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 145 ++++++++++++++------------------------
target/riscv/csr.c | 12 ++--
2 files changed, 60 insertions(+), 97 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 073bdcfe74..a02f4dad8c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -454,118 +454,81 @@ void riscv_cpu_do_interrupt(CPUState *cs)
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- if (RISCV_DEBUG_INTERRUPT) {
- int log_cause = cs->exception_index & RISCV_EXCP_INT_MASK;
- if (cs->exception_index & RISCV_EXCP_INT_FLAG) {
- qemu_log_mask(LOG_TRACE, "core "
- TARGET_FMT_ld ": trap %s, epc 0x" TARGET_FMT_lx "\n",
- env->mhartid, riscv_intr_names[log_cause], env->pc);
- } else {
- qemu_log_mask(LOG_TRACE, "core "
- TARGET_FMT_ld ": intr %s, epc 0x" TARGET_FMT_lx "\n",
- env->mhartid, riscv_excp_names[log_cause], env->pc);
+ /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
+ * so we mask off the MSB and separate into trap type and cause.
+ */
+ bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
+ target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
+ target_ulong deleg = async ? env->mideleg : env->medeleg;
+ target_ulong tval = 0;
+
+ static const int ecall_cause_map[] = {
+ [PRV_U] = RISCV_EXCP_U_ECALL,
+ [PRV_S] = RISCV_EXCP_S_ECALL,
+ [PRV_H] = RISCV_EXCP_H_ECALL,
+ [PRV_M] = RISCV_EXCP_M_ECALL
+ };
+
+ if (!async) {
+ /* set tval to badaddr for traps with address information */
+ switch (cause) {
+ case RISCV_EXCP_INST_ADDR_MIS:
+ case RISCV_EXCP_INST_ACCESS_FAULT:
+ case RISCV_EXCP_LOAD_ADDR_MIS:
+ case RISCV_EXCP_STORE_AMO_ADDR_MIS:
+ case RISCV_EXCP_LOAD_ACCESS_FAULT:
+ case RISCV_EXCP_STORE_AMO_ACCESS_FAULT:
+ case RISCV_EXCP_INST_PAGE_FAULT:
+ case RISCV_EXCP_LOAD_PAGE_FAULT:
+ case RISCV_EXCP_STORE_PAGE_FAULT:
+ tval = env->badaddr;
+ break;
+ default:
+ break;
}
- }
-
- target_ulong fixed_cause = 0;
- if (cs->exception_index & (RISCV_EXCP_INT_FLAG)) {
- /* hacky for now. the MSB (bit 63) indicates interrupt but cs->exception
- index is only 32 bits wide */
- fixed_cause = cs->exception_index & RISCV_EXCP_INT_MASK;
- fixed_cause |= ((target_ulong)1) << (TARGET_LONG_BITS - 1);
- } else {
- /* fixup User ECALL -> correct priv ECALL */
- if (cs->exception_index == RISCV_EXCP_U_ECALL) {
- switch (env->priv) {
- case PRV_U:
- fixed_cause = RISCV_EXCP_U_ECALL;
- break;
- case PRV_S:
- fixed_cause = RISCV_EXCP_S_ECALL;
- break;
- case PRV_H:
- fixed_cause = RISCV_EXCP_H_ECALL;
- break;
- case PRV_M:
- fixed_cause = RISCV_EXCP_M_ECALL;
- break;
- }
- } else {
- fixed_cause = cs->exception_index;
+ /* ecall is dispatched as one cause so translate based on mode */
+ if (cause == RISCV_EXCP_U_ECALL) {
+ assert(env->priv <= 3);
+ cause = ecall_cause_map[env->priv];
}
}
- target_ulong backup_epc = env->pc;
-
- target_ulong bit = fixed_cause;
- target_ulong deleg = env->medeleg;
-
- int hasbadaddr =
- (fixed_cause == RISCV_EXCP_INST_ADDR_MIS) ||
- (fixed_cause == RISCV_EXCP_INST_ACCESS_FAULT) ||
- (fixed_cause == RISCV_EXCP_LOAD_ADDR_MIS) ||
- (fixed_cause == RISCV_EXCP_STORE_AMO_ADDR_MIS) ||
- (fixed_cause == RISCV_EXCP_LOAD_ACCESS_FAULT) ||
- (fixed_cause == RISCV_EXCP_STORE_AMO_ACCESS_FAULT) ||
- (fixed_cause == RISCV_EXCP_INST_PAGE_FAULT) ||
- (fixed_cause == RISCV_EXCP_LOAD_PAGE_FAULT) ||
- (fixed_cause == RISCV_EXCP_STORE_PAGE_FAULT);
-
- if (bit & ((target_ulong)1 << (TARGET_LONG_BITS - 1))) {
- deleg = env->mideleg;
- bit &= ~((target_ulong)1 << (TARGET_LONG_BITS - 1));
+ if (RISCV_DEBUG_INTERRUPT) {
+ qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": %s %s, "
+ "epc 0x" TARGET_FMT_lx ": tval 0x" TARGET_FMT_lx "\n",
+ env->mhartid, async ? "intr" : "trap",
+ (async ? riscv_intr_names : riscv_excp_names)[cause],
+ env->pc, tval);
}
- if (env->priv <= PRV_S && bit < 64 && ((deleg >> bit) & 1)) {
+ if (env->priv <= PRV_S &&
+ cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
/* handle the trap in S-mode */
- /* No need to check STVEC for misaligned - lower 2 bits cannot be set */
- env->pc = env->stvec;
- env->scause = fixed_cause;
- env->sepc = backup_epc;
-
- if (hasbadaddr) {
- if (RISCV_DEBUG_INTERRUPT) {
- qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": badaddr 0x"
- TARGET_FMT_lx "\n", env->mhartid, env->badaddr);
- }
- env->sbadaddr = env->badaddr;
- } else {
- /* otherwise we must clear sbadaddr/stval
- * todo: support populating stval on illegal instructions */
- env->sbadaddr = 0;
- }
-
target_ulong s = env->mstatus;
s = set_field(s, MSTATUS_SPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv));
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
env->mstatus = s;
+ env->scause = cause | ~(((target_ulong)-1) >> async);
+ env->sepc = env->pc;
+ env->sbadaddr = tval;
+ env->pc = (env->stvec >> 2 << 2) +
+ ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
riscv_cpu_set_mode(env, PRV_S);
} else {
- /* No need to check MTVEC for misaligned - lower 2 bits cannot be set */
- env->pc = env->mtvec;
- env->mepc = backup_epc;
- env->mcause = fixed_cause;
-
- if (hasbadaddr) {
- if (RISCV_DEBUG_INTERRUPT) {
- qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": badaddr 0x"
- TARGET_FMT_lx "\n", env->mhartid, env->badaddr);
- }
- env->mbadaddr = env->badaddr;
- } else {
- /* otherwise we must clear mbadaddr/mtval
- * todo: support populating mtval on illegal instructions */
- env->mbadaddr = 0;
- }
-
+ /* handle the trap in M-mode */
target_ulong s = env->mstatus;
s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv));
s = set_field(s, MSTATUS_MPP, env->priv);
s = set_field(s, MSTATUS_MIE, 0);
env->mstatus = s;
+ env->mcause = cause | ~(((target_ulong)-1) >> async);
+ env->mepc = env->pc;
+ env->mbadaddr = tval;
+ env->pc = (env->mtvec >> 2 << 2) +
+ ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
riscv_cpu_set_mode(env, PRV_M);
}
/* TODO yield load reservation */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 938c10897c..8039eb6e48 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -435,10 +435,10 @@ static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val)
static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
{
/* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
- if ((val & 3) == 0) {
- env->mtvec = val >> 2 << 2;
+ if ((val & 3) < 2) {
+ env->mtvec = val;
} else {
- qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: vectored traps not supported");
+ qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
}
return 0;
}
@@ -607,10 +607,10 @@ static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
{
/* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
- if ((val & 3) == 0) {
- env->stvec = val >> 2 << 2;
+ if ((val & 3) < 2) {
+ env->stvec = val;
} else {
- qemu_log_mask(LOG_UNIMP, "CSR_STVEC: vectored traps not supported");
+ qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
}
return 0;
}
--
2.21.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-riscv] [PATCH v1 09/12] RISC-V: Convert trap debugging to trace events
2019-03-16 1:19 [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
` (7 preceding siblings ...)
2019-03-16 1:21 ` [Qemu-riscv] [PATCH v1 08/12] RISC-V: Add support for vectored interrupts Alistair Francis
@ 2019-03-16 1:21 ` Alistair Francis
2019-03-16 1:21 ` [Qemu-riscv] [PATCH v1 10/12] RISC-V: Update load reservation comment in do_interrupt Alistair Francis
` (3 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2019-03-16 1:21 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
From: Michael Clark <mjc@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
Makefile.objs | 1 +
target/riscv/cpu_helper.c | 12 +++---------
target/riscv/trace-events | 2 ++
3 files changed, 6 insertions(+), 9 deletions(-)
create mode 100644 target/riscv/trace-events
diff --git a/Makefile.objs b/Makefile.objs
index 72debbf5c5..cf065de5ed 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -186,6 +186,7 @@ trace-events-subdirs += target/hppa
trace-events-subdirs += target/i386
trace-events-subdirs += target/mips
trace-events-subdirs += target/ppc
+trace-events-subdirs += target/riscv
trace-events-subdirs += target/s390x
trace-events-subdirs += target/sparc
trace-events-subdirs += ui
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index a02f4dad8c..6d3fbc3401 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -22,8 +22,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "tcg-op.h"
-
-#define RISCV_DEBUG_INTERRUPT 0
+#include "trace.h"
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
{
@@ -493,13 +492,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
}
}
- if (RISCV_DEBUG_INTERRUPT) {
- qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": %s %s, "
- "epc 0x" TARGET_FMT_lx ": tval 0x" TARGET_FMT_lx "\n",
- env->mhartid, async ? "intr" : "trap",
- (async ? riscv_intr_names : riscv_excp_names)[cause],
- env->pc, tval);
- }
+ trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 16 ?
+ (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)");
if (env->priv <= PRV_S &&
cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
diff --git a/target/riscv/trace-events b/target/riscv/trace-events
new file mode 100644
index 0000000000..48af0373df
--- /dev/null
+++ b/target/riscv/trace-events
@@ -0,0 +1,2 @@
+# target/riscv/cpu_helper.c
+riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char *desc) "hart:%"PRId64", async:%d, cause:%"PRId64", epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s"
--
2.21.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-riscv] [PATCH v1 10/12] RISC-V: Update load reservation comment in do_interrupt
2019-03-16 1:19 [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
` (8 preceding siblings ...)
2019-03-16 1:21 ` [Qemu-riscv] [PATCH v1 09/12] RISC-V: Convert trap debugging to trace events Alistair Francis
@ 2019-03-16 1:21 ` Alistair Francis
2019-03-16 1:21 ` [Qemu-riscv] [PATCH v1 11/12] riscv: sifive_u: Allow up to 4 CPUs to be created Alistair Francis
` (2 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2019-03-16 1:21 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
From: Michael Clark <mjc@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 6d3fbc3401..b17f169681 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -525,7 +525,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
riscv_cpu_set_mode(env, PRV_M);
}
- /* TODO yield load reservation */
+
+ /* NOTE: it is not necessary to yield load reservations here. It is only
+ * necessary for an SC from "another hart" to cause a load reservation
+ * to be yielded. Refer to the memory consistency model section of the
+ * RISC-V ISA Specification.
+ */
+
#endif
cs->exception_index = EXCP_NONE; /* mark handled to qemu */
}
--
2.21.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-riscv] [PATCH v1 11/12] riscv: sifive_u: Allow up to 4 CPUs to be created
2019-03-16 1:19 [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
` (9 preceding siblings ...)
2019-03-16 1:21 ` [Qemu-riscv] [PATCH v1 10/12] RISC-V: Update load reservation comment in do_interrupt Alistair Francis
@ 2019-03-16 1:21 ` Alistair Francis
2019-03-16 1:21 ` [Qemu-riscv] [PATCH v1 12/12] target/riscv: Remove unused struct Alistair Francis
2019-03-16 1:22 ` [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
12 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2019-03-16 1:21 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7bc25820fe..3199238ba0 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -398,7 +398,10 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V Board compatible with SiFive U SDK";
mc->init = riscv_sifive_u_init;
- mc->max_cpus = 1;
+ /* The real hardware has 5 CPUs, but one of them is a small embedded power
+ * management CPU.
+ */
+ mc->max_cpus = 4;
}
DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
--
2.21.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-riscv] [PATCH v1 12/12] target/riscv: Remove unused struct
2019-03-16 1:19 [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
` (10 preceding siblings ...)
2019-03-16 1:21 ` [Qemu-riscv] [PATCH v1 11/12] riscv: sifive_u: Allow up to 4 CPUs to be created Alistair Francis
@ 2019-03-16 1:21 ` Alistair Francis
2019-03-16 1:22 ` [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
12 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2019-03-16 1:21 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cc3ddc0ae4..568c4cd637 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -80,12 +80,6 @@ const char * const riscv_intr_names[] = {
"reserved"
};
-typedef struct RISCVCPUInfo {
- const int bit_widths;
- const char *name;
- void (*initfn)(Object *obj);
-} RISCVCPUInfo;
-
static void set_misa(CPURISCVState *env, target_ulong misa)
{
env->misa_mask = env->misa = misa;
--
2.21.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4
2019-03-16 1:19 [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
` (11 preceding siblings ...)
2019-03-16 1:21 ` [Qemu-riscv] [PATCH v1 12/12] target/riscv: Remove unused struct Alistair Francis
@ 2019-03-16 1:22 ` Alistair Francis
2019-03-19 0:33 ` Alistair Francis
12 siblings, 1 reply; 17+ messages in thread
From: Alistair Francis @ 2019-03-16 1:22 UTC (permalink / raw)
To: Alistair Francis; +Cc: qemu-devel, qemu-riscv, palmer
On Fri, Mar 15, 2019 at 6:19 PM Alistair Francis
<Alistair.Francis@wdc.com> wrote:
>
> v3:
> - Add a patch to remove some dead code
> - Rebase on master
> v2:
> - Add a patch for SiFive U SMP support
> - Rebase on master
>
> Alistair Francis (3):
> riscv: pmp: Log pmp access errors as guest errors
> riscv: sifive_u: Allow up to 4 CPUs to be created
> target/riscv: Remove unused struct
>
> Kito Cheng (1):
> RISC-V: linux-user support for RVE ABI
>
> Michael Clark (8):
> RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
> RISC-V: Allow interrupt controllers to claim interrupts
> RISC-V: Remove unnecessary disassembler constraints
> elf: Add RISC-V PSABI ELF header defines
> RISC-V: Change local interrupts from edge to level
> RISC-V: Add support for vectored interrupts
> RISC-V: Convert trap debugging to trace events
> RISC-V: Update load reservation comment in do_interrupt
Sorry, this series should be v3 in the title. I won't resend it, just pretend :)
Alistair
>
> Makefile.objs | 1 +
> disas/riscv.c | 138 -----------------------------
> hw/riscv/sifive_plic.c | 19 +++-
> hw/riscv/sifive_u.c | 5 +-
> include/elf.h | 10 +++
> linux-user/riscv/cpu_loop.c | 15 +++-
> target/riscv/cpu.c | 6 --
> target/riscv/cpu.h | 6 ++
> target/riscv/cpu_helper.c | 168 +++++++++++++++---------------------
> target/riscv/cpu_user.h | 3 +-
> target/riscv/csr.c | 22 ++---
> target/riscv/pmp.c | 20 +++--
> target/riscv/trace-events | 2 +
> 13 files changed, 148 insertions(+), 267 deletions(-)
> create mode 100644 target/riscv/trace-events
>
> --
> 2.21.0
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4
2019-03-16 1:22 ` [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
@ 2019-03-19 0:33 ` Alistair Francis
2019-03-19 3:41 ` Palmer Dabbelt
0 siblings, 1 reply; 17+ messages in thread
From: Alistair Francis @ 2019-03-19 0:33 UTC (permalink / raw)
To: palmer; +Cc: qemu-devel, qemu-riscv, Alistair Francis
On Fri, Mar 15, 2019 at 6:22 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Fri, Mar 15, 2019 at 6:19 PM Alistair Francis
> <Alistair.Francis@wdc.com> wrote:
> >
> > v3:
> > - Add a patch to remove some dead code
> > - Rebase on master
> > v2:
> > - Add a patch for SiFive U SMP support
> > - Rebase on master
> >
> > Alistair Francis (3):
> > riscv: pmp: Log pmp access errors as guest errors
> > riscv: sifive_u: Allow up to 4 CPUs to be created
> > target/riscv: Remove unused struct
> >
> > Kito Cheng (1):
> > RISC-V: linux-user support for RVE ABI
> >
> > Michael Clark (8):
> > RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
> > RISC-V: Allow interrupt controllers to claim interrupts
> > RISC-V: Remove unnecessary disassembler constraints
> > elf: Add RISC-V PSABI ELF header defines
> > RISC-V: Change local interrupts from edge to level
> > RISC-V: Add support for vectored interrupts
> > RISC-V: Convert trap debugging to trace events
> > RISC-V: Update load reservation comment in do_interrupt
@Palmer
Any chance this can go in for 4.0? It's just bug fixes that have been
on list for a while. Without this series u-boot SMP won't work in
QEMU, see here:
https://lists.denx.de/pipermail/u-boot/2019-March/360899.html
Alistair
>
> Sorry, this series should be v3 in the title. I won't resend it, just pretend :)
>
> Alistair
>
> >
> > Makefile.objs | 1 +
> > disas/riscv.c | 138 -----------------------------
> > hw/riscv/sifive_plic.c | 19 +++-
> > hw/riscv/sifive_u.c | 5 +-
> > include/elf.h | 10 +++
> > linux-user/riscv/cpu_loop.c | 15 +++-
> > target/riscv/cpu.c | 6 --
> > target/riscv/cpu.h | 6 ++
> > target/riscv/cpu_helper.c | 168 +++++++++++++++---------------------
> > target/riscv/cpu_user.h | 3 +-
> > target/riscv/csr.c | 22 ++---
> > target/riscv/pmp.c | 20 +++--
> > target/riscv/trace-events | 2 +
> > 13 files changed, 148 insertions(+), 267 deletions(-)
> > create mode 100644 target/riscv/trace-events
> >
> > --
> > 2.21.0
> >
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4
2019-03-19 0:33 ` Alistair Francis
@ 2019-03-19 3:41 ` Palmer Dabbelt
2019-03-19 17:14 ` Alistair Francis
0 siblings, 1 reply; 17+ messages in thread
From: Palmer Dabbelt @ 2019-03-19 3:41 UTC (permalink / raw)
To: alistair23; +Cc: qemu-devel, qemu-riscv, Alistair Francis
On Mon, 18 Mar 2019 17:33:38 PDT (-0700), alistair23@gmail.com wrote:
> On Fri, Mar 15, 2019 at 6:22 PM Alistair Francis <alistair23@gmail.com> wrote:
>>
>> On Fri, Mar 15, 2019 at 6:19 PM Alistair Francis
>> <Alistair.Francis@wdc.com> wrote:
>> >
>> > v3:
>> > - Add a patch to remove some dead code
>> > - Rebase on master
>> > v2:
>> > - Add a patch for SiFive U SMP support
>> > - Rebase on master
>> >
>> > Alistair Francis (3):
>> > riscv: pmp: Log pmp access errors as guest errors
>> > riscv: sifive_u: Allow up to 4 CPUs to be created
>> > target/riscv: Remove unused struct
>> >
>> > Kito Cheng (1):
>> > RISC-V: linux-user support for RVE ABI
>> >
>> > Michael Clark (8):
>> > RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
>> > RISC-V: Allow interrupt controllers to claim interrupts
>> > RISC-V: Remove unnecessary disassembler constraints
>> > elf: Add RISC-V PSABI ELF header defines
>> > RISC-V: Change local interrupts from edge to level
>> > RISC-V: Add support for vectored interrupts
>> > RISC-V: Convert trap debugging to trace events
>> > RISC-V: Update load reservation comment in do_interrupt
>
> @Palmer
>
> Any chance this can go in for 4.0? It's just bug fixes that have been
> on list for a while. Without this series u-boot SMP won't work in
> QEMU, see here:
> https://lists.denx.de/pipermail/u-boot/2019-March/360899.html
That was my plan. Since they're all bug fixes I was more worried about getting
everything together on the decodetree front. I'm hoping to get another PR out
later this week that collects all the bug fixes we have floating around for
rc1.
>
> Alistair
>
>>
>> Sorry, this series should be v3 in the title. I won't resend it, just pretend :)
>>
>> Alistair
>>
>> >
>> > Makefile.objs | 1 +
>> > disas/riscv.c | 138 -----------------------------
>> > hw/riscv/sifive_plic.c | 19 +++-
>> > hw/riscv/sifive_u.c | 5 +-
>> > include/elf.h | 10 +++
>> > linux-user/riscv/cpu_loop.c | 15 +++-
>> > target/riscv/cpu.c | 6 --
>> > target/riscv/cpu.h | 6 ++
>> > target/riscv/cpu_helper.c | 168 +++++++++++++++---------------------
>> > target/riscv/cpu_user.h | 3 +-
>> > target/riscv/csr.c | 22 ++---
>> > target/riscv/pmp.c | 20 +++--
>> > target/riscv/trace-events | 2 +
>> > 13 files changed, 148 insertions(+), 267 deletions(-)
>> > create mode 100644 target/riscv/trace-events
>> >
>> > --
>> > 2.21.0
>> >
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4
2019-03-19 3:41 ` Palmer Dabbelt
@ 2019-03-19 17:14 ` Alistair Francis
0 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2019-03-19 17:14 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Alistair Francis
On Mon, Mar 18, 2019 at 8:41 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Mon, 18 Mar 2019 17:33:38 PDT (-0700), alistair23@gmail.com wrote:
> > On Fri, Mar 15, 2019 at 6:22 PM Alistair Francis <alistair23@gmail.com> wrote:
> >>
> >> On Fri, Mar 15, 2019 at 6:19 PM Alistair Francis
> >> <Alistair.Francis@wdc.com> wrote:
> >> >
> >> > v3:
> >> > - Add a patch to remove some dead code
> >> > - Rebase on master
> >> > v2:
> >> > - Add a patch for SiFive U SMP support
> >> > - Rebase on master
> >> >
> >> > Alistair Francis (3):
> >> > riscv: pmp: Log pmp access errors as guest errors
> >> > riscv: sifive_u: Allow up to 4 CPUs to be created
> >> > target/riscv: Remove unused struct
> >> >
> >> > Kito Cheng (1):
> >> > RISC-V: linux-user support for RVE ABI
> >> >
> >> > Michael Clark (8):
> >> > RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
> >> > RISC-V: Allow interrupt controllers to claim interrupts
> >> > RISC-V: Remove unnecessary disassembler constraints
> >> > elf: Add RISC-V PSABI ELF header defines
> >> > RISC-V: Change local interrupts from edge to level
> >> > RISC-V: Add support for vectored interrupts
> >> > RISC-V: Convert trap debugging to trace events
> >> > RISC-V: Update load reservation comment in do_interrupt
> >
> > @Palmer
> >
> > Any chance this can go in for 4.0? It's just bug fixes that have been
> > on list for a while. Without this series u-boot SMP won't work in
> > QEMU, see here:
> > https://lists.denx.de/pipermail/u-boot/2019-March/360899.html
>
> That was my plan. Since they're all bug fixes I was more worried about getting
> everything together on the decodetree front. I'm hoping to get another PR out
> later this week that collects all the bug fixes we have floating around for
> rc1.
Awesome! Thanks for getting all the patches in.
Alistair
>
> >
> > Alistair
> >
> >>
> >> Sorry, this series should be v3 in the title. I won't resend it, just pretend :)
> >>
> >> Alistair
> >>
> >> >
> >> > Makefile.objs | 1 +
> >> > disas/riscv.c | 138 -----------------------------
> >> > hw/riscv/sifive_plic.c | 19 +++-
> >> > hw/riscv/sifive_u.c | 5 +-
> >> > include/elf.h | 10 +++
> >> > linux-user/riscv/cpu_loop.c | 15 +++-
> >> > target/riscv/cpu.c | 6 --
> >> > target/riscv/cpu.h | 6 ++
> >> > target/riscv/cpu_helper.c | 168 +++++++++++++++---------------------
> >> > target/riscv/cpu_user.h | 3 +-
> >> > target/riscv/csr.c | 22 ++---
> >> > target/riscv/pmp.c | 20 +++--
> >> > target/riscv/trace-events | 2 +
> >> > 13 files changed, 148 insertions(+), 267 deletions(-)
> >> > create mode 100644 target/riscv/trace-events
> >> >
> >> > --
> >> > 2.21.0
> >> >
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2019-03-19 17:15 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-16 1:19 [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 01/12] riscv: pmp: Log pmp access errors as guest errors Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 02/12] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 03/12] RISC-V: Allow interrupt controllers to claim interrupts Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 04/12] RISC-V: Remove unnecessary disassembler constraints Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 05/12] elf: Add RISC-V PSABI ELF header defines Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 06/12] RISC-V: linux-user support for RVE ABI Alistair Francis
2019-03-16 1:20 ` [Qemu-riscv] [PATCH v1 07/12] RISC-V: Change local interrupts from edge to level Alistair Francis
2019-03-16 1:21 ` [Qemu-riscv] [PATCH v1 08/12] RISC-V: Add support for vectored interrupts Alistair Francis
2019-03-16 1:21 ` [Qemu-riscv] [PATCH v1 09/12] RISC-V: Convert trap debugging to trace events Alistair Francis
2019-03-16 1:21 ` [Qemu-riscv] [PATCH v1 10/12] RISC-V: Update load reservation comment in do_interrupt Alistair Francis
2019-03-16 1:21 ` [Qemu-riscv] [PATCH v1 11/12] riscv: sifive_u: Allow up to 4 CPUs to be created Alistair Francis
2019-03-16 1:21 ` [Qemu-riscv] [PATCH v1 12/12] target/riscv: Remove unused struct Alistair Francis
2019-03-16 1:22 ` [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4 Alistair Francis
2019-03-19 0:33 ` Alistair Francis
2019-03-19 3:41 ` Palmer Dabbelt
2019-03-19 17:14 ` Alistair Francis
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