From: "Maciej W. Rozycki" <macro@imgtec.com> To: Fredrik Noring <noring@nocrew.org> Cc: <linux-mips@linux-mips.org> Subject: Re: [PATCH v2] MIPS: Add basic R5900 support Date: Mon, 2 Oct 2017 10:11:35 +0100 [thread overview] Message-ID: <alpine.DEB.2.00.1709301929060.12020@tp.orcam.me.uk> (raw) In-Reply-To: <20170930182608.GB7714@localhost.localdomain> Hi Fredrik, > > > I suspect 63:32 are the critical bits of the upper 96 bits since SD/LD > > > is sufficient. Summery of observations thus far: save/restore works with > > > SQ/LQ and SD/LD, but not SW/LW, in a 32-bit kernel ceteris paribus. > > > > This does look intriguing. > > I believe the simple answer to this mystery is that addresses are not > supposed to be sign-extended, given the look of $31 below. What are > your thoughts on this? [...] > $28 : > ffffffff81f70000 > ffffffff81f71bf8 > ffffffff815010f8 > 00000000800bed80 > Hi : 00000000 > Lo : 00000048 > epc : 800beeb0 unmap_page_range+0x3cc/0x664 > ra : 00000000800bed80 unmap_page_range+0x29c/0x664 Hmm, this looks consistent with the TX79 manual: "6.2.1 Virtual Address Space The C790 only implements 32 bits of virtual address space. There is no requirement for address sign extension and no checking will be done on the upper 32 bits of the address." and then say in the JAL instruction description: "I: GPR[31] 63..0 <- zero_extend (PC + 8)" It does not matter for the user mode where bit #31 is 0 and therefore both zero-extension and sign-extension produce the same result, so the typical PIC code sequence used to determine its own location, i.e.: la $2, 0f bltzal $0, 0f 0: subu $2, $31, $2 will work correctly, not causing UB with the SUBU instruction. However it does cause complications for the kernel in that the value of $ra retrieved cannot be readily used for 32-bit calculations and has to be treated with SLL by 0 first. You'll have to audit the arch/mips subtree for any such $ra use for calculation; hopefully are there's none. I wonder why they broke it like this -- was it a silly deliberate choice or merely an oversight (erratum) they chose to document rather than fix? For a change they do implement MFC0 with sign-extension, so retrieving e.g. CP0.EPC will see kernel addresses correctly sign-extended. Anyway, as noted above that shouldn't cause a problem with user software and I think that any corruption you can see comes from elsewhere. You'll have to paper this $ra non-sign-extension issue over somehow to proceed though. Maciej
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From: "Maciej W. Rozycki" <macro@imgtec.com> To: Fredrik Noring <noring@nocrew.org> Cc: linux-mips@linux-mips.org Subject: Re: [PATCH v2] MIPS: Add basic R5900 support Date: Mon, 2 Oct 2017 10:11:35 +0100 [thread overview] Message-ID: <alpine.DEB.2.00.1709301929060.12020@tp.orcam.me.uk> (raw) Message-ID: <20171002091135.VzzZCX_P9NNDvBCuqJ0Gg04Q5znquucAwTd6RC0yTjo@z> (raw) In-Reply-To: <20170930182608.GB7714@localhost.localdomain> Hi Fredrik, > > > I suspect 63:32 are the critical bits of the upper 96 bits since SD/LD > > > is sufficient. Summery of observations thus far: save/restore works with > > > SQ/LQ and SD/LD, but not SW/LW, in a 32-bit kernel ceteris paribus. > > > > This does look intriguing. > > I believe the simple answer to this mystery is that addresses are not > supposed to be sign-extended, given the look of $31 below. What are > your thoughts on this? [...] > $28 : > ffffffff81f70000 > ffffffff81f71bf8 > ffffffff815010f8 > 00000000800bed80 > Hi : 00000000 > Lo : 00000048 > epc : 800beeb0 unmap_page_range+0x3cc/0x664 > ra : 00000000800bed80 unmap_page_range+0x29c/0x664 Hmm, this looks consistent with the TX79 manual: "6.2.1 Virtual Address Space The C790 only implements 32 bits of virtual address space. There is no requirement for address sign extension and no checking will be done on the upper 32 bits of the address." and then say in the JAL instruction description: "I: GPR[31] 63..0 <- zero_extend (PC + 8)" It does not matter for the user mode where bit #31 is 0 and therefore both zero-extension and sign-extension produce the same result, so the typical PIC code sequence used to determine its own location, i.e.: la $2, 0f bltzal $0, 0f 0: subu $2, $31, $2 will work correctly, not causing UB with the SUBU instruction. However it does cause complications for the kernel in that the value of $ra retrieved cannot be readily used for 32-bit calculations and has to be treated with SLL by 0 first. You'll have to audit the arch/mips subtree for any such $ra use for calculation; hopefully are there's none. I wonder why they broke it like this -- was it a silly deliberate choice or merely an oversight (erratum) they chose to document rather than fix? For a change they do implement MFC0 with sign-extension, so retrieving e.g. CP0.EPC will see kernel addresses correctly sign-extended. Anyway, as noted above that shouldn't cause a problem with user software and I think that any corruption you can see comes from elsewhere. You'll have to paper this $ra non-sign-extension issue over somehow to proceed though. Maciej
next prev parent reply other threads:[~2017-10-02 9:12 UTC|newest] Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-08-27 13:23 [PATCH] MIPS: Add basic R5900 support Fredrik Noring 2017-08-28 13:53 ` Ralf Baechle 2017-08-28 17:11 ` Maciej W. Rozycki 2017-08-29 17:33 ` Fredrik Noring 2017-08-29 17:24 ` Maciej W. Rozycki 2017-08-29 17:24 ` Maciej W. Rozycki 2017-08-30 13:23 ` Fredrik Noring 2017-08-31 15:11 ` Maciej W. Rozycki 2017-08-31 15:11 ` Maciej W. Rozycki 2017-09-02 10:28 ` Fredrik Noring 2017-09-09 10:13 ` Maciej W. Rozycki 2017-09-09 10:13 ` Maciej W. Rozycki 2017-09-11 5:21 ` Maciej W. Rozycki 2017-09-11 5:21 ` Maciej W. Rozycki 2017-09-12 17:59 ` Fredrik Noring 2017-09-15 11:12 ` Maciej W. Rozycki 2017-09-15 11:12 ` Maciej W. Rozycki 2017-09-15 13:19 ` Fredrik Noring 2017-09-15 18:28 ` Maciej W. Rozycki 2017-09-15 18:28 ` Maciej W. Rozycki 2017-09-02 14:10 ` [PATCH v2] " Fredrik Noring 2017-09-11 5:18 ` Maciej W. Rozycki 2017-09-11 5:18 ` Maciej W. Rozycki 2017-09-11 15:17 ` Fredrik Noring 2017-09-14 13:50 ` Maciej W. Rozycki 2017-09-14 13:50 ` Maciej W. Rozycki 2017-09-16 13:34 ` Fredrik Noring 2017-09-18 17:05 ` Maciej W. Rozycki 2017-09-18 17:05 ` Maciej W. Rozycki 2017-09-18 19:24 ` Fredrik Noring 2017-09-19 12:44 ` Maciej W. Rozycki 2017-09-19 12:44 ` Maciej W. Rozycki 2017-09-20 14:54 ` Fredrik Noring 2017-09-26 11:50 ` Maciej W. Rozycki 2017-09-26 11:50 ` Maciej W. Rozycki 2017-09-27 17:21 ` Fredrik Noring 2017-09-28 12:13 ` Maciej W. Rozycki 2017-09-28 12:13 ` Maciej W. Rozycki 2017-09-30 6:56 ` Fredrik Noring 2017-10-02 9:05 ` Maciej W. Rozycki 2017-10-02 9:05 ` Maciej W. Rozycki 2017-10-02 16:33 ` Fredrik Noring 2017-10-29 17:20 ` Fredrik Noring 2017-11-10 23:34 ` Maciej W. Rozycki 2017-11-10 23:34 ` Maciej W. Rozycki 2017-11-11 16:04 ` Fredrik Noring 2018-01-29 20:27 ` Fredrik Noring 2018-01-31 23:01 ` Maciej W. Rozycki 2018-02-11 7:29 ` [RFC] MIPS: R5900: Workaround for the short loop bug Fredrik Noring 2018-02-12 9:25 ` Maciej W. Rozycki 2018-02-12 15:22 ` Fredrik Noring 2018-02-11 7:46 ` [RFC] MIPS: R5900: Use SYNC.L for data cache and SYNC.P for instruction cache Fredrik Noring 2018-02-11 7:56 ` [RFC] MIPS: R5900: Workaround exception NOP execution bug (FLX05) Fredrik Noring 2018-02-12 9:28 ` Maciej W. Rozycki 2018-02-15 19:15 ` [RFC v2] " Fredrik Noring 2018-02-15 20:49 ` Maciej W. Rozycki 2018-02-17 11:16 ` Fredrik Noring 2018-02-17 11:57 ` Maciej W. Rozycki 2018-02-17 13:38 ` Fredrik Noring 2018-02-17 15:03 ` Maciej W. Rozycki 2018-02-17 20:04 ` Fredrik Noring 2018-02-20 14:09 ` Maciej W. Rozycki 2018-02-22 17:04 ` Fredrik Noring 2018-02-18 8:47 ` Fredrik Noring 2018-02-20 14:41 ` Maciej W. Rozycki 2018-02-22 17:27 ` Fredrik Noring 2018-02-11 8:01 ` [RFC] MIPS: R5900: Workaround for CACHE instruction near branch delay slot Fredrik Noring 2018-02-11 11:16 ` Aw: " "Jürgen Urban" 2018-02-11 8:09 ` [RFC] MIPS: R5900: The ERET instruction has issues with delay slot and CACHE Fredrik Noring 2018-02-11 11:07 ` Aw: " "Jürgen Urban" 2018-02-11 8:29 ` [RFC] MIPS: R5900: Use mandatory SYNC.L in exception handlers Fredrik Noring 2018-02-11 10:33 ` Aw: " "Jürgen Urban" 2018-02-12 9:22 ` Maciej W. Rozycki 2018-02-12 9:22 ` Maciej W. Rozycki 2018-02-18 10:30 ` Fredrik Noring 2018-02-17 14:43 ` [RFC] MIPS: R5900: Workaround for saving and restoring FPU registers Fredrik Noring 2018-02-17 15:18 ` Maciej W. Rozycki 2018-02-17 17:47 ` Fredrik Noring 2018-02-17 19:33 ` Maciej W. Rozycki 2018-02-18 9:26 ` [RFC] MIPS: R5900: Workaround where MSB must be 0 for the instruction cache Fredrik Noring 2018-02-18 11:08 ` [RFC] MIPS: R5900: Add mandatory SYNC.P to all M[FT]C0 instructions Fredrik Noring 2018-03-03 12:26 ` [RFC] MIPS: PS2: Interrupt request (IRQ) support Fredrik Noring 2018-03-03 13:09 ` Maciej W. Rozycki 2018-03-03 14:14 ` Fredrik Noring 2018-04-09 15:51 ` Fredrik Noring 2018-03-18 10:45 ` Fredrik Noring 2018-03-19 19:15 ` Thomas Gleixner 2018-06-18 18:52 ` [RFC v2] " Fredrik Noring 2017-10-30 17:55 ` [PATCH v2] MIPS: Add basic R5900 support Fredrik Noring 2017-11-24 10:26 ` Maciej W. Rozycki 2017-11-24 10:26 ` Maciej W. Rozycki 2017-11-24 10:39 ` Maciej W. Rozycki 2017-11-24 10:39 ` Maciej W. Rozycki 2017-09-20 14:07 ` Fredrik Noring 2017-09-21 21:07 ` Maciej W. Rozycki 2017-09-21 21:07 ` Maciej W. Rozycki 2017-09-22 16:37 ` Fredrik Noring 2017-09-22 16:37 ` Fredrik Noring 2017-09-29 23:55 ` Maciej W. Rozycki 2017-09-29 23:55 ` Maciej W. Rozycki 2017-09-30 18:26 ` Fredrik Noring 2017-10-02 9:11 ` Maciej W. Rozycki [this message] 2017-10-02 9:11 ` Maciej W. Rozycki 2017-10-03 19:49 ` Fredrik Noring 2017-10-05 19:04 ` Fredrik Noring 2017-10-06 20:28 ` Fredrik Noring 2017-10-15 16:39 ` Fredrik Noring 2017-10-17 12:23 ` Maciej W. Rozycki 2017-10-17 12:23 ` Maciej W. Rozycki 2017-10-21 18:00 ` Fredrik Noring 2017-10-23 16:10 ` Maciej W. Rozycki 2017-10-23 16:10 ` Maciej W. Rozycki 2017-09-21 18:11 ` Paul Burton 2017-09-21 18:11 ` Paul Burton 2017-09-21 19:48 ` Maciej W. Rozycki 2017-09-21 19:48 ` Maciej W. Rozycki 2017-10-29 18:42 ` Fredrik Noring
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