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From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org
Cc: mathieu.poirier@linaro.org, mike.leach@linaro.org,
	Linu Cherian <lcherian@marvell.com>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2 07/11] arm64: Add TRBE definitions
Date: Fri, 15 Jan 2021 07:22:09 +0530	[thread overview]
Message-ID: <cb73f274-c8d0-a069-e274-f8994f007315@arm.com> (raw)
In-Reply-To: <d6af6dae-f3ba-cd35-2ffb-cfbc9d222469@arm.com>



On 1/13/21 2:51 PM, Suzuki K Poulose wrote:
> On 1/13/21 4:18 AM, Anshuman Khandual wrote:
>> This adds TRBE related registers and corresponding feature macros.
>>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Mike Leach <mike.leach@linaro.org>
>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>>   arch/arm64/include/asm/sysreg.h | 49 +++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 49 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 4acff97..d60750e7 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -329,6 +329,55 @@
>>     /*** End of Statistical Profiling Extension ***/
>>   +/*
>> + * TRBE Registers
>> + */
>> +#define SYS_TRBLIMITR_EL1        sys_reg(3, 0, 9, 11, 0)
>> +#define SYS_TRBPTR_EL1            sys_reg(3, 0, 9, 11, 1)
>> +#define SYS_TRBBASER_EL1        sys_reg(3, 0, 9, 11, 2)
>> +#define SYS_TRBSR_EL1            sys_reg(3, 0, 9, 11, 3)
>> +#define SYS_TRBMAR_EL1            sys_reg(3, 0, 9, 11, 4)
>> +#define SYS_TRBTRG_EL1            sys_reg(3, 0, 9, 11, 6)
>> +#define SYS_TRBIDR_EL1            sys_reg(3, 0, 9, 11, 7)
>> +
>> +#define TRBLIMITR_LIMIT_MASK        GENMASK_ULL(51, 0)
>> +#define TRBLIMITR_LIMIT_SHIFT        12
>> +#define TRBLIMITR_NVM            BIT(5)
>> +#define TRBLIMITR_TRIG_MODE_MASK    GENMASK(1, 0)
>> +#define TRBLIMITR_TRIG_MODE_SHIFT    2
> 
> This must be 3.

Changed.

> 
> Rest looks fine to me
> 
> Suzuki

WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org
Cc: linux-kernel@vger.kernel.org, Linu Cherian <lcherian@marvell.com>,
	mathieu.poirier@linaro.org, mike.leach@linaro.org
Subject: Re: [PATCH V2 07/11] arm64: Add TRBE definitions
Date: Fri, 15 Jan 2021 07:22:09 +0530	[thread overview]
Message-ID: <cb73f274-c8d0-a069-e274-f8994f007315@arm.com> (raw)
In-Reply-To: <d6af6dae-f3ba-cd35-2ffb-cfbc9d222469@arm.com>



On 1/13/21 2:51 PM, Suzuki K Poulose wrote:
> On 1/13/21 4:18 AM, Anshuman Khandual wrote:
>> This adds TRBE related registers and corresponding feature macros.
>>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Mike Leach <mike.leach@linaro.org>
>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>>   arch/arm64/include/asm/sysreg.h | 49 +++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 49 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 4acff97..d60750e7 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -329,6 +329,55 @@
>>     /*** End of Statistical Profiling Extension ***/
>>   +/*
>> + * TRBE Registers
>> + */
>> +#define SYS_TRBLIMITR_EL1        sys_reg(3, 0, 9, 11, 0)
>> +#define SYS_TRBPTR_EL1            sys_reg(3, 0, 9, 11, 1)
>> +#define SYS_TRBBASER_EL1        sys_reg(3, 0, 9, 11, 2)
>> +#define SYS_TRBSR_EL1            sys_reg(3, 0, 9, 11, 3)
>> +#define SYS_TRBMAR_EL1            sys_reg(3, 0, 9, 11, 4)
>> +#define SYS_TRBTRG_EL1            sys_reg(3, 0, 9, 11, 6)
>> +#define SYS_TRBIDR_EL1            sys_reg(3, 0, 9, 11, 7)
>> +
>> +#define TRBLIMITR_LIMIT_MASK        GENMASK_ULL(51, 0)
>> +#define TRBLIMITR_LIMIT_SHIFT        12
>> +#define TRBLIMITR_NVM            BIT(5)
>> +#define TRBLIMITR_TRIG_MODE_MASK    GENMASK(1, 0)
>> +#define TRBLIMITR_TRIG_MODE_SHIFT    2
> 
> This must be 3.

Changed.

> 
> Rest looks fine to me
> 
> Suzuki

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  reply	other threads:[~2021-01-15  1:52 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-13  4:18 [PATCH V2 00/11] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
2021-01-13  4:18 ` Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 01/11] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 02/11] coresight: Do not scan for graph if none is present Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 03/11] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 04/11] coresight: ete: Add support for ETE sysreg access Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 05/11] coresight: ete: Add support for ETE tracing Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 06/11] dts: bindings: Document device tree bindings for ETE Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-25 19:22   ` Rob Herring
2021-01-25 19:22     ` Rob Herring
2021-01-25 22:20     ` Suzuki K Poulose
2021-01-25 22:20       ` Suzuki K Poulose
2021-01-25 23:28       ` Suzuki K Poulose
2021-01-25 23:28         ` Suzuki K Poulose
2021-01-13  4:18 ` [PATCH V2 07/11] arm64: Add TRBE definitions Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13  9:21   ` Suzuki K Poulose
2021-01-13  9:21     ` Suzuki K Poulose
2021-01-15  1:52     ` Anshuman Khandual [this message]
2021-01-15  1:52       ` Anshuman Khandual
2021-02-22 13:55   ` Catalin Marinas
2021-02-22 13:55     ` Catalin Marinas
2021-02-22 13:59     ` Catalin Marinas
2021-02-22 13:59       ` Catalin Marinas
2021-01-13  4:18 ` [PATCH V2 08/11] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13  9:43   ` Suzuki K Poulose
2021-01-13  9:43     ` Suzuki K Poulose
2021-01-15  2:36     ` Anshuman Khandual
2021-01-15  2:36       ` Anshuman Khandual
2021-01-15 12:31       ` Suzuki K Poulose
2021-01-15 12:31         ` Suzuki K Poulose
2021-01-13  4:18 ` [PATCH V2 09/11] coresight: etm-perf: Truncate the perf record if handle has no space Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13  9:48   ` Suzuki K Poulose
2021-01-13  9:48     ` Suzuki K Poulose
2021-01-13  4:18 ` [PATCH V2 10/11] coresight: sink: Add TRBE driver Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13 15:28   ` Suzuki K Poulose
2021-01-13 15:28     ` Suzuki K Poulose
2021-01-15  5:29     ` Anshuman Khandual
2021-01-15  5:29       ` Anshuman Khandual
2021-01-15 12:43       ` Suzuki K Poulose
2021-01-15 12:43         ` Suzuki K Poulose
2021-01-17 12:10         ` Anshuman Khandual
2021-01-17 12:10           ` Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 11/11] dts: bindings: Document device tree bindings for Arm TRBE Anshuman Khandual
2021-01-13  4:18   ` Anshuman Khandual
2021-01-13 15:45   ` Rob Herring
2021-01-13 15:45     ` Rob Herring
2021-01-14 10:17     ` Suzuki K Poulose
2021-01-14 10:17       ` Suzuki K Poulose
2021-01-14 14:07   ` Rob Herring
2021-01-14 14:07     ` Rob Herring
2021-01-14 14:47     ` Suzuki K Poulose
2021-01-14 14:47       ` Suzuki K Poulose

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