From: Joshua Clayton <stillcompiling@gmail.com> To: Alexandre Belloni <alexandre.belloni@free-electrons.com>, Alessandro Zummo <a.zummo@towertech.it> Cc: rtc-linux@googlegroups.com, linux-kernel@vger.kernel.org, Joshua Clayton <stillcompiling@gmail.com> Subject: [PATCH v2 1/8] rtc-pcf2123: define registers and bit macros Date: Mon, 4 Jan 2016 10:31:19 -0800 [thread overview] Message-ID: <eaa3bff3d0e00c2071e32239e8e9d5a514d65ad0.1451929910.git.stillcompiling@gmail.com> (raw) In-Reply-To: <cover.1451928661.git.stillcompiling@gmail.com> In-Reply-To: <0000-cover-letter.patch> Add defines for all 16 registers in the pcf2123. Add defines for useful bits from several registers I've tried to document all the registers, and as best as possible, all the special bits they employ Use BIT() wherever possible in the bit definitions Signed-off-by: Joshua Clayton <stillcompiling@gmail.com> --- drivers/rtc/rtc-pcf2123.c | 50 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 47 insertions(+), 3 deletions(-) diff --git a/drivers/rtc/rtc-pcf2123.c b/drivers/rtc/rtc-pcf2123.c index ea8a31c..be3ec83 100644 --- a/drivers/rtc/rtc-pcf2123.c +++ b/drivers/rtc/rtc-pcf2123.c @@ -48,6 +48,7 @@ #define DRV_VERSION "0.6" +/* REGISTERS */ #define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */ #define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */ #define PCF2123_REG_SC (0x02) /* datetime */ @@ -57,10 +58,53 @@ #define PCF2123_REG_DW (0x06) #define PCF2123_REG_MO (0x07) #define PCF2123_REG_YR (0x08) +#define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */ +#define PCF2123_REG_ALRM_HR (0x0a) +#define PCF2123_REG_ALRM_DM (0x0b) +#define PCF2123_REG_ALRM_DW (0x0c) +#define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */ +#define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */ +#define PCF2123_REG_CTDWN_TMR (0x0f) + +/* PCF2123_REG_CTRL1 BITS */ +#define CTRL1_CLEAR (0) /* Clear */ +#define CTRL1_CORR_INT BIT(1) /* Correction irq enable */ +#define CTRL1_12_HOUR BIT(2) /* 12 hour time */ +#define CTRL1_SW_RESET (BIT(3) | BIT(4) | BIT(6)) /* Software reset */ +#define CTRL1_STOP BIT(5) /* Stop the clock */ +#define CTRL1_EXT_TEST BIT(7) /* External clock test mode */ + +/* PCF2123_REG_CTRL2 BITS */ +#define CTRL2_TIE BIT(0) /* Countdown timer irq enable */ +#define CTRL2_AIE BIT(1) /* Alarm irq enable */ +#define CTRL2_TF BIT(2) /* Countdown timer flag */ +#define CTRL2_AF BIT(3) /* Alarm flag */ +#define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */ +#define CTRL2_MSF BIT(5) /* Minute or second irq flag */ +#define CTRL2_SI BIT(6) /* Second irq enable */ +#define CTRL2_MI BIT(7) /* Minute irq enable */ + +/* PCF2123_REG_SC BITS */ +#define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */ + +/* PCF2123_REG_ALRM_XX BITS */ +#define ALRM_ENABLE BIT(7) /* MN, HR, DM, or DW alarm enable */ + +/* PCF2123_REG_TMR_CLKOUT BITS */ +#define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */ +#define CD_TMR_64HZ (1) /* 64 Hz countdown timer */ +#define CD_TMR_1HZ (2) /* 1 Hz countdown timer */ +#define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */ +#define CD_TMR_TE BIT(3) /* Countdown timer enable */ + +/* PCF2123_REG_OFFSET BITS */ +#define OFFSET_SIGN_BIT BIT(6) /* 2's complement sign bit */ +#define OFFSET_COARSE BIT(7) /* Coarse mode offset */ + +/* READ/WRITE ADDRESS BITS */ +#define PCF2123_WRITE BIT(4) +#define PCF2123_READ (BIT(4) | BIT(7)) -#define PCF2123_SUBADDR (1 << 4) -#define PCF2123_WRITE ((0 << 7) | PCF2123_SUBADDR) -#define PCF2123_READ ((1 << 7) | PCF2123_SUBADDR) static struct spi_driver pcf2123_driver; -- 2.5.0
WARNING: multiple messages have this Message-ID (diff)
From: Joshua Clayton <stillcompiling@gmail.com> To: Alexandre Belloni <alexandre.belloni@free-electrons.com>, Alessandro Zummo <a.zummo@towertech.it> Cc: rtc-linux@googlegroups.com, linux-kernel@vger.kernel.org, Joshua Clayton <stillcompiling@gmail.com> Subject: [rtc-linux] [PATCH v2 1/8] rtc-pcf2123: define registers and bit macros Date: Mon, 4 Jan 2016 10:31:19 -0800 [thread overview] Message-ID: <eaa3bff3d0e00c2071e32239e8e9d5a514d65ad0.1451929910.git.stillcompiling@gmail.com> (raw) In-Reply-To: <cover.1451928661.git.stillcompiling@gmail.com> In-Reply-To: <0000-cover-letter.patch> Add defines for all 16 registers in the pcf2123. Add defines for useful bits from several registers I've tried to document all the registers, and as best as possible, all the special bits they employ Use BIT() wherever possible in the bit definitions Signed-off-by: Joshua Clayton <stillcompiling@gmail.com> --- drivers/rtc/rtc-pcf2123.c | 50 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 47 insertions(+), 3 deletions(-) diff --git a/drivers/rtc/rtc-pcf2123.c b/drivers/rtc/rtc-pcf2123.c index ea8a31c..be3ec83 100644 --- a/drivers/rtc/rtc-pcf2123.c +++ b/drivers/rtc/rtc-pcf2123.c @@ -48,6 +48,7 @@ #define DRV_VERSION "0.6" +/* REGISTERS */ #define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */ #define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */ #define PCF2123_REG_SC (0x02) /* datetime */ @@ -57,10 +58,53 @@ #define PCF2123_REG_DW (0x06) #define PCF2123_REG_MO (0x07) #define PCF2123_REG_YR (0x08) +#define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */ +#define PCF2123_REG_ALRM_HR (0x0a) +#define PCF2123_REG_ALRM_DM (0x0b) +#define PCF2123_REG_ALRM_DW (0x0c) +#define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */ +#define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */ +#define PCF2123_REG_CTDWN_TMR (0x0f) + +/* PCF2123_REG_CTRL1 BITS */ +#define CTRL1_CLEAR (0) /* Clear */ +#define CTRL1_CORR_INT BIT(1) /* Correction irq enable */ +#define CTRL1_12_HOUR BIT(2) /* 12 hour time */ +#define CTRL1_SW_RESET (BIT(3) | BIT(4) | BIT(6)) /* Software reset */ +#define CTRL1_STOP BIT(5) /* Stop the clock */ +#define CTRL1_EXT_TEST BIT(7) /* External clock test mode */ + +/* PCF2123_REG_CTRL2 BITS */ +#define CTRL2_TIE BIT(0) /* Countdown timer irq enable */ +#define CTRL2_AIE BIT(1) /* Alarm irq enable */ +#define CTRL2_TF BIT(2) /* Countdown timer flag */ +#define CTRL2_AF BIT(3) /* Alarm flag */ +#define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */ +#define CTRL2_MSF BIT(5) /* Minute or second irq flag */ +#define CTRL2_SI BIT(6) /* Second irq enable */ +#define CTRL2_MI BIT(7) /* Minute irq enable */ + +/* PCF2123_REG_SC BITS */ +#define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */ + +/* PCF2123_REG_ALRM_XX BITS */ +#define ALRM_ENABLE BIT(7) /* MN, HR, DM, or DW alarm enable */ + +/* PCF2123_REG_TMR_CLKOUT BITS */ +#define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */ +#define CD_TMR_64HZ (1) /* 64 Hz countdown timer */ +#define CD_TMR_1HZ (2) /* 1 Hz countdown timer */ +#define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */ +#define CD_TMR_TE BIT(3) /* Countdown timer enable */ + +/* PCF2123_REG_OFFSET BITS */ +#define OFFSET_SIGN_BIT BIT(6) /* 2's complement sign bit */ +#define OFFSET_COARSE BIT(7) /* Coarse mode offset */ + +/* READ/WRITE ADDRESS BITS */ +#define PCF2123_WRITE BIT(4) +#define PCF2123_READ (BIT(4) | BIT(7)) -#define PCF2123_SUBADDR (1 << 4) -#define PCF2123_WRITE ((0 << 7) | PCF2123_SUBADDR) -#define PCF2123_READ ((1 << 7) | PCF2123_SUBADDR) static struct spi_driver pcf2123_driver; -- 2.5.0 -- -- You received this message because you are subscribed to "rtc-linux". Membership options at http://groups.google.com/group/rtc-linux . Please read http://groups.google.com/group/rtc-linux/web/checklist before submitting a driver. --- You received this message because you are subscribed to the Google Groups "rtc-linux" group. To unsubscribe from this group and stop receiving emails from it, send an email to rtc-linux+unsubscribe@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
next prev parent reply other threads:[~2016-01-04 18:34 UTC|newest] Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-01-04 18:31 [PATCH v2 0/8] rtc: enable adjustment of clock offset Joshua Clayton 2016-01-04 18:31 ` [rtc-linux] " Joshua Clayton [not found] ` <0000-cover-letter.patch> 2016-01-04 18:31 ` Joshua Clayton [this message] 2016-01-04 18:31 ` [rtc-linux] [PATCH v2 1/8] rtc-pcf2123: define registers and bit macros Joshua Clayton 2016-01-04 18:31 ` [PATCH v2 2/8] rtc-pcf2123: clean up reads from the chip Joshua Clayton 2016-01-04 18:31 ` [rtc-linux] " Joshua Clayton 2016-01-04 18:31 ` [PATCH v2 3/8] rtc-pcf2123: clean up writes to the rtc chip Joshua Clayton 2016-01-04 18:31 ` [rtc-linux] " Joshua Clayton 2016-01-04 18:31 ` [PATCH v2 4/8] rtc-pcf2123: refactor chip reset into a function Joshua Clayton 2016-01-04 18:31 ` [rtc-linux] " Joshua Clayton 2016-01-04 18:31 ` [PATCH v2 5/8] rtc-pcf2123: avoid resetting the clock if possible Joshua Clayton 2016-01-04 18:31 ` [rtc-linux] " Joshua Clayton 2016-01-04 18:31 ` [PATCH v2 6/8] rtc: Add functions to set and read clock offset Joshua Clayton 2016-01-04 18:31 ` [rtc-linux] " Joshua Clayton 2016-01-04 18:31 ` [PATCH v2 7/8] rtc: implement a sysfs interface for " Joshua Clayton 2016-01-04 18:31 ` [rtc-linux] " Joshua Clayton 2016-01-31 11:41 ` Alexandre Belloni 2016-01-31 11:41 ` [rtc-linux] " Alexandre Belloni 2016-02-01 20:56 ` Joshua Clayton 2016-02-01 20:56 ` [rtc-linux] " Joshua Clayton 2016-02-02 10:41 ` Alexandre Belloni 2016-02-02 10:41 ` [rtc-linux] " Alexandre Belloni 2016-02-03 17:16 ` [PATCH v3 1/3] rtc: Add functions to set and read rtc offset Joshua Clayton 2016-02-03 17:16 ` [rtc-linux] " Joshua Clayton 2016-02-04 22:07 ` Alexandre Belloni 2016-02-04 22:07 ` [rtc-linux] " Alexandre Belloni 2016-02-04 23:32 ` Joshua Clayton 2016-02-04 23:32 ` [rtc-linux] " Joshua Clayton 2016-02-05 14:39 ` Alexandre Belloni 2016-02-05 14:39 ` [rtc-linux] " Alexandre Belloni 2016-02-05 20:41 ` [PATCH v4 " Joshua Clayton 2016-02-05 20:41 ` [rtc-linux] " Joshua Clayton 2016-02-05 20:41 ` [PATCH v4 2/3] rtc: implement a sysfs interface for clock offset Joshua Clayton 2016-02-05 20:41 ` [rtc-linux] " Joshua Clayton 2016-02-05 20:41 ` [PATCH v4 3/3] rtc-pcf2123: implement read_offset and set_offset Joshua Clayton 2016-02-05 20:41 ` [rtc-linux] " Joshua Clayton 2016-02-23 18:47 ` [PATCH v4 1/3] rtc: Add functions to set and read rtc offset Joshua Clayton 2016-02-23 18:47 ` [rtc-linux] " Joshua Clayton 2016-02-23 21:44 ` Alexandre Belloni 2016-02-23 21:44 ` [rtc-linux] " Alexandre Belloni 2016-02-03 17:16 ` [PATCH v3 2/3] rtc: implement a sysfs interface for clock offset Joshua Clayton 2016-02-03 17:16 ` [rtc-linux] " Joshua Clayton 2016-02-04 22:12 ` Alexandre Belloni 2016-02-04 22:12 ` [rtc-linux] " Alexandre Belloni 2016-02-03 17:16 ` [PATCH v3 3/3] rtc-pcf2123: implement read_offset and set_offset Joshua Clayton 2016-02-03 17:16 ` [rtc-linux] " Joshua Clayton 2016-01-04 18:31 ` [PATCH v2 8/8] " Joshua Clayton 2016-01-04 18:31 ` [rtc-linux] " Joshua Clayton 2016-01-29 18:21 ` [PATCH v6 1/8] eal: pci: add api to rd/wr pci bar region Santosh Shukla 2016-01-29 18:21 ` [PATCH v6 2/8] linuxapp/vfio: ignore mapping for ioport region Santosh Shukla 2016-01-29 18:21 ` [PATCH v6 3/8] eal/linux: never check iopl for arm Santosh Shukla 2016-01-29 18:21 ` [PATCH v6 4/8] virtio: Introduce config RTE_VIRTIO_INC_VECTOR Santosh Shukla 2016-01-29 18:21 ` [PATCH v6 5/8] virtio: move io header and api from virtio_pci.h Santosh Shukla 2016-01-29 18:21 ` [PATCH v6 6/8] virtio: add vfio api to rd/wr ioport space Santosh Shukla 2016-02-01 12:48 ` Yuanhan Liu 2016-02-02 4:30 ` Santosh Shukla 2016-02-02 5:19 ` Yuanhan Liu 2016-02-02 6:02 ` Santosh Shukla 2016-01-29 18:21 ` [PATCH v6 7/8] virtio: extend pci rw api for vfio Santosh Shukla 2016-01-29 18:21 ` [PATCH v6 8/8] virtio: do not parse if interface is vfio Santosh Shukla 2016-02-01 13:48 ` [PATCH v6 1/8] eal: pci: add api to rd/wr pci bar region Yuanhan Liu 2016-02-02 4:14 ` Santosh Shukla 2016-02-02 5:43 ` Yuanhan Liu 2016-02-02 5:50 ` David Marchand 2016-02-02 8:49 ` Yuanhan Liu 2016-02-02 15:51 ` Santosh Shukla 2016-02-02 16:18 ` Santosh Shukla 2016-02-03 9:50 ` Santosh Shukla 2016-02-03 11:50 ` Yuanhan Liu 2016-02-05 17:56 ` David Marchand 2016-02-03 11:43 ` Yuanhan Liu 2016-02-02 7:00 ` Santosh Shukla 2016-02-02 7:01 ` Santosh Shukla 2016-02-08 10:03 ` [PATCH v8 3/4] eal/linux: vfio: ignore mapping for ioport region Santosh Shukla 2016-02-08 10:03 ` [PATCH v8 4/4] eal/linux: vfio: add pci ioport support Santosh Shukla 2016-02-08 14:13 ` Burakov, Anatoly 2016-02-09 9:04 ` David Marchand 2016-02-18 5:25 ` Santosh Shukla 2016-02-18 14:00 ` Thomas Monjalon 2016-01-26 14:56 ` [PATCH v2 0/8] rtc: enable adjustment of clock offset Joshua Clayton 2016-01-26 14:56 ` [rtc-linux] " Joshua Clayton 2016-01-26 16:00 ` Alexandre Belloni 2016-01-26 16:00 ` [rtc-linux] " Alexandre Belloni 2016-01-31 11:29 ` Alexandre Belloni 2016-01-31 11:29 ` [rtc-linux] " Alexandre Belloni
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=eaa3bff3d0e00c2071e32239e8e9d5a514d65ad0.1451929910.git.stillcompiling@gmail.com \ --to=stillcompiling@gmail.com \ --cc=a.zummo@towertech.it \ --cc=alexandre.belloni@free-electrons.com \ --cc=linux-kernel@vger.kernel.org \ --cc=rtc-linux@googlegroups.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.