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From: Mark Brown <broonie@kernel.org>
To: William Qiu <william.qiu@starfivetech.com>
Cc: devicetree@vger.kernel.org, linux-spi@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Emil Renner Berthing <kernel@esmil.dk>,
	Ziv Xu <ziv.xu@starfivetech.com>
Subject: Re: [PATCH v1 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
Date: Wed, 31 May 2023 14:20:57 +0100	[thread overview]
Message-ID: <075db1ba-e15c-4c3c-9430-99c866eca24d@sirena.org.uk> (raw)
In-Reply-To: <93ba0b97-45aa-e59d-1454-80c4f245acc0@starfivetech.com>


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On Wed, May 31, 2023 at 02:19:16PM +0800, William Qiu wrote:
> On 2023/5/30 18:33, Mark Brown wrote:

> > You could always specify a different array of clocks depending on which
> > compatible the driver sees, just like you'd conditionally request clocks
> > individually.

> 	If specify a different array of clocks depending on which compatible
> the driver sees, since there will also be clock operations in the suspend
> and resume interfaces, this can make the code look complicated.

If you store the clock count and array in the driver data that should be
fairly simple I think.

> 	as following:

> 	/* Obtain QSPI clock. */
> 	cqspi->num_clks = devm_clk_bulk_get_all(dev, &cqspi->clks);
> 	if (cqspi->num_clks < 0) {
> 		dev_err(dev, "Cannot claim QSPI clock: %u\n", cqspi->num_clks);
> 		return -EINVAL;
> 	}

> 	This way, the code will look simpler and clearer. How do you think
> about it.

I'm not clear how enable and disable would then work?

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  reply	other threads:[~2023-05-31 13:21 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-26  6:25 [PATCH v1 0/3] Add initialization of clock for StarFive JH7110 SoC William Qiu
2023-05-26  6:25 ` [PATCH v1 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks " William Qiu
2023-05-26 15:33   ` Mark Brown
2023-05-29  6:44     ` William Qiu
2023-05-30 10:02       ` Mark Brown
2023-05-31  2:24         ` William Qiu
2023-05-26  6:25 ` [PATCH v1 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI William Qiu
2023-05-26 15:36   ` Mark Brown
2023-05-29  6:44     ` William Qiu
2023-05-30  2:05       ` William Qiu
2023-05-30 10:33         ` Mark Brown
2023-05-31  6:19           ` William Qiu
2023-05-31 13:20             ` Mark Brown [this message]
2023-06-01  1:52               ` William Qiu
2023-05-26  6:25 ` [PATCH v1 3/3] riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC William Qiu

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