From: William Qiu <william.qiu@starfivetech.com>
To: <devicetree@vger.kernel.org>, <linux-spi@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>
Cc: Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Emil Renner Berthing <kernel@esmil.dk>,
Ziv Xu <ziv.xu@starfivetech.com>,
William Qiu <william.qiu@starfivetech.com>
Subject: [PATCH v1 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
Date: Fri, 26 May 2023 14:25:28 +0800 [thread overview]
Message-ID: <20230526062529.46747-3-william.qiu@starfivetech.com> (raw)
In-Reply-To: <20230526062529.46747-1-william.qiu@starfivetech.com>
Add QSPI clock operation in device probe.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
---
drivers/spi/spi-cadence-quadspi.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 6ddb2dfc0f00..c6430fb3a0a4 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1624,6 +1624,7 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi)
static int cqspi_probe(struct platform_device *pdev)
{
const struct cqspi_driver_platdata *ddata;
+ struct clk *qspi_ahb, *qspi_apb;
struct reset_control *rstc, *rstc_ocp, *rstc_ref;
struct device *dev = &pdev->dev;
struct spi_master *master;
@@ -1715,6 +1716,32 @@ static int cqspi_probe(struct platform_device *pdev)
}
if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {
+ qspi_ahb = devm_clk_get(dev, "qspi-ahb");
+ if (IS_ERR(qspi_ahb)) {
+ dev_err(dev, "Cannot claim QSPI_AHB clock.\n");
+ ret = PTR_ERR(qspi_ahb);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(qspi_ahb);
+ if (ret) {
+ dev_err(dev, "Cannot enable QSPI AHB clock.\n");
+ goto probe_clk_failed;
+ }
+
+ qspi_apb = devm_clk_get(dev, "qspi-apb");
+ if (IS_ERR(qspi_apb)) {
+ dev_err(dev, "Cannot claim QSPI_APB clock.\n");
+ ret = PTR_ERR(qspi_apb);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(qspi_apb);
+ if (ret) {
+ dev_err(dev, "Cannot enable QSPI APB clock.\n");
+ goto probe_clk_failed;
+ }
+
rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref");
if (IS_ERR(rstc_ref)) {
ret = PTR_ERR(rstc_ref);
--
2.34.1
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next prev parent reply other threads:[~2023-05-26 6:26 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-26 6:25 [PATCH v1 0/3] Add initialization of clock for StarFive JH7110 SoC William Qiu
2023-05-26 6:25 ` [PATCH v1 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks " William Qiu
2023-05-26 15:33 ` Mark Brown
2023-05-29 6:44 ` William Qiu
2023-05-30 10:02 ` Mark Brown
2023-05-31 2:24 ` William Qiu
2023-05-26 6:25 ` William Qiu [this message]
2023-05-26 15:36 ` [PATCH v1 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI Mark Brown
2023-05-29 6:44 ` William Qiu
2023-05-30 2:05 ` William Qiu
2023-05-30 10:33 ` Mark Brown
2023-05-31 6:19 ` William Qiu
2023-05-31 13:20 ` Mark Brown
2023-06-01 1:52 ` William Qiu
2023-05-26 6:25 ` [PATCH v1 3/3] riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC William Qiu
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