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From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
	anup@brainfault.org, atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: vineetg@rivosinc.com, greentime.hu@sifive.com,
	guoren@linux.alibaba.com, Andy Chiu <andy.chiu@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Heiko Stuebner <heiko.stuebner@vrull.eu>,
	Conor Dooley <conor.dooley@microchip.com>,
	Guo Ren <guoren@kernel.org>,
	Mathis Salmen <mathis.salmen@matsal.de>,
	Andrew Bresticker <abrestic@rivosinc.com>,
	Vincent Chen <vincent.chen@sifive.com>
Subject: [PATCH -next v21 13/27] riscv: signal: check fp-reserved words unconditionally
Date: Mon,  5 Jun 2023 11:07:10 +0000	[thread overview]
Message-ID: <20230605110724.21391-14-andy.chiu@sifive.com> (raw)
In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com>

In order to let kernel/user locate and identify an extension context on
the existing sigframe, we are going to utilize reserved space of fp and
encode the information there. And since the sigcontext has already
preserved a space for fp context w or w/o CONFIG_FPU, we move those
reserved words checking/setting routine back into generic code.

This commit also undone an additional logical change carried by the
refactor commit 007f5c3589578
("Refactor FPU code in signal setup/return procedures"). Originally we
did not restore fp context if restoring of gpr have failed. And it was
fine on the other side. In such way the kernel could keep the regfiles
intact, and potentially react at the failing point of restore.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
---
 arch/riscv/kernel/signal.c | 55 +++++++++++++++++++-------------------
 1 file changed, 28 insertions(+), 27 deletions(-)

diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c
index 9aff9d720590..6b4a5c90bd87 100644
--- a/arch/riscv/kernel/signal.c
+++ b/arch/riscv/kernel/signal.c
@@ -40,26 +40,13 @@ static long restore_fp_state(struct pt_regs *regs,
 {
 	long err;
 	struct __riscv_d_ext_state __user *state = &sc_fpregs->d;
-	size_t i;
 
 	err = __copy_from_user(&current->thread.fstate, state, sizeof(*state));
 	if (unlikely(err))
 		return err;
 
 	fstate_restore(current, regs);
-
-	/* We support no other extension state at this time. */
-	for (i = 0; i < ARRAY_SIZE(sc_fpregs->q.reserved); i++) {
-		u32 value;
-
-		err = __get_user(value, &sc_fpregs->q.reserved[i]);
-		if (unlikely(err))
-			break;
-		if (value != 0)
-			return -EINVAL;
-	}
-
-	return err;
+	return 0;
 }
 
 static long save_fp_state(struct pt_regs *regs,
@@ -67,20 +54,9 @@ static long save_fp_state(struct pt_regs *regs,
 {
 	long err;
 	struct __riscv_d_ext_state __user *state = &sc_fpregs->d;
-	size_t i;
 
 	fstate_save(current, regs);
 	err = __copy_to_user(state, &current->thread.fstate, sizeof(*state));
-	if (unlikely(err))
-		return err;
-
-	/* We support no other extension state at this time. */
-	for (i = 0; i < ARRAY_SIZE(sc_fpregs->q.reserved); i++) {
-		err = __put_user(0, &sc_fpregs->q.reserved[i]);
-		if (unlikely(err))
-			break;
-	}
-
 	return err;
 }
 #else
@@ -92,11 +68,30 @@ static long restore_sigcontext(struct pt_regs *regs,
 	struct sigcontext __user *sc)
 {
 	long err;
+	size_t i;
+
 	/* sc_regs is structured the same as the start of pt_regs */
 	err = __copy_from_user(regs, &sc->sc_regs, sizeof(sc->sc_regs));
+	if (unlikely(err))
+		return err;
+
 	/* Restore the floating-point state. */
-	if (has_fpu())
-		err |= restore_fp_state(regs, &sc->sc_fpregs);
+	if (has_fpu()) {
+		err = restore_fp_state(regs, &sc->sc_fpregs);
+		if (unlikely(err))
+			return err;
+	}
+
+	/* We support no other extension state at this time. */
+	for (i = 0; i < ARRAY_SIZE(sc->sc_fpregs.q.reserved); i++) {
+		u32 value;
+
+		err = __get_user(value, &sc->sc_fpregs.q.reserved[i]);
+		if (unlikely(err))
+			break;
+		if (value != 0)
+			return -EINVAL;
+	}
 	return err;
 }
 
@@ -147,11 +142,17 @@ static long setup_sigcontext(struct rt_sigframe __user *frame,
 {
 	struct sigcontext __user *sc = &frame->uc.uc_mcontext;
 	long err;
+	size_t i;
+
 	/* sc_regs is structured the same as the start of pt_regs */
 	err = __copy_to_user(&sc->sc_regs, regs, sizeof(sc->sc_regs));
 	/* Save the floating-point state. */
 	if (has_fpu())
 		err |= save_fp_state(regs, &sc->sc_fpregs);
+	/* We support no other extension state at this time. */
+	for (i = 0; i < ARRAY_SIZE(sc->sc_fpregs.q.reserved); i++)
+		err |= __put_user(0, &sc->sc_fpregs.q.reserved[i]);
+
 	return err;
 }
 
-- 
2.17.1


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  parent reply	other threads:[~2023-06-05 15:41 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-05 11:06 [PATCH -next v21 00/27] riscv: Add vector ISA support Andy Chiu
2023-06-05 11:06 ` [PATCH -next v21 01/27] riscv: Rename __switch_to_aux() -> fpu Andy Chiu
2023-06-05 11:06 ` [PATCH -next v21 02/27] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 03/27] riscv: hwprobe: Add support for probing V in RISCV_HWPROBE_KEY_IMA_EXT_0 Andy Chiu
2023-06-08 12:36   ` Heiko Stübner
2023-06-28  0:30   ` Stefan O'Rear
2023-06-28  1:56     ` Palmer Dabbelt
2023-06-28  4:53       ` Stefan O'Rear
2023-06-05 11:07 ` [PATCH -next v21 04/27] riscv: Add new csr defines related to vector extension Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 05/27] riscv: Clear vector regfile on bootup Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 06/27] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 07/27] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 08/27] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 09/27] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-06-12 14:32   ` Rémi Denis-Courmont
2023-06-13 14:19     ` Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 10/27] riscv: Add task switch support for vector Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 11/27] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-06-05 16:04   ` Conor Dooley
2023-06-08 13:58   ` Heiko Stübner
2023-06-05 11:07 ` [PATCH -next v21 12/27] riscv: Add ptrace vector support Andy Chiu
2023-06-05 11:07 ` Andy Chiu [this message]
2023-06-05 11:07 ` [PATCH -next v21 14/27] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-10-08  9:19   ` Aurelien Jarno
2023-10-08 16:23     ` Andy Chiu
2023-10-09 17:08       ` Aurelien Jarno
2023-06-05 11:07 ` [PATCH -next v21 15/27] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 16/27] riscv: signal: validate altstack to reflect Vector Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 17/27] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 18/27] riscv: kvm: Add V extension to KVM ISA Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 19/27] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 20/27] riscv: hwcap: change ELF_HWCAP to a function Andy Chiu
2023-06-05 16:24   ` Conor Dooley
2023-06-12 14:36     ` Rémi Denis-Courmont
2023-06-12 15:30       ` Conor Dooley
2023-06-05 11:07 ` [PATCH -next v21 21/27] riscv: Add prctl controls for userspace vector management Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 22/27] riscv: Add sysctl to set the default vector rule for new processes Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 23/27] riscv: detect assembler support for .option arch Andy Chiu
2023-06-05 15:48   ` Nathan Chancellor
2023-06-05 16:25     ` Conor Dooley
2024-01-21  1:13   ` Eric Biggers
2024-01-21  2:55     ` Palmer Dabbelt
2024-01-21 14:32       ` Andy Chiu
2024-01-21 18:10         ` Eric Biggers
2024-01-22 22:29           ` Nathan Chancellor
2024-01-24 21:58             ` Eric Biggers
2023-06-05 11:07 ` [PATCH -next v21 24/27] riscv: Enable Vector code to be built Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 25/27] riscv: Add documentation for Vector Andy Chiu
2023-06-12 14:40   ` Rémi Denis-Courmont
2023-06-05 11:07 ` [PATCH -next v21 26/27] selftests: Test RISC-V Vector prctl interface Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 27/27] selftests: add .gitignore file for RISC-V hwprobe Andy Chiu
2023-06-09 14:00 ` [PATCH -next v21 00/27] riscv: Add vector ISA support Palmer Dabbelt
2023-06-09 14:50 ` patchwork-bot+linux-riscv

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