From: Andy Chiu <andy.chiu@sifive.com>
To: "Andy Chiu" <andy.chiu@sifive.com>,
linux-riscv@lists.infradead.org, palmer@dabbelt.com,
anup@brainfault.org, atishp@atishpatra.org,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
vineetg@rivosinc.com, greentime.hu@sifive.com,
guoren@linux.alibaba.com,
"Vincent Chen" <vincent.chen@sifive.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Heiko Stuebner" <heiko.stuebner@vrull.eu>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Alexandre Ghiti" <alexghiti@rivosinc.com>,
"Björn Töpel" <bjorn@rivosinc.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Rob Herring" <robh@kernel.org>,
"Jisheng Zhang" <jszhang@kernel.org>,
"Wenting Zhang" <zephray@outlook.com>,
"Guo Ren" <guoren@kernel.org>,
"Andrew Bresticker" <abrestic@rivosinc.com>,
"Al Viro" <viro@zeniv.linux.org.uk>
Subject: Re: [PATCH -next v21 14/27] riscv: signal: Add sigcontext save/restore for vector
Date: Mon, 9 Oct 2023 01:23:26 +0900 [thread overview]
Message-ID: <CABgGipVQ3j+Njw1CDkD9cuDwTwR2-WqF7Y_yZt3NPipAedK_2Q@mail.gmail.com> (raw)
In-Reply-To: <ZSJ0K5JFrglyJY8o@aurel32.net>
On Sun, Oct 8, 2023 at 6:19 PM Aurelien Jarno <aurelien@aurel32.net> wrote:
>
> Hi,
>
> On 2023-06-05 11:07, Andy Chiu wrote:
> > From: Greentime Hu <greentime.hu@sifive.com>
> >
> > This patch facilitates the existing fp-reserved words for placement of
> > the first extension's context header on the user's sigframe. A context
> > header consists of a distinct magic word and the size, including the
> > header itself, of an extension on the stack. Then, the frame is followed
> > by the context of that extension, and then a header + context body for
> > another extension if exists. If there is no more extension to come, then
> > the frame must be ended with a null context header. A special case is
> > rv64gc, where the kernel support no extensions requiring to expose
> > additional regfile to the user. In such case the kernel would place the
> > null context header right after the first reserved word of
> > __riscv_q_ext_state when saving sigframe. And the kernel would check if
> > all reserved words are zeros when a signal handler returns.
> >
> > __riscv_q_ext_state---->| |<-__riscv_extra_ext_header
> > ~ ~
> > .reserved[0]--->|0 |<- .reserved
> > <-------|magic |<- .hdr
> > | |size |_______ end of sc_fpregs
> > | |ext-bdy|
> > | ~ ~
> > +)size ------->|magic |<- another context header
> > |size |
> > |ext-bdy|
> > ~ ~
> > |magic:0|<- null context header
> > |size:0 |
> >
> > The vector registers will be saved in datap pointer. The datap pointer
> > will be allocated dynamically when the task needs in kernel space. On
> > the other hand, datap pointer on the sigframe will be set right after
> > the __riscv_v_ext_state data structure.
>
> It appears that this patch somehow breaks userland, at least the rust
> compiler. This can be observed for instance by building the rust-lsd
> package in Debian, but many other rust packages are also affected:
Sorry for the time spent on pinpointing the issue. Yes, this is a bug
and we had a fix [1]. This fix was accidently not getting into the
-fixes branch, but it will. And it should be going into linux stable
as well, though I am not certain about the timing. Otherwise, this bug
may potentially break any processes which allocate a sigaltstack at an
address higher than their stack.
>
> * Failed build with kernel 6.5.3:
> https://buildd.debian.org/status/fetch.php?pkg=rust-lsd&arch=riscv64&ver=0.23.1-7%2Bb1&stamp=1696475386&raw=0
>
> * Successful build with kernel 6.4.13:
> https://buildd.debian.org/status/fetch.php?pkg=rust-lsd&arch=riscv64&ver=0.23.1-7%2Bb1&stamp=1696491025&raw=0
>
> It happens on hardware which does not have the V extension (in the above
> case on a Hifive Unmatched board). This can also be reproduced in a QEMU
> VM. Unfortunately disabling CONFIG_RISCV_ISA_V does not workaround the
> issue.
>
> It is not clear to me if it is a kernel issue or a wrong assumption on
> the rust side. Any hint on how to continue investigating?
>
> Regards
> Aurelien
>
> --
> Aurelien Jarno GPG: 4096R/1DDD8C9B
> aurelien@aurel32.net http://aurel32.net
[1]: https://yhbt.net/lore/all/mhng-7799d3a1-c12a-48e9-bb5f-e0a596892d78@palmer-ri-x1c9/
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next prev parent reply other threads:[~2023-10-08 16:23 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-05 11:06 [PATCH -next v21 00/27] riscv: Add vector ISA support Andy Chiu
2023-06-05 11:06 ` [PATCH -next v21 01/27] riscv: Rename __switch_to_aux() -> fpu Andy Chiu
2023-06-05 11:06 ` [PATCH -next v21 02/27] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 03/27] riscv: hwprobe: Add support for probing V in RISCV_HWPROBE_KEY_IMA_EXT_0 Andy Chiu
2023-06-08 12:36 ` Heiko Stübner
2023-06-28 0:30 ` Stefan O'Rear
2023-06-28 1:56 ` Palmer Dabbelt
2023-06-28 4:53 ` Stefan O'Rear
2023-06-05 11:07 ` [PATCH -next v21 04/27] riscv: Add new csr defines related to vector extension Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 05/27] riscv: Clear vector regfile on bootup Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 06/27] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 07/27] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 08/27] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 09/27] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-06-12 14:32 ` Rémi Denis-Courmont
2023-06-13 14:19 ` Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 10/27] riscv: Add task switch support for vector Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 11/27] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-06-05 16:04 ` Conor Dooley
2023-06-08 13:58 ` Heiko Stübner
2023-06-05 11:07 ` [PATCH -next v21 12/27] riscv: Add ptrace vector support Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 13/27] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 14/27] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-10-08 9:19 ` Aurelien Jarno
2023-10-08 16:23 ` Andy Chiu [this message]
2023-10-09 17:08 ` Aurelien Jarno
2023-06-05 11:07 ` [PATCH -next v21 15/27] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 16/27] riscv: signal: validate altstack to reflect Vector Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 17/27] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 18/27] riscv: kvm: Add V extension to KVM ISA Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 19/27] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 20/27] riscv: hwcap: change ELF_HWCAP to a function Andy Chiu
2023-06-05 16:24 ` Conor Dooley
2023-06-12 14:36 ` Rémi Denis-Courmont
2023-06-12 15:30 ` Conor Dooley
2023-06-05 11:07 ` [PATCH -next v21 21/27] riscv: Add prctl controls for userspace vector management Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 22/27] riscv: Add sysctl to set the default vector rule for new processes Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 23/27] riscv: detect assembler support for .option arch Andy Chiu
2023-06-05 15:48 ` Nathan Chancellor
2023-06-05 16:25 ` Conor Dooley
2024-01-21 1:13 ` Eric Biggers
2024-01-21 2:55 ` Palmer Dabbelt
2024-01-21 14:32 ` Andy Chiu
2024-01-21 18:10 ` Eric Biggers
2024-01-22 22:29 ` Nathan Chancellor
2024-01-24 21:58 ` Eric Biggers
2023-06-05 11:07 ` [PATCH -next v21 24/27] riscv: Enable Vector code to be built Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 25/27] riscv: Add documentation for Vector Andy Chiu
2023-06-12 14:40 ` Rémi Denis-Courmont
2023-06-05 11:07 ` [PATCH -next v21 26/27] selftests: Test RISC-V Vector prctl interface Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 27/27] selftests: add .gitignore file for RISC-V hwprobe Andy Chiu
2023-06-09 14:00 ` [PATCH -next v21 00/27] riscv: Add vector ISA support Palmer Dabbelt
2023-06-09 14:50 ` patchwork-bot+linux-riscv
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