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From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
	anup@brainfault.org, atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: vineetg@rivosinc.com, greentime.hu@sifive.com,
	guoren@linux.alibaba.com,
	"Vincent Chen" <vincent.chen@sifive.com>,
	"Han-Kuan Chen" <hankuan.chen@sifive.com>,
	"Andy Chiu" <andy.chiu@sifive.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Guo Ren" <guoren@kernel.org>,
	"Nicolas Saenz Julienne" <nsaenzju@redhat.com>,
	"Jisheng Zhang" <jszhang@kernel.org>,
	"Björn Töpel" <bjorn@rivosinc.com>,
	"Frederic Weisbecker" <frederic@kernel.org>,
	"Andrew Bresticker" <abrestic@rivosinc.com>,
	"Heiko Stuebner" <heiko.stuebner@vrull.eu>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Masahiro Yamada" <masahiroy@kernel.org>
Subject: [PATCH -next v21 06/27] riscv: Disable Vector Instructions for kernel itself
Date: Mon,  5 Jun 2023 11:07:03 +0000	[thread overview]
Message-ID: <20230605110724.21391-7-andy.chiu@sifive.com> (raw)
In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com>

From: Guo Ren <guoren@linux.alibaba.com>

Disable vector instructions execution for kernel mode at its entrances.
This helps find illegal uses of vector in the kernel space, which is
similar to the fpu.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Co-developed-by: Han-Kuan Chen <hankuan.chen@sifive.com>
Signed-off-by: Han-Kuan Chen <hankuan.chen@sifive.com>
Co-developed-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
---
Changelog V19:
 - Add description in commit msg (Heiko's suggestion on v17)
---
 arch/riscv/kernel/entry.S |  6 +++---
 arch/riscv/kernel/head.S  | 12 ++++++------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 3fbb100bc9e4..e9ae284a55c1 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -48,10 +48,10 @@ _save_context:
 	 * Disable user-mode memory access as it should only be set in the
 	 * actual user copy routines.
 	 *
-	 * Disable the FPU to detect illegal usage of floating point in kernel
-	 * space.
+	 * Disable the FPU/Vector to detect illegal usage of floating point
+	 * or vector in kernel space.
 	 */
-	li t0, SR_SUM | SR_FS
+	li t0, SR_SUM | SR_FS_VS
 
 	REG_L s0, TASK_TI_USER_SP(tp)
 	csrrc s1, CSR_STATUS, t0
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 3fd6a4bd9c3e..e16bb2185d55 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -140,10 +140,10 @@ secondary_start_sbi:
 	.option pop
 
 	/*
-	 * Disable FPU to detect illegal usage of
-	 * floating point in kernel space
+	 * Disable FPU & VECTOR to detect illegal usage of
+	 * floating point or vector in kernel space
 	 */
-	li t0, SR_FS
+	li t0, SR_FS_VS
 	csrc CSR_STATUS, t0
 
 	/* Set trap vector to spin forever to help debug */
@@ -234,10 +234,10 @@ pmp_done:
 .option pop
 
 	/*
-	 * Disable FPU to detect illegal usage of
-	 * floating point in kernel space
+	 * Disable FPU & VECTOR to detect illegal usage of
+	 * floating point or vector in kernel space
 	 */
-	li t0, SR_FS
+	li t0, SR_FS_VS
 	csrc CSR_STATUS, t0
 
 #ifdef CONFIG_RISCV_BOOT_SPINWAIT
-- 
2.17.1


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  parent reply	other threads:[~2023-06-05 15:40 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-05 11:06 [PATCH -next v21 00/27] riscv: Add vector ISA support Andy Chiu
2023-06-05 11:06 ` [PATCH -next v21 01/27] riscv: Rename __switch_to_aux() -> fpu Andy Chiu
2023-06-05 11:06 ` [PATCH -next v21 02/27] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 03/27] riscv: hwprobe: Add support for probing V in RISCV_HWPROBE_KEY_IMA_EXT_0 Andy Chiu
2023-06-08 12:36   ` Heiko Stübner
2023-06-28  0:30   ` Stefan O'Rear
2023-06-28  1:56     ` Palmer Dabbelt
2023-06-28  4:53       ` Stefan O'Rear
2023-06-05 11:07 ` [PATCH -next v21 04/27] riscv: Add new csr defines related to vector extension Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 05/27] riscv: Clear vector regfile on bootup Andy Chiu
2023-06-05 11:07 ` Andy Chiu [this message]
2023-06-05 11:07 ` [PATCH -next v21 07/27] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 08/27] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 09/27] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-06-12 14:32   ` Rémi Denis-Courmont
2023-06-13 14:19     ` Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 10/27] riscv: Add task switch support for vector Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 11/27] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-06-05 16:04   ` Conor Dooley
2023-06-08 13:58   ` Heiko Stübner
2023-06-05 11:07 ` [PATCH -next v21 12/27] riscv: Add ptrace vector support Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 13/27] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 14/27] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-10-08  9:19   ` Aurelien Jarno
2023-10-08 16:23     ` Andy Chiu
2023-10-09 17:08       ` Aurelien Jarno
2023-06-05 11:07 ` [PATCH -next v21 15/27] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 16/27] riscv: signal: validate altstack to reflect Vector Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 17/27] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 18/27] riscv: kvm: Add V extension to KVM ISA Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 19/27] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 20/27] riscv: hwcap: change ELF_HWCAP to a function Andy Chiu
2023-06-05 16:24   ` Conor Dooley
2023-06-12 14:36     ` Rémi Denis-Courmont
2023-06-12 15:30       ` Conor Dooley
2023-06-05 11:07 ` [PATCH -next v21 21/27] riscv: Add prctl controls for userspace vector management Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 22/27] riscv: Add sysctl to set the default vector rule for new processes Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 23/27] riscv: detect assembler support for .option arch Andy Chiu
2023-06-05 15:48   ` Nathan Chancellor
2023-06-05 16:25     ` Conor Dooley
2024-01-21  1:13   ` Eric Biggers
2024-01-21  2:55     ` Palmer Dabbelt
2024-01-21 14:32       ` Andy Chiu
2024-01-21 18:10         ` Eric Biggers
2024-01-22 22:29           ` Nathan Chancellor
2024-01-24 21:58             ` Eric Biggers
2023-06-05 11:07 ` [PATCH -next v21 24/27] riscv: Enable Vector code to be built Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 25/27] riscv: Add documentation for Vector Andy Chiu
2023-06-12 14:40   ` Rémi Denis-Courmont
2023-06-05 11:07 ` [PATCH -next v21 26/27] selftests: Test RISC-V Vector prctl interface Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 27/27] selftests: add .gitignore file for RISC-V hwprobe Andy Chiu
2023-06-09 14:00 ` [PATCH -next v21 00/27] riscv: Add vector ISA support Palmer Dabbelt
2023-06-09 14:50 ` patchwork-bot+linux-riscv

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