* [PATCH v3 1/6] riscv: dts: microchip: convert isa detection to new properties
2023-10-09 9:37 [PATCH v3 0/6] riscv,isa-extensions additions Conor Dooley
@ 2023-10-09 9:37 ` Conor Dooley
2023-10-09 9:37 ` [PATCH v3 2/6] riscv: dts: sifive: " Conor Dooley
` (6 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Conor Dooley @ 2023-10-09 9:37 UTC (permalink / raw)
To: linux-riscv
Cc: conor, conor.dooley, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Daire McNamara,
Geert Uytterhoeven, Magnus Damm, Emil Renner Berthing,
Jisheng Zhang, Guo Ren, Fu Wei, Chen Wang, devicetree,
linux-riscv, linux-sunxi, linux-renesas-soc
Convert the PolarFire SoC devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/microchip/mpfs.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 104504352e99..a6faf24f1dba 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -22,6 +22,9 @@ cpu0: cpu@0 {
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
+ "zihpm";
clocks = <&clkcfg CLK_CPU>;
status = "disabled";
@@ -48,6 +51,9 @@ cpu1: cpu@1 {
mmu-type = "riscv,sv39";
reg = <1>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
@@ -76,6 +82,9 @@ cpu2: cpu@2 {
mmu-type = "riscv,sv39";
reg = <2>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
@@ -104,6 +113,9 @@ cpu3: cpu@3 {
mmu-type = "riscv,sv39";
reg = <3>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
@@ -132,6 +144,9 @@ cpu4: cpu@4 {
mmu-type = "riscv,sv39";
reg = <4>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
--
2.40.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 2/6] riscv: dts: sifive: convert isa detection to new properties
2023-10-09 9:37 [PATCH v3 0/6] riscv,isa-extensions additions Conor Dooley
2023-10-09 9:37 ` [PATCH v3 1/6] riscv: dts: microchip: convert isa detection to new properties Conor Dooley
@ 2023-10-09 9:37 ` Conor Dooley
2023-10-09 9:37 ` [PATCH v3 3/6] riscv: dts: starfive: " Conor Dooley
` (5 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Conor Dooley @ 2023-10-09 9:37 UTC (permalink / raw)
To: linux-riscv
Cc: Emil Renner Berthing, Geert Uytterhoeven, conor.dooley, Guo Ren,
Krzysztof Kozlowski, linux-riscv, Samuel Holland, Chen Wang,
Magnus Damm, Jernej Skrabec, Chen-Yu Tsai, linux-sunxi,
devicetree, Conor Dooley, Albert Ou, Rob Herring, Paul Walmsley,
Jisheng Zhang, Daire McNamara, conor, linux-renesas-soc,
Palmer Dabbelt, Fu Wei
Convert the fu540 and fu740 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 15 +++++++++++++++
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 15 +++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 24bba83bec77..156330a9bbf3 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -30,6 +30,9 @@ cpu0: cpu@0 {
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
+ "zihpm";
status = "disabled";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -53,6 +56,9 @@ cpu1: cpu@1 {
mmu-type = "riscv,sv39";
reg = <1>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
tlb-split;
next-level-cache = <&l2cache>;
cpu1_intc: interrupt-controller {
@@ -77,6 +83,9 @@ cpu2: cpu@2 {
mmu-type = "riscv,sv39";
reg = <2>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
tlb-split;
next-level-cache = <&l2cache>;
cpu2_intc: interrupt-controller {
@@ -101,6 +110,9 @@ cpu3: cpu@3 {
mmu-type = "riscv,sv39";
reg = <3>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
tlb-split;
next-level-cache = <&l2cache>;
cpu3_intc: interrupt-controller {
@@ -125,6 +137,9 @@ cpu4: cpu@4 {
mmu-type = "riscv,sv39";
reg = <4>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
tlb-split;
next-level-cache = <&l2cache>;
cpu4_intc: interrupt-controller {
diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
index 5235fd1c9cb6..6150f3397bff 100644
--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
@@ -31,6 +31,9 @@ cpu0: cpu@0 {
next-level-cache = <&ccache>;
reg = <0x0>;
riscv,isa = "rv64imac";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
+ "zihpm";
status = "disabled";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -55,6 +58,9 @@ cpu1: cpu@1 {
next-level-cache = <&ccache>;
reg = <0x1>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
tlb-split;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -79,6 +85,9 @@ cpu2: cpu@2 {
next-level-cache = <&ccache>;
reg = <0x2>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
tlb-split;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -103,6 +112,9 @@ cpu3: cpu@3 {
next-level-cache = <&ccache>;
reg = <0x3>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
tlb-split;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -127,6 +139,9 @@ cpu4: cpu@4 {
next-level-cache = <&ccache>;
reg = <0x4>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
tlb-split;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
--
2.40.1
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 3/6] riscv: dts: starfive: convert isa detection to new properties
2023-10-09 9:37 [PATCH v3 0/6] riscv,isa-extensions additions Conor Dooley
2023-10-09 9:37 ` [PATCH v3 1/6] riscv: dts: microchip: convert isa detection to new properties Conor Dooley
2023-10-09 9:37 ` [PATCH v3 2/6] riscv: dts: sifive: " Conor Dooley
@ 2023-10-09 9:37 ` Conor Dooley
2023-10-09 9:37 ` [PATCH v3 4/6] riscv: dts: renesas: " Conor Dooley
` (4 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Conor Dooley @ 2023-10-09 9:37 UTC (permalink / raw)
To: linux-riscv
Cc: conor, conor.dooley, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Daire McNamara,
Geert Uytterhoeven, Magnus Damm, Emil Renner Berthing,
Jisheng Zhang, Guo Ren, Fu Wei, Chen Wang, devicetree,
linux-riscv, linux-sunxi, linux-renesas-soc
Convert the jh7100 and jh7110 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/starfive/jh7100.dtsi | 6 ++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 35ab54fb235f..e68cafe7545f 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -33,6 +33,9 @@ U74_0: cpu@0 {
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
tlb-split;
cpu0_intc: interrupt-controller {
@@ -58,6 +61,9 @@ U74_1: cpu@1 {
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
tlb-split;
cpu1_intc: interrupt-controller {
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 9f31dec57c0d..45213cdf50dc 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -28,6 +28,9 @@ S7_0: cpu@0 {
i-cache-size = <16384>;
next-level-cache = <&ccache>;
riscv,isa = "rv64imac_zba_zbb";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr",
+ "zifencei", "zihpm";
status = "disabled";
cpu0_intc: interrupt-controller {
@@ -54,6 +57,9 @@ U74_1: cpu@1 {
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
+ "zicsr", "zifencei", "zihpm";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
@@ -84,6 +90,9 @@ U74_2: cpu@2 {
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
+ "zicsr", "zifencei", "zihpm";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
@@ -114,6 +123,9 @@ U74_3: cpu@3 {
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
+ "zicsr", "zifencei", "zihpm";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
@@ -144,6 +156,9 @@ U74_4: cpu@4 {
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
+ "zicsr", "zifencei", "zihpm";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
--
2.40.1
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 4/6] riscv: dts: renesas: convert isa detection to new properties
2023-10-09 9:37 [PATCH v3 0/6] riscv,isa-extensions additions Conor Dooley
` (2 preceding siblings ...)
2023-10-09 9:37 ` [PATCH v3 3/6] riscv: dts: starfive: " Conor Dooley
@ 2023-10-09 9:37 ` Conor Dooley
2023-10-09 12:15 ` Geert Uytterhoeven
2023-10-16 6:09 ` Yu-Chien Peter Lin
2023-10-09 9:37 ` [PATCH v3 5/6] riscv: dts: allwinner: " Conor Dooley
` (3 subsequent siblings)
7 siblings, 2 replies; 16+ messages in thread
From: Conor Dooley @ 2023-10-09 9:37 UTC (permalink / raw)
To: linux-riscv
Cc: conor, conor.dooley, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Daire McNamara,
Geert Uytterhoeven, Magnus Damm, Emil Renner Berthing,
Jisheng Zhang, Guo Ren, Fu Wei, Chen Wang, devicetree,
linux-riscv, linux-sunxi, linux-renesas-soc
Convert the RZ/Five devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index b0796015e36b..eb301d8eb2b0 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -24,6 +24,9 @@ cpu0: cpu@0 {
reg = <0x0>;
status = "okay";
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
mmu-type = "riscv,sv39";
i-cache-size = <0x8000>;
i-cache-line-size = <0x40>;
--
2.40.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v3 4/6] riscv: dts: renesas: convert isa detection to new properties
2023-10-09 9:37 ` [PATCH v3 4/6] riscv: dts: renesas: " Conor Dooley
@ 2023-10-09 12:15 ` Geert Uytterhoeven
2023-10-09 16:16 ` Conor Dooley
2023-10-16 6:09 ` Yu-Chien Peter Lin
1 sibling, 1 reply; 16+ messages in thread
From: Geert Uytterhoeven @ 2023-10-09 12:15 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-riscv, conor, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Daire McNamara,
Geert Uytterhoeven, Magnus Damm, Emil Renner Berthing,
Jisheng Zhang, Guo Ren, Fu Wei, Chen Wang, devicetree,
linux-riscv, linux-sunxi, linux-renesas-soc
Hi Conor,
On Mon, Oct 9, 2023 at 11:44 AM Conor Dooley <conor.dooley@microchip.com> wrote:
> Convert the RZ/Five devicetrees to use the new properties
> "riscv,isa-base" & "riscv,isa-extensions".
> For compatibility with other projects, "riscv,isa" remains.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Thanks for your patch!
> --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> @@ -24,6 +24,9 @@ cpu0: cpu@0 {
> reg = <0x0>;
> status = "okay";
> riscv,isa = "rv64imafdc";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> + "zifencei", "zihpm";
LGMT, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
I could not review the "zi*" parts, as the documentation that I have
does not mention these.
> mmu-type = "riscv,sv39";
> i-cache-size = <0x8000>;
> i-cache-line-size = <0x40>;
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v3 4/6] riscv: dts: renesas: convert isa detection to new properties
2023-10-09 12:15 ` Geert Uytterhoeven
@ 2023-10-09 16:16 ` Conor Dooley
0 siblings, 0 replies; 16+ messages in thread
From: Conor Dooley @ 2023-10-09 16:16 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Daire McNamara,
Geert Uytterhoeven, Magnus Damm, Emil Renner Berthing,
Jisheng Zhang, Guo Ren, Fu Wei, Chen Wang, devicetree,
linux-riscv, linux-sunxi, linux-renesas-soc
[-- Attachment #1.1: Type: text/plain, Size: 1997 bytes --]
On Mon, Oct 09, 2023 at 02:15:47PM +0200, Geert Uytterhoeven wrote:
> Hi Conor,
>
> On Mon, Oct 9, 2023 at 11:44 AM Conor Dooley <conor.dooley@microchip.com> wrote:
> > Convert the RZ/Five devicetrees to use the new properties
> > "riscv,isa-base" & "riscv,isa-extensions".
> > For compatibility with other projects, "riscv,isa" remains.
> >
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>
> Thanks for your patch!
>
> > --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > @@ -24,6 +24,9 @@ cpu0: cpu@0 {
> > reg = <0x0>;
> > status = "okay";
> > riscv,isa = "rv64imafdc";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > + "zifencei", "zihpm";
>
> LGMT, so
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> I could not review the "zi*" parts, as the documentation that I have
> does not mention these.
These are effectively the assumptions that the kernel already makes, for
things that used to be part of the base isa (or were assumed to be) that
are now extensions in their own right.
The Zihpm it'd be good if someone from the Renesas or Andes sides could
confirm though.
Cheers,
Conor.
>
> > mmu-type = "riscv,sv39";
> > i-cache-size = <0x8000>;
> > i-cache-line-size = <0x40>;
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 4/6] riscv: dts: renesas: convert isa detection to new properties
2023-10-09 9:37 ` [PATCH v3 4/6] riscv: dts: renesas: " Conor Dooley
2023-10-09 12:15 ` Geert Uytterhoeven
@ 2023-10-16 6:09 ` Yu-Chien Peter Lin
2023-10-16 7:17 ` Geert Uytterhoeven
1 sibling, 1 reply; 16+ messages in thread
From: Yu-Chien Peter Lin @ 2023-10-16 6:09 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-riscv, conor, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Daire McNamara,
Geert Uytterhoeven, Magnus Damm, Emil Renner Berthing,
Jisheng Zhang, Guo Ren, Fu Wei, Chen Wang, devicetree,
linux-riscv, linux-sunxi, linux-renesas-soc
On Mon, Oct 09, 2023 at 10:37:48AM +0100, Conor Dooley wrote:
> Convert the RZ/Five devicetrees to use the new properties
> "riscv,isa-base" & "riscv,isa-extensions".
> For compatibility with other projects, "riscv,isa" remains.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> index b0796015e36b..eb301d8eb2b0 100644
> --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> @@ -24,6 +24,9 @@ cpu0: cpu@0 {
> reg = <0x0>;
> status = "okay";
> riscv,isa = "rv64imafdc";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> + "zifencei", "zihpm";
We do have zihpm, and OpenSBI can also probe its existence.
Boot HART ISA Extensions : zihpm
Boot HART MHPM Info : 4 (0x00000078)
By the way, we will append "xandespmu" here.
I hope this is an appropriate way to add a new custom extension.
> mmu-type = "riscv,sv39";
> i-cache-size = <0x8000>;
> i-cache-line-size = <0x40>;
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^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v3 4/6] riscv: dts: renesas: convert isa detection to new properties
2023-10-16 6:09 ` Yu-Chien Peter Lin
@ 2023-10-16 7:17 ` Geert Uytterhoeven
0 siblings, 0 replies; 16+ messages in thread
From: Geert Uytterhoeven @ 2023-10-16 7:17 UTC (permalink / raw)
To: Yu-Chien Peter Lin
Cc: Conor Dooley, linux-riscv, conor, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland,
Daire McNamara, Geert Uytterhoeven, Magnus Damm,
Emil Renner Berthing, Jisheng Zhang, Guo Ren, Fu Wei, Chen Wang,
devicetree, linux-riscv, linux-sunxi, linux-renesas-soc
Hi Yu-Chien,
On Mon, Oct 16, 2023 at 8:10 AM Yu-Chien Peter Lin
<peterlin@andestech.com> wrote:
> On Mon, Oct 09, 2023 at 10:37:48AM +0100, Conor Dooley wrote:
> > Convert the RZ/Five devicetrees to use the new properties
> > "riscv,isa-base" & "riscv,isa-extensions".
> > For compatibility with other projects, "riscv,isa" remains.
> >
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > ---
> > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > index b0796015e36b..eb301d8eb2b0 100644
> > --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > @@ -24,6 +24,9 @@ cpu0: cpu@0 {
> > reg = <0x0>;
> > status = "okay";
> > riscv,isa = "rv64imafdc";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > + "zifencei", "zihpm";
>
> We do have zihpm, and OpenSBI can also probe its existence.
>
> Boot HART ISA Extensions : zihpm
> Boot HART MHPM Info : 4 (0x00000078)
Thank you, I hadn't digested the full output from OpenSBI yet, and
I can confirm this is present in that output.
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 5/6] riscv: dts: allwinner: convert isa detection to new properties
2023-10-09 9:37 [PATCH v3 0/6] riscv,isa-extensions additions Conor Dooley
` (3 preceding siblings ...)
2023-10-09 9:37 ` [PATCH v3 4/6] riscv: dts: renesas: " Conor Dooley
@ 2023-10-09 9:37 ` Conor Dooley
2023-10-13 19:22 ` Jernej Škrabec
2023-10-09 9:37 ` [PATCH v3 6/6] riscv: dts: thead: " Conor Dooley
` (2 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Conor Dooley @ 2023-10-09 9:37 UTC (permalink / raw)
To: linux-riscv
Cc: conor, conor.dooley, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Daire McNamara,
Geert Uytterhoeven, Magnus Damm, Emil Renner Berthing,
Jisheng Zhang, Guo Ren, Fu Wei, Chen Wang, devicetree,
linux-riscv, linux-sunxi, linux-renesas-soc
Convert the D1 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
index 0856f18dc3cf..64c3c2e6cbe0 100644
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
@@ -25,6 +25,9 @@ cpu0: cpu@0 {
mmu-type = "riscv,sv39";
operating-points-v2 = <&opp_table_cpu>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
#cooling-cells = <2>;
cpu0_intc: interrupt-controller {
--
2.40.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v3 5/6] riscv: dts: allwinner: convert isa detection to new properties
2023-10-09 9:37 ` [PATCH v3 5/6] riscv: dts: allwinner: " Conor Dooley
@ 2023-10-13 19:22 ` Jernej Škrabec
0 siblings, 0 replies; 16+ messages in thread
From: Jernej Škrabec @ 2023-10-13 19:22 UTC (permalink / raw)
To: linux-riscv, Conor Dooley
Cc: conor, conor.dooley, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Chen-Yu Tsai, Samuel Holland, Daire McNamara, Geert Uytterhoeven,
Magnus Damm, Emil Renner Berthing, Jisheng Zhang, Guo Ren,
Fu Wei, Chen Wang, devicetree, linux-riscv, linux-sunxi,
linux-renesas-soc
Dne ponedeljek, 09. oktober 2023 ob 11:37:49 CEST je Conor Dooley napisal(a):
> Convert the D1 devicetrees to use the new properties
> "riscv,isa-base" & "riscv,isa-extensions".
> For compatibility with other projects, "riscv,isa" remains.
>
> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Applied, thanks!
Best regards,
Jernej
> ---
> arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> index 0856f18dc3cf..64c3c2e6cbe0 100644
> --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> @@ -25,6 +25,9 @@ cpu0: cpu@0 {
> mmu-type = "riscv,sv39";
> operating-points-v2 = <&opp_table_cpu>;
> riscv,isa = "rv64imafdc";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> + "zifencei", "zihpm";
> #cooling-cells = <2>;
>
> cpu0_intc: interrupt-controller {
>
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^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 6/6] riscv: dts: thead: convert isa detection to new properties
2023-10-09 9:37 [PATCH v3 0/6] riscv,isa-extensions additions Conor Dooley
` (4 preceding siblings ...)
2023-10-09 9:37 ` [PATCH v3 5/6] riscv: dts: allwinner: " Conor Dooley
@ 2023-10-09 9:37 ` Conor Dooley
2023-10-15 12:22 ` (subset) [PATCH v3 0/6] riscv,isa-extensions additions Conor Dooley
2023-11-12 0:55 ` patchwork-bot+linux-riscv
7 siblings, 0 replies; 16+ messages in thread
From: Conor Dooley @ 2023-10-09 9:37 UTC (permalink / raw)
To: linux-riscv
Cc: conor, conor.dooley, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Daire McNamara,
Geert Uytterhoeven, Magnus Damm, Emil Renner Berthing,
Jisheng Zhang, Guo Ren, Fu Wei, Chen Wang, devicetree,
linux-riscv, linux-sunxi, linux-renesas-soc
Convert the th1520 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index ce708183b6f6..723f65487246 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -20,6 +20,9 @@ c910_0: cpu@0 {
compatible = "thead,c910", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
reg = <0>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -41,6 +44,9 @@ c910_1: cpu@1 {
compatible = "thead,c910", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
reg = <1>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -62,6 +68,9 @@ c910_2: cpu@2 {
compatible = "thead,c910", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
reg = <2>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -83,6 +92,9 @@ c910_3: cpu@3 {
compatible = "thead,c910", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
reg = <3>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
--
2.40.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: (subset) [PATCH v3 0/6] riscv,isa-extensions additions
2023-10-09 9:37 [PATCH v3 0/6] riscv,isa-extensions additions Conor Dooley
` (5 preceding siblings ...)
2023-10-09 9:37 ` [PATCH v3 6/6] riscv: dts: thead: " Conor Dooley
@ 2023-10-15 12:22 ` Conor Dooley
2023-10-16 7:23 ` Geert Uytterhoeven
2023-11-12 0:55 ` patchwork-bot+linux-riscv
7 siblings, 1 reply; 16+ messages in thread
From: Conor Dooley @ 2023-10-15 12:22 UTC (permalink / raw)
To: linux-riscv, Conor Dooley
Cc: conor, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Daire McNamara,
Geert Uytterhoeven, Magnus Damm, Emil Renner Berthing,
Jisheng Zhang, Guo Ren, Fu Wei, Chen Wang, devicetree,
linux-riscv, linux-sunxi, linux-renesas-soc
From: Conor Dooley <conor.dooley@microchip.com>
On Mon, 09 Oct 2023 10:37:44 +0100, Conor Dooley wrote:
> Now with the RFC tag dropped. There are no changes here from "RFC v2",
> other than the addition of tags that were provided along the way. I have
> not added "Zfh" to the T-Head based stuff, as I can't actually read the
> documentation that would show that they're encoding-for-encoding
> compatible with the standard extension, since it is apparently only in
> Chinese.
>
> [...]
The first 3 applied to riscv-dt-for-next, I expect the rest to go via
their respective platform maintainers.
[1/6] riscv: dts: microchip: convert isa detection to new properties
https://git.kernel.org/conor/c/561add0da6d3
[2/6] riscv: dts: sifive: convert isa detection to new properties
https://git.kernel.org/conor/c/a54f42722e49
[3/6] riscv: dts: starfive: convert isa detection to new properties
https://git.kernel.org/conor/c/81b5948cf1a7
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 16+ messages in thread* Re: (subset) [PATCH v3 0/6] riscv,isa-extensions additions
2023-10-15 12:22 ` (subset) [PATCH v3 0/6] riscv,isa-extensions additions Conor Dooley
@ 2023-10-16 7:23 ` Geert Uytterhoeven
2023-10-16 8:09 ` Conor Dooley
0 siblings, 1 reply; 16+ messages in thread
From: Geert Uytterhoeven @ 2023-10-16 7:23 UTC (permalink / raw)
To: Conor Dooley
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Daire McNamara,
Geert Uytterhoeven, Magnus Damm, Emil Renner Berthing,
Jisheng Zhang, Guo Ren, Fu Wei, Chen Wang, devicetree,
linux-riscv, linux-sunxi, linux-renesas-soc
Hi Conor,
On Sun, Oct 15, 2023 at 2:22 PM Conor Dooley <conor@kernel.org> wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> On Mon, 09 Oct 2023 10:37:44 +0100, Conor Dooley wrote:
> > Now with the RFC tag dropped. There are no changes here from "RFC v2",
> > other than the addition of tags that were provided along the way. I have
> > not added "Zfh" to the T-Head based stuff, as I can't actually read the
> > documentation that would show that they're encoding-for-encoding
> > compatible with the standard extension, since it is apparently only in
> > Chinese.
> >
> > [...]
>
> The first 3 applied to riscv-dt-for-next, I expect the rest to go via
> their respective platform maintainers.
I sent my last soc PR for v6.7 last Friday, as per the soc deadline.
Feel free to take "[PATCH v3 4/6] riscv: dts: renesas: convert isa
detection to new properties" into your tree for v6, if that is still
possible (I have just provided my Acked-by). Otherwise, I can queue
it in renesas-devel for v6.8.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-riscv mailing list
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: (subset) [PATCH v3 0/6] riscv,isa-extensions additions
2023-10-16 7:23 ` Geert Uytterhoeven
@ 2023-10-16 8:09 ` Conor Dooley
0 siblings, 0 replies; 16+ messages in thread
From: Conor Dooley @ 2023-10-16 8:09 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Daire McNamara,
Geert Uytterhoeven, Magnus Damm, Emil Renner Berthing,
Jisheng Zhang, Guo Ren, Fu Wei, Chen Wang, devicetree,
linux-riscv, linux-sunxi, linux-renesas-soc
[-- Attachment #1.1: Type: text/plain, Size: 833 bytes --]
On Mon, Oct 16, 2023 at 09:23:23AM +0200, Geert Uytterhoeven wrote:
> On Sun, Oct 15, 2023 at 2:22 PM Conor Dooley <conor@kernel.org> wrote:
> > The first 3 applied to riscv-dt-for-next, I expect the rest to go via
> > their respective platform maintainers.
>
> I sent my last soc PR for v6.7 last Friday, as per the soc deadline.
I was going to send mine this afternoon :)
> Feel free to take "[PATCH v3 4/6] riscv: dts: renesas: convert isa
> detection to new properties" into your tree for v6, if that is still
> possible (I have just provided my Acked-by). Otherwise, I can queue
> it in renesas-devel for v6.8.
I was expecting them to end up in v6.8 since it's pretty late & I don't
really want to send a PR with stuff that hasn't been in linux-next.
Queuing it renesas-devel sounds good to me, thanks!
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/6] riscv,isa-extensions additions
2023-10-09 9:37 [PATCH v3 0/6] riscv,isa-extensions additions Conor Dooley
` (6 preceding siblings ...)
2023-10-15 12:22 ` (subset) [PATCH v3 0/6] riscv,isa-extensions additions Conor Dooley
@ 2023-11-12 0:55 ` patchwork-bot+linux-riscv
7 siblings, 0 replies; 16+ messages in thread
From: patchwork-bot+linux-riscv @ 2023-11-12 0:55 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-riscv, linux-riscv, conor, robh+dt, krzysztof.kozlowski+dt,
conor+dt, paul.walmsley, palmer, aou, wens, jernej.skrabec,
samuel, daire.mcnamara, geert+renesas, magnus.damm, kernel,
jszhang, guoren, wefu, unicorn_wang, devicetree, linux-sunxi,
linux-renesas-soc
Hello:
This series was applied to riscv/linux.git (fixes)
by Arnd Bergmann <arnd@arndb.de>:
On Mon, 9 Oct 2023 10:37:44 +0100 you wrote:
> Now with the RFC tag dropped. There are no changes here from "RFC v2",
> other than the addition of tags that were provided along the way. I have
> not added "Zfh" to the T-Head based stuff, as I can't actually read the
> documentation that would show that they're encoding-for-encoding
> compatible with the standard extension, since it is apparently only in
> Chinese.
>
> [...]
Here is the summary with links:
- [v3,1/6] riscv: dts: microchip: convert isa detection to new properties
(no matching commit)
- [v3,2/6] riscv: dts: sifive: convert isa detection to new properties
(no matching commit)
- [v3,3/6] riscv: dts: starfive: convert isa detection to new properties
(no matching commit)
- [v3,4/6] riscv: dts: renesas: convert isa detection to new properties
(no matching commit)
- [v3,5/6] riscv: dts: allwinner: convert isa detection to new properties
https://git.kernel.org/riscv/c/c3f7c14856eb
- [v3,6/6] riscv: dts: thead: convert isa detection to new properties
https://git.kernel.org/riscv/c/0804f3bec9e9
You are awesome, thank you!
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