From: Chen Wang <unicornxw@gmail.com>
To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org,
krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
palmer@dabbelt.com, paul.walmsley@sifive.com,
richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com,
guoren@kernel.org, jszhang@kernel.org, inochiama@outlook.com,
samuel.holland@sifive.com
Cc: Chen Wang <unicorn_wang@outlook.com>
Subject: [PATCH v7 4/4] riscv: dts: add clock generator for Sophgo SG2042 SoC
Date: Mon, 8 Jan 2024 14:49:53 +0800 [thread overview]
Message-ID: <25650372c373b15309cd9f3822306838e556d3c7.1704694903.git.unicorn_wang@outlook.com> (raw)
In-Reply-To: <cover.1704694903.git.unicorn_wang@outlook.com>
From: Chen Wang <unicorn_wang@outlook.com>
Add clock generator node to device tree for SG2042, and enable clock for
uart.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
.../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 4 ++++
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 23 +++++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
index 49b4b9c2c101..0b3b3b2b0c64 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
@@ -14,6 +14,10 @@ chosen {
};
};
+&cgi {
+ clock-frequency = <25000000>;
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index 93256540d078..c9616d111905 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -5,6 +5,7 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
#include "sg2042-cpus.dtsi"
@@ -18,6 +19,12 @@ aliases {
serial0 = &uart0;
};
+ cgi: oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "cgi";
+ #clock-cells = <0>;
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -311,12 +318,28 @@ intc: interrupt-controller@7090000000 {
riscv,ndev = <224>;
};
+ sys_ctrl: system-controller@7030010000 {
+ compatible = "sophgo,sg2042-sysctrl";
+ reg = <0x70 0x30010000 0x0 0x1000>;
+ };
+
+ clkgen: clock-controller@7030012000 {
+ compatible = "sophgo,sg2042-clkgen";
+ reg = <0x70 0x30012000 0x0 0x1000>;
+ sophgo,system-ctrl = <&sys_ctrl>;
+ #clock-cells = <1>;
+ clocks = <&cgi>;
+ };
+
uart0: serial@7040000000 {
compatible = "snps,dw-apb-uart";
reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
interrupt-parent = <&intc>;
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
+ clocks = <&clkgen GATE_CLK_UART_500M>,
+ <&clkgen GATE_CLK_APB_UART>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
--
2.25.1
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next prev parent reply other threads:[~2024-01-08 6:50 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-08 6:47 [PATCH v7 0/4] riscv: sophgo: add clock support for sg2042 Chen Wang
2024-01-08 6:48 ` [PATCH v7 1/4] dt-bindings: soc: sophgo: Add Sophgo system control module Chen Wang
2024-01-08 7:03 ` Krzysztof Kozlowski
2024-01-08 7:20 ` Chen Wang
2024-01-08 19:36 ` Krzysztof Kozlowski
2024-01-09 8:26 ` Chen Wang
2024-01-09 8:52 ` Chen Wang
2024-01-09 8:56 ` Krzysztof Kozlowski
2024-01-10 0:44 ` Chen Wang
2024-01-10 7:24 ` Krzysztof Kozlowski
2024-01-08 6:49 ` [PATCH v7 2/4] dt-bindings: clock: sophgo: support SG2042 Chen Wang
2024-01-08 7:04 ` Krzysztof Kozlowski
2024-01-10 0:53 ` Chen Wang
2024-01-10 14:42 ` Conor Dooley
2024-01-11 7:51 ` Chen Wang
2024-01-11 8:00 ` Chen Wang
2024-01-11 16:58 ` Conor Dooley
2024-01-12 0:08 ` Chen Wang
2024-01-12 7:42 ` Conor Dooley
2024-01-12 8:27 ` Chen Wang
2024-01-12 8:35 ` Chen Wang
2024-01-12 8:38 ` Krzysztof Kozlowski
2024-01-12 19:35 ` Samuel Holland
2024-01-13 1:15 ` Chen Wang
2024-01-08 6:49 ` [PATCH v7 3/4] clk: sophgo: Add SG2042 clock generator driver Chen Wang
2024-01-08 6:49 ` Chen Wang [this message]
2024-01-10 14:13 ` [PATCH v7 4/4] riscv: dts: add clock generator for Sophgo SG2042 SoC Conor Dooley
2024-01-11 7:55 ` Chen Wang
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