From: Chen Wang <unicorn_wang@outlook.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Chen Wang <unicornxw@gmail.com>,
aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org,
krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
palmer@dabbelt.com, paul.walmsley@sifive.com,
richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com,
guoren@kernel.org, jszhang@kernel.org, inochiama@outlook.com,
samuel.holland@sifive.com
Cc: Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v7 2/4] dt-bindings: clock: sophgo: support SG2042
Date: Wed, 10 Jan 2024 08:53:42 +0800 [thread overview]
Message-ID: <MA0P287MB2822C7A3C1DC7786708E860BFE692@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <f88b79c3-e44b-4136-ae56-10e1f2502e2d@linaro.org>
On 2024/1/8 15:04, Krzysztof Kozlowski wrote:
> On 08/01/2024 07:49, Chen Wang wrote:
>> From: Chen Wang <unicorn_wang@outlook.com>
>>
>> Add bindings for the clock generator on the SG2042 RISC-V SoC.
>>
>> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
>> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> .../bindings/clock/sophgo,sg2042-clkgen.yaml | 53 ++++++
>> .../dt-bindings/clock/sophgo,sg2042-clkgen.h | 169 ++++++++++++++++++
>> 2 files changed, 222 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml
>> create mode 100644 include/dt-bindings/clock/sophgo,sg2042-clkgen.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml b/Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml
>> new file mode 100644
>> index 000000000000..f9935e66fc95
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml
>> @@ -0,0 +1,53 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/sophgo,sg2042-clkgen.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Sophgo SG2042 Clock Generator
>> +
>> +maintainers:
>> + - Chen Wang <unicorn_wang@outlook.com>
>> +
>> +properties:
>> + compatible:
>> + const: sophgo,sg2042-clkgen
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + sophgo,system-ctrl:
>> + $ref: /schemas/types.yaml#/definitions/phandle
>> + description:
>> + Phandle to SG2042 System Controller node. On SG2042, part of control
>> + registers of Clock Controller are defined in System controller. Clock
>> + driver will use this phandle to get the register map base to plus the
>> + offset of the registers to access them.
> Do not describe the driver, but hardware. What registers are in
> system-ctrl? What are their purpose? Why this hardware needs them?
Understood, will fix the words in revision, thanks.
>
>
>
> Best regards,
> Krzysztof
>
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next prev parent reply other threads:[~2024-01-10 0:54 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-08 6:47 [PATCH v7 0/4] riscv: sophgo: add clock support for sg2042 Chen Wang
2024-01-08 6:48 ` [PATCH v7 1/4] dt-bindings: soc: sophgo: Add Sophgo system control module Chen Wang
2024-01-08 7:03 ` Krzysztof Kozlowski
2024-01-08 7:20 ` Chen Wang
2024-01-08 19:36 ` Krzysztof Kozlowski
2024-01-09 8:26 ` Chen Wang
2024-01-09 8:52 ` Chen Wang
2024-01-09 8:56 ` Krzysztof Kozlowski
2024-01-10 0:44 ` Chen Wang
2024-01-10 7:24 ` Krzysztof Kozlowski
2024-01-08 6:49 ` [PATCH v7 2/4] dt-bindings: clock: sophgo: support SG2042 Chen Wang
2024-01-08 7:04 ` Krzysztof Kozlowski
2024-01-10 0:53 ` Chen Wang [this message]
2024-01-10 14:42 ` Conor Dooley
2024-01-11 7:51 ` Chen Wang
2024-01-11 8:00 ` Chen Wang
2024-01-11 16:58 ` Conor Dooley
2024-01-12 0:08 ` Chen Wang
2024-01-12 7:42 ` Conor Dooley
2024-01-12 8:27 ` Chen Wang
2024-01-12 8:35 ` Chen Wang
2024-01-12 8:38 ` Krzysztof Kozlowski
2024-01-12 19:35 ` Samuel Holland
2024-01-13 1:15 ` Chen Wang
2024-01-08 6:49 ` [PATCH v7 3/4] clk: sophgo: Add SG2042 clock generator driver Chen Wang
2024-01-08 6:49 ` [PATCH v7 4/4] riscv: dts: add clock generator for Sophgo SG2042 SoC Chen Wang
2024-01-10 14:13 ` Conor Dooley
2024-01-11 7:55 ` Chen Wang
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