From: Chen Wang <unicorn_wang@outlook.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Chen Wang <unicornxw@gmail.com>,
aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org,
krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
palmer@dabbelt.com, paul.walmsley@sifive.com,
richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com,
guoren@kernel.org, jszhang@kernel.org, inochiama@outlook.com,
samuel.holland@sifive.com
Subject: Re: [PATCH v7 1/4] dt-bindings: soc: sophgo: Add Sophgo system control module
Date: Tue, 9 Jan 2024 16:26:31 +0800 [thread overview]
Message-ID: <MA0P287MB2822FD86915185F6C908ACCFFE6A2@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <1e1ef0a0-6639-4a4d-9b4e-50bcee3fb3c5@linaro.org>
On 2024/1/9 3:36, Krzysztof Kozlowski wrote:
> On 08/01/2024 08:20, Chen Wang wrote:
>> On 2024/1/8 15:03, Krzysztof Kozlowski wrote:
>>> On 08/01/2024 07:48, Chen Wang wrote:
>>>> From: Chen Wang <unicorn_wang@outlook.com>
>>>>
>>>> Add documentation to describe Sophgo System Controller for SG2042.
>>>>
>>>> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
>>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>> ---
>>>> .../soc/sophgo/sophgo,sg2042-sysctrl.yaml | 34 +++++++++++++++++++
>>>> 1 file changed, 34 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml
>>>> new file mode 100644
>>>> index 000000000000..1ec1eaa55598
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml
>>>> @@ -0,0 +1,34 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2042-sysctrl.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: Sophgo SG2042 SoC system controller
>>>> +
>>>> +maintainers:
>>>> + - Chen Wang <unicorn_wang@outlook.com>
>>>> +
>>>> +description:
>>>> + The Sophgo SG2042 SoC system controller provides register information such
>>>> + as offset, mask and shift that can be used by other modules, such as clocks.
>>> "offset, mask and shift" is not a register information stored in
>>> syscons. Are you really sure, that your system controller hardware
>>> stores offsets of some other registers?
>>>
>>> Show as some example of such offsets, masks and shifts provided by this
>>> hardware.
>> The system control module is defined here:
>> https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/system-control.rst.
>> It contains some registers related to pll and gates.
> I do not see there registers providing shifts and offsets... just values.
Let me first clarify more what the "offset"/"shift"/"mask" I meant,
Use
https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/system-control.rst#mpll_control-offset-0x0e8
as example, this register is used to control Main PLL:
- Offset: 0x0E8, to my understand, it is the offest between this
MPLL_CONTROL register and the start of system-control base
- Shift: the conlumn "LSB", for example, to locate the field
MPLL_CONTROL.MPLL_FBDIV, we can first use system-control base + offset
to get the address of MPLL_CONTROL, then use LSB(16) as shift to get the
start position of this field.
- Mask: still use MPLL_CONTROL.MPLL_FBDIV as example, use MSB(27) and
LSB(16), this means the width of this field is 12 and with this we can
get bit-mask for this field.
For SG2042, IC define clock related registers in two parts, one is in
https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/clock.rst,
and another in
https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/system-control.rst.
I define the system control node in DTS and just treat it as a block of
registers array and after regmap I can get some registers address such
as MPLL_CONTROL to access it from my driver code.
>> Some other clocks registars are defined in
>> https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/clock.rst.
>>
>> memory-map is defined in
>> https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/mmap.rst
>
> Please fix the wording because it does not make sense. System controller
> does not provide register information. Your datasheet provides register
> information.
Sorry, I don't understand why you say "System controller does not
provide register information."? As I explained above, I did see the
information about these clock-related registers from the system control
module, such as the offset/shift/mask I mentioned above. That's why I
wrote "that can be used by other modules, such as clocks". How should I
express, please enlighten me.
Thanks,
Chen
> Best regards,
> Krzysztof
>
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next prev parent reply other threads:[~2024-01-09 8:27 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-08 6:47 [PATCH v7 0/4] riscv: sophgo: add clock support for sg2042 Chen Wang
2024-01-08 6:48 ` [PATCH v7 1/4] dt-bindings: soc: sophgo: Add Sophgo system control module Chen Wang
2024-01-08 7:03 ` Krzysztof Kozlowski
2024-01-08 7:20 ` Chen Wang
2024-01-08 19:36 ` Krzysztof Kozlowski
2024-01-09 8:26 ` Chen Wang [this message]
2024-01-09 8:52 ` Chen Wang
2024-01-09 8:56 ` Krzysztof Kozlowski
2024-01-10 0:44 ` Chen Wang
2024-01-10 7:24 ` Krzysztof Kozlowski
2024-01-08 6:49 ` [PATCH v7 2/4] dt-bindings: clock: sophgo: support SG2042 Chen Wang
2024-01-08 7:04 ` Krzysztof Kozlowski
2024-01-10 0:53 ` Chen Wang
2024-01-10 14:42 ` Conor Dooley
2024-01-11 7:51 ` Chen Wang
2024-01-11 8:00 ` Chen Wang
2024-01-11 16:58 ` Conor Dooley
2024-01-12 0:08 ` Chen Wang
2024-01-12 7:42 ` Conor Dooley
2024-01-12 8:27 ` Chen Wang
2024-01-12 8:35 ` Chen Wang
2024-01-12 8:38 ` Krzysztof Kozlowski
2024-01-12 19:35 ` Samuel Holland
2024-01-13 1:15 ` Chen Wang
2024-01-08 6:49 ` [PATCH v7 3/4] clk: sophgo: Add SG2042 clock generator driver Chen Wang
2024-01-08 6:49 ` [PATCH v7 4/4] riscv: dts: add clock generator for Sophgo SG2042 SoC Chen Wang
2024-01-10 14:13 ` Conor Dooley
2024-01-11 7:55 ` Chen Wang
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