From: Inochi Amaoto <inochiama@outlook.com>
To: Chao Wei <chao.wei@sophgo.com>,
Chen Wang <unicorn_wang@outlook.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: Jisheng Zhang <jszhang@kernel.org>,
Inochi Amaoto <inochiama@outlook.com>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v2 6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree
Date: Mon, 9 Oct 2023 19:26:37 +0800 [thread overview]
Message-ID: <IA1PR20MB4953262ABB6EFFBC4B4F932BBBCEA@IA1PR20MB4953.namprd20.prod.outlook.com> (raw)
In-Reply-To: <20231009112642.477337-1-inochiama@outlook.com>
Add initial device tree for the CV1812H RISC-V SoC by SOPHGO.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
---
arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi
diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
new file mode 100644
index 000000000000..3864d34b0100
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "cv180x.dtsi"
+
+/ {
+ compatible = "sophgo,cv1812h";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+
+ soc {
+ interrupt-parent = <&plic>;
+
+ plic: interrupt-controller@70000000 {
+ compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
+ reg = <0x70000000 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ riscv,ndev = <101>;
+ };
+
+ clint: timer@74000000 {
+ compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
+ reg = <0x74000000 0x10000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+ };
+ };
+};
--
2.42.0
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next prev parent reply other threads:[~2023-10-09 11:27 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-09 11:25 [PATCH v2 0/7] Add Huashan Pi board support Inochi Amaoto
2023-10-09 11:26 ` [PATCH v2 1/7] dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic Inochi Amaoto
2023-10-09 11:30 ` Krzysztof Kozlowski
[not found] ` <20231009112642.477337-1-inochiama@outlook.com>
2023-10-09 11:26 ` [PATCH v2 2/7] dt-bindings: timer: Add SOPHGO CV1812H clint Inochi Amaoto
2023-10-09 11:30 ` Krzysztof Kozlowski
2023-10-09 11:26 ` [PATCH v2 3/7] dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles Inochi Amaoto
2023-10-09 11:30 ` Krzysztof Kozlowski
2023-10-09 11:26 ` [PATCH v2 4/7] riscv: dts: sophgo: Separate common devices from cv1800b soc Inochi Amaoto
2023-10-12 10:46 ` Chen Wang
2023-10-12 12:50 ` Chen Wang
2023-10-13 9:08 ` Conor Dooley
2023-10-13 9:50 ` [PATCH v2 6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree Inochi Amaoto
2023-10-13 9:52 ` [PATCH v2 6/7] riscv: dts: sophgo: Separate common devices from cv1800b soc Inochi Amaoto
2023-10-13 13:27 ` Conor Dooley
2023-10-13 22:36 ` [PATCH v2 4/7] " Inochi Amaoto
2023-10-14 9:04 ` Jisheng Zhang
2023-10-14 9:28 ` Conor Dooley
2023-10-09 11:26 ` [PATCH v2 5/7] riscv: dts: sophgo: cv180x: Add gpio devices Inochi Amaoto
2023-10-12 12:52 ` Chen Wang
2023-10-09 11:26 ` Inochi Amaoto [this message]
2023-10-10 7:21 ` [PATCH v2 6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree Chen Wang
2023-10-10 7:53 ` Inochi Amaoto
2023-10-12 9:41 ` Conor Dooley
2023-10-12 13:02 ` Chen Wang
2023-10-09 11:26 ` [PATCH v2 7/7] riscv: dts: sophgo: add Huashan Pi board " Inochi Amaoto
2023-10-12 12:53 ` Chen Wang
2023-10-12 13:20 ` [PATCH v2 0/7] Add Huashan Pi board support Jisheng Zhang
2023-10-13 8:48 ` Krzysztof Kozlowski
2023-10-13 8:55 ` Inochi Amaoto
2023-10-13 9:00 ` Inochi Amaoto
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