From: Chen Wang <unicorn_wang@outlook.com>
To: Inochi Amaoto <inochiama@outlook.com>,
Chao Wei <chao.wei@sophgo.com>, Conor Dooley <conor@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: Jisheng Zhang <jszhang@kernel.org>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 4/7] riscv: dts: sophgo: Separate common devices from cv1800b soc
Date: Thu, 12 Oct 2023 20:50:18 +0800 [thread overview]
Message-ID: <MA0P287MB0332C3CA4A3604BA7F7C340CFED3A@MA0P287MB0332.INDP287.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <IA1PR20MB49532560A3CA2670A0EAB846BBCEA@IA1PR20MB4953.namprd20.prod.outlook.com>
On 2023/10/9 19:26, Inochi Amaoto wrote:
> Move the cpu and the common peripherals of CV181x and CV180x to new file.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> ---
> arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 95 +------------------
> .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} | 19 +---
> 2 files changed, 2 insertions(+), 112 deletions(-)
> copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (80%)
LGTM
Acked-by: Chen Wang <unicorn_wang@outlook.com>
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index df40e87ee063..0904154f9829 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -3,106 +3,13 @@
> * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> */
>
> -#include <dt-bindings/interrupt-controller/irq.h>
> +#include "cv180x.dtsi"
>
> / {
> compatible = "sophgo,cv1800b";
> - #address-cells = <1>;
> - #size-cells = <1>;
> -
> - cpus: cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - timebase-frequency = <25000000>;
> -
> - cpu0: cpu@0 {
> - compatible = "thead,c906", "riscv";
> - device_type = "cpu";
> - reg = <0>;
> - d-cache-block-size = <64>;
> - d-cache-sets = <512>;
> - d-cache-size = <65536>;
> - i-cache-block-size = <64>;
> - i-cache-sets = <128>;
> - i-cache-size = <32768>;
> - mmu-type = "riscv,sv39";
> - riscv,isa = "rv64imafdc";
> - riscv,isa-base = "rv64i";
> - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> - "zifencei", "zihpm";
> -
> - cpu0_intc: interrupt-controller {
> - compatible = "riscv,cpu-intc";
> - interrupt-controller;
> - #address-cells = <0>;
> - #interrupt-cells = <1>;
> - };
> - };
> - };
> -
> - osc: oscillator {
> - compatible = "fixed-clock";
> - clock-output-names = "osc_25m";
> - #clock-cells = <0>;
> - };
>
> soc {
> - compatible = "simple-bus";
> interrupt-parent = <&plic>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> - dma-noncoherent;
> - ranges;
> -
> - uart0: serial@4140000 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x04140000 0x100>;
> - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&osc>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - status = "disabled";
> - };
> -
> - uart1: serial@4150000 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x04150000 0x100>;
> - interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&osc>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - status = "disabled";
> - };
> -
> - uart2: serial@4160000 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x04160000 0x100>;
> - interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&osc>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - status = "disabled";
> - };
> -
> - uart3: serial@4170000 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x04170000 0x100>;
> - interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&osc>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - status = "disabled";
> - };
> -
> - uart4: serial@41c0000 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x041c0000 0x100>;
> - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&osc>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - status = "disabled";
> - };
>
> plic: interrupt-controller@70000000 {
> compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> similarity index 80%
> copy from arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> copy to arch/riscv/boot/dts/sophgo/cv180x.dtsi
> index df40e87ee063..ffaf51724c98 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> @@ -1,12 +1,12 @@
> // SPDX-License-Identifier: (GPL-2.0 OR MIT)
> /*
> * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
> */
>
> #include <dt-bindings/interrupt-controller/irq.h>
>
> / {
> - compatible = "sophgo,cv1800b";
> #address-cells = <1>;
> #size-cells = <1>;
>
> @@ -48,7 +48,6 @@ osc: oscillator {
>
> soc {
> compatible = "simple-bus";
> - interrupt-parent = <&plic>;
> #address-cells = <1>;
> #size-cells = <1>;
> dma-noncoherent;
> @@ -103,21 +102,5 @@ uart4: serial@41c0000 {
> reg-io-width = <4>;
> status = "disabled";
> };
> -
> - plic: interrupt-controller@70000000 {
> - compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> - reg = <0x70000000 0x4000000>;
> - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> - interrupt-controller;
> - #address-cells = <0>;
> - #interrupt-cells = <2>;
> - riscv,ndev = <101>;
> - };
> -
> - clint: timer@74000000 {
> - compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
> - reg = <0x74000000 0x10000>;
> - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> - };
> };
> };
> --
> 2.42.0
>
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next prev parent reply other threads:[~2023-10-12 12:50 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-09 11:25 [PATCH v2 0/7] Add Huashan Pi board support Inochi Amaoto
2023-10-09 11:26 ` [PATCH v2 1/7] dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic Inochi Amaoto
2023-10-09 11:30 ` Krzysztof Kozlowski
[not found] ` <20231009112642.477337-1-inochiama@outlook.com>
2023-10-09 11:26 ` [PATCH v2 2/7] dt-bindings: timer: Add SOPHGO CV1812H clint Inochi Amaoto
2023-10-09 11:30 ` Krzysztof Kozlowski
2023-10-09 11:26 ` [PATCH v2 3/7] dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles Inochi Amaoto
2023-10-09 11:30 ` Krzysztof Kozlowski
2023-10-09 11:26 ` [PATCH v2 4/7] riscv: dts: sophgo: Separate common devices from cv1800b soc Inochi Amaoto
2023-10-12 10:46 ` Chen Wang
2023-10-12 12:50 ` Chen Wang [this message]
2023-10-13 9:08 ` Conor Dooley
2023-10-13 9:50 ` [PATCH v2 6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree Inochi Amaoto
2023-10-13 9:52 ` [PATCH v2 6/7] riscv: dts: sophgo: Separate common devices from cv1800b soc Inochi Amaoto
2023-10-13 13:27 ` Conor Dooley
2023-10-13 22:36 ` [PATCH v2 4/7] " Inochi Amaoto
2023-10-14 9:04 ` Jisheng Zhang
2023-10-14 9:28 ` Conor Dooley
2023-10-09 11:26 ` [PATCH v2 5/7] riscv: dts: sophgo: cv180x: Add gpio devices Inochi Amaoto
2023-10-12 12:52 ` Chen Wang
2023-10-09 11:26 ` [PATCH v2 6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree Inochi Amaoto
2023-10-10 7:21 ` Chen Wang
2023-10-10 7:53 ` Inochi Amaoto
2023-10-12 9:41 ` Conor Dooley
2023-10-12 13:02 ` Chen Wang
2023-10-09 11:26 ` [PATCH v2 7/7] riscv: dts: sophgo: add Huashan Pi board " Inochi Amaoto
2023-10-12 12:53 ` Chen Wang
2023-10-12 13:20 ` [PATCH v2 0/7] Add Huashan Pi board support Jisheng Zhang
2023-10-13 8:48 ` Krzysztof Kozlowski
2023-10-13 8:55 ` Inochi Amaoto
2023-10-13 9:00 ` Inochi Amaoto
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