* [PATCH v5 01/15] dt-bindings: clock: split qcom,gcc.yaml to common and specific schema
2022-02-24 16:48 [PATCH v5 00/15] Multiple addition and improvement to ipq8064 gcc Ansuel Smith
@ 2022-02-24 16:48 ` Ansuel Smith
2022-02-24 18:43 ` Rob Herring
` (2 more replies)
2022-02-24 16:48 ` [PATCH v5 02/15] dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation Ansuel Smith
` (13 subsequent siblings)
14 siblings, 3 replies; 38+ messages in thread
From: Ansuel Smith @ 2022-02-24 16:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Philipp Zabel, Taniya Das, Ansuel Smith,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Split qcom,gcc.yaml to common and specific schema to use it as a
template for schema that needs to use the gcc bindings and require
to add additional bindings.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
.../bindings/clock/qcom,gcc-other.yaml | 76 +++++++++++++++++++
.../devicetree/bindings/clock/qcom,gcc.yaml | 59 +-------------
2 files changed, 80 insertions(+), 55 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
new file mode 100644
index 000000000000..4e5903bcd70d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding
+
+maintainers:
+ - Stephen Boyd <sboyd@kernel.org>
+ - Taniya Das <tdas@codeaurora.org>
+
+description:
+ Qualcomm global clock control module which supports the clocks, resets and
+ power domains.
+
+ See also:
+ - dt-bindings/clock/qcom,gcc-apq8084.h
+ - dt-bindings/reset/qcom,gcc-apq8084.h
+ - dt-bindings/clock/qcom,gcc-ipq4019.h
+ - dt-bindings/clock/qcom,gcc-ipq6018.h
+ - dt-bindings/reset/qcom,gcc-ipq6018.h
+ - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
+ - dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
+ - dt-bindings/clock/qcom,gcc-msm8939.h
+ - dt-bindings/clock/qcom,gcc-msm8953.h
+ - dt-bindings/reset/qcom,gcc-msm8939.h
+ - dt-bindings/clock/qcom,gcc-msm8660.h
+ - dt-bindings/reset/qcom,gcc-msm8660.h
+ - dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
+ - dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
+ - dt-bindings/clock/qcom,gcc-mdm9607.h
+ - dt-bindings/clock/qcom,gcc-mdm9615.h
+ - dt-bindings/reset/qcom,gcc-mdm9615.h
+ - dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
+
+allOf:
+ - $ref: "qcom,gcc.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - qcom,gcc-apq8084
+ - qcom,gcc-ipq4019
+ - qcom,gcc-ipq6018
+ - qcom,gcc-ipq8064
+ - qcom,gcc-mdm9607
+ - qcom,gcc-msm8226
+ - qcom,gcc-msm8660
+ - qcom,gcc-msm8916
+ - qcom,gcc-msm8939
+ - qcom,gcc-msm8953
+ - qcom,gcc-msm8960
+ - qcom,gcc-msm8974
+ - qcom,gcc-msm8974pro
+ - qcom,gcc-msm8974pro-ac
+ - qcom,gcc-mdm9615
+ - qcom,gcc-sdm630
+ - qcom,gcc-sdm660
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ # Example for GCC for MSM8960:
+ - |
+ clock-controller@900000 {
+ compatible = "qcom,gcc-msm8960";
+ reg = <0x900000 0x4000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
index f66d703bd913..2ed27a2ef445 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
@@ -4,57 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Global Clock & Reset Controller Binding
+title: Qualcomm Global Clock & Reset Controller Binding Common Bindings
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
- Qualcomm global clock control module which supports the clocks, resets and
- power domains.
-
- See also:
- - dt-bindings/clock/qcom,gcc-apq8084.h
- - dt-bindings/reset/qcom,gcc-apq8084.h
- - dt-bindings/clock/qcom,gcc-ipq4019.h
- - dt-bindings/clock/qcom,gcc-ipq6018.h
- - dt-bindings/reset/qcom,gcc-ipq6018.h
- - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
- - dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
- - dt-bindings/clock/qcom,gcc-msm8939.h
- - dt-bindings/clock/qcom,gcc-msm8953.h
- - dt-bindings/reset/qcom,gcc-msm8939.h
- - dt-bindings/clock/qcom,gcc-msm8660.h
- - dt-bindings/reset/qcom,gcc-msm8660.h
- - dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
- - dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
- - dt-bindings/clock/qcom,gcc-mdm9607.h
- - dt-bindings/clock/qcom,gcc-mdm9615.h
- - dt-bindings/reset/qcom,gcc-mdm9615.h
- - dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
+ Common bindings for Qualcomm global clock control module which supports
+ the clocks, resets and power domains.
properties:
- compatible:
- enum:
- - qcom,gcc-apq8084
- - qcom,gcc-ipq4019
- - qcom,gcc-ipq6018
- - qcom,gcc-ipq8064
- - qcom,gcc-mdm9607
- - qcom,gcc-msm8226
- - qcom,gcc-msm8660
- - qcom,gcc-msm8916
- - qcom,gcc-msm8939
- - qcom,gcc-msm8953
- - qcom,gcc-msm8960
- - qcom,gcc-msm8974
- - qcom,gcc-msm8974pro
- - qcom,gcc-msm8974pro-ac
- - qcom,gcc-mdm9615
- - qcom,gcc-sdm630
- - qcom,gcc-sdm660
-
'#clock-cells':
const: 1
@@ -72,22 +32,11 @@ properties:
Protected clock specifier list as per common clock binding.
required:
- - compatible
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
-additionalProperties: false
+additionalProperties: true
-examples:
- # Example for GCC for MSM8960:
- - |
- clock-controller@900000 {
- compatible = "qcom,gcc-msm8960";
- reg = <0x900000 0x4000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
...
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v5 01/15] dt-bindings: clock: split qcom,gcc.yaml to common and specific schema
2022-02-24 16:48 ` [PATCH v5 01/15] dt-bindings: clock: split qcom,gcc.yaml to common and specific schema Ansuel Smith
@ 2022-02-24 18:43 ` Rob Herring
2022-02-24 22:04 ` Stephen Boyd
2022-03-23 13:55 ` Rob Herring
2 siblings, 0 replies; 38+ messages in thread
From: Rob Herring @ 2022-02-24 18:43 UTC (permalink / raw)
To: Ansuel Smith
Cc: linux-kernel, devicetree, Bjorn Andersson, Rob Herring,
Michael Turquette, Philipp Zabel, Taniya Das, linux-clk,
linux-arm-msm, Stephen Boyd, Andy Gross
On Thu, 24 Feb 2022 17:48:17 +0100, Ansuel Smith wrote:
> Split qcom,gcc.yaml to common and specific schema to use it as a
> template for schema that needs to use the gcc bindings and require
> to add additional bindings.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
> .../bindings/clock/qcom,gcc-other.yaml | 76 +++++++++++++++++++
> .../devicetree/bindings/clock/qcom,gcc.yaml | 59 +-------------
> 2 files changed, 80 insertions(+), 55 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 01/15] dt-bindings: clock: split qcom,gcc.yaml to common and specific schema
2022-02-24 16:48 ` [PATCH v5 01/15] dt-bindings: clock: split qcom,gcc.yaml to common and specific schema Ansuel Smith
2022-02-24 18:43 ` Rob Herring
@ 2022-02-24 22:04 ` Stephen Boyd
2022-03-23 13:55 ` Rob Herring
2 siblings, 0 replies; 38+ messages in thread
From: Stephen Boyd @ 2022-02-24 22:04 UTC (permalink / raw)
To: Andy Gross, Ansuel Smith, Bjorn Andersson, Michael Turquette,
Philipp Zabel, Rob Herring, Taniya Das, devicetree,
linux-arm-msm, linux-clk, linux-kernel
Quoting Ansuel Smith (2022-02-24 08:48:17)
> Split qcom,gcc.yaml to common and specific schema to use it as a
> template for schema that needs to use the gcc bindings and require
> to add additional bindings.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 01/15] dt-bindings: clock: split qcom,gcc.yaml to common and specific schema
2022-02-24 16:48 ` [PATCH v5 01/15] dt-bindings: clock: split qcom,gcc.yaml to common and specific schema Ansuel Smith
2022-02-24 18:43 ` Rob Herring
2022-02-24 22:04 ` Stephen Boyd
@ 2022-03-23 13:55 ` Rob Herring
2022-03-23 19:47 ` Ansuel Smith
2 siblings, 1 reply; 38+ messages in thread
From: Rob Herring @ 2022-03-23 13:55 UTC (permalink / raw)
To: Ansuel Smith
Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Philipp Zabel, Taniya Das, linux-arm-msm, linux-clk, devicetree,
linux-kernel
On Thu, Feb 24, 2022 at 10:48 AM Ansuel Smith <ansuelsmth@gmail.com> wrote:
>
> Split qcom,gcc.yaml to common and specific schema to use it as a
> template for schema that needs to use the gcc bindings and require
> to add additional bindings.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
> .../bindings/clock/qcom,gcc-other.yaml | 76 +++++++++++++++++++
This now throws errors in linux-next:
Traceback (most recent call last):
File "/usr/local/lib/python3.8/dist-packages/jsonschema/validators.py",
line 816, in resolve_from_url
document = self.resolve_remote(url)
File "/usr/local/lib/python3.8/dist-packages/jsonschema/validators.py",
line 923, in resolve_remote
result = json.loads(url.read().decode("utf-8"))
File "/usr/lib/python3.8/json/__init__.py", line 357, in loads
return _default_decoder.decode(s)
File "/usr/lib/python3.8/json/decoder.py", line 337, in decode
obj, end = self.raw_decode(s, idx=_w(s, 0).end())
File "/usr/lib/python3.8/json/decoder.py", line 355, in raw_decode
raise JSONDecodeError("Expecting value", s, err.value) from None
json.decoder.JSONDecodeError: Expecting value: line 1 column 1 (char 0)
During handling of the above exception, another exception occurred:
Traceback (most recent call last):
File "/usr/local/bin/dt-doc-validate", line 70, in <module>
ret = check_doc(f)
File "/usr/local/bin/dt-doc-validate", line 36, in check_doc
for error in
sorted(dtschema.DTValidator.iter_schema_errors(testtree), key=lambda
e: e.linecol):
File "/usr/local/lib/python3.8/dist-packages/dtschema/lib.py", line
1016, in iter_schema_errors
meta_schema = cls.resolver.resolve_from_url(schema['$schema'])
File "/usr/local/lib/python3.8/dist-packages/jsonschema/validators.py",
line 818, in resolve_from_url
raise exceptions.RefResolutionError(exc)
jsonschema.exceptions.RefResolutionError: Expecting value: line 1
column 1 (char 0)
./Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml:
mapping values are not allowed in this context
in "<unicode string>", line 17, column 11
> .../devicetree/bindings/clock/qcom,gcc.yaml | 59 +-------------
> 2 files changed, 80 insertions(+), 55 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> new file mode 100644
> index 000000000000..4e5903bcd70d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> @@ -0,0 +1,76 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Global Clock & Reset Controller Binding
> +
> +maintainers:
> + - Stephen Boyd <sboyd@kernel.org>
> + - Taniya Das <tdas@codeaurora.org>
> +
> +description:
> + Qualcomm global clock control module which supports the clocks, resets and
> + power domains.
> +
> + See also:
I think the problem is here. You need a '|' after 'description' to
preserve formatting and ignore what looks like a mapping.
> + - dt-bindings/clock/qcom,gcc-apq8084.h
> + - dt-bindings/reset/qcom,gcc-apq8084.h
> + - dt-bindings/clock/qcom,gcc-ipq4019.h
> + - dt-bindings/clock/qcom,gcc-ipq6018.h
> + - dt-bindings/reset/qcom,gcc-ipq6018.h
> + - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
> + - dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
> + - dt-bindings/clock/qcom,gcc-msm8939.h
> + - dt-bindings/clock/qcom,gcc-msm8953.h
> + - dt-bindings/reset/qcom,gcc-msm8939.h
> + - dt-bindings/clock/qcom,gcc-msm8660.h
> + - dt-bindings/reset/qcom,gcc-msm8660.h
> + - dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
> + - dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
> + - dt-bindings/clock/qcom,gcc-mdm9607.h
> + - dt-bindings/clock/qcom,gcc-mdm9615.h
> + - dt-bindings/reset/qcom,gcc-mdm9615.h
> + - dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 01/15] dt-bindings: clock: split qcom,gcc.yaml to common and specific schema
2022-03-23 13:55 ` Rob Herring
@ 2022-03-23 19:47 ` Ansuel Smith
2022-03-24 13:16 ` Rob Herring
0 siblings, 1 reply; 38+ messages in thread
From: Ansuel Smith @ 2022-03-23 19:47 UTC (permalink / raw)
To: Rob Herring
Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Philipp Zabel, Taniya Das, linux-arm-msm, linux-clk, devicetree,
linux-kernel
On Wed, Mar 23, 2022 at 08:55:30AM -0500, Rob Herring wrote:
> On Thu, Feb 24, 2022 at 10:48 AM Ansuel Smith <ansuelsmth@gmail.com> wrote:
> >
> > Split qcom,gcc.yaml to common and specific schema to use it as a
> > template for schema that needs to use the gcc bindings and require
> > to add additional bindings.
> >
> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > ---
> > .../bindings/clock/qcom,gcc-other.yaml | 76 +++++++++++++++++++
>
> This now throws errors in linux-next:
>
> Traceback (most recent call last):
> File "/usr/local/lib/python3.8/dist-packages/jsonschema/validators.py",
> line 816, in resolve_from_url
> document = self.resolve_remote(url)
> File "/usr/local/lib/python3.8/dist-packages/jsonschema/validators.py",
> line 923, in resolve_remote
> result = json.loads(url.read().decode("utf-8"))
> File "/usr/lib/python3.8/json/__init__.py", line 357, in loads
> return _default_decoder.decode(s)
> File "/usr/lib/python3.8/json/decoder.py", line 337, in decode
> obj, end = self.raw_decode(s, idx=_w(s, 0).end())
> File "/usr/lib/python3.8/json/decoder.py", line 355, in raw_decode
> raise JSONDecodeError("Expecting value", s, err.value) from None
> json.decoder.JSONDecodeError: Expecting value: line 1 column 1 (char 0)
> During handling of the above exception, another exception occurred:
> Traceback (most recent call last):
> File "/usr/local/bin/dt-doc-validate", line 70, in <module>
> ret = check_doc(f)
> File "/usr/local/bin/dt-doc-validate", line 36, in check_doc
> for error in
> sorted(dtschema.DTValidator.iter_schema_errors(testtree), key=lambda
> e: e.linecol):
> File "/usr/local/lib/python3.8/dist-packages/dtschema/lib.py", line
> 1016, in iter_schema_errors
> meta_schema = cls.resolver.resolve_from_url(schema['$schema'])
> File "/usr/local/lib/python3.8/dist-packages/jsonschema/validators.py",
> line 818, in resolve_from_url
> raise exceptions.RefResolutionError(exc)
> jsonschema.exceptions.RefResolutionError: Expecting value: line 1
> column 1 (char 0)
> ./Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml:
> mapping values are not allowed in this context
> in "<unicode string>", line 17, column 11
>
> > .../devicetree/bindings/clock/qcom,gcc.yaml | 59 +-------------
> > 2 files changed, 80 insertions(+), 55 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> > new file mode 100644
> > index 000000000000..4e5903bcd70d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> > @@ -0,0 +1,76 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm Global Clock & Reset Controller Binding
> > +
> > +maintainers:
> > + - Stephen Boyd <sboyd@kernel.org>
> > + - Taniya Das <tdas@codeaurora.org>
> > +
> > +description:
> > + Qualcomm global clock control module which supports the clocks, resets and
> > + power domains.
> > +
> > + See also:
>
> I think the problem is here. You need a '|' after 'description' to
> preserve formatting and ignore what looks like a mapping.
>
Yes, I just sent a patch to fix this.
Out of curiosity, any idea why this wasn't flagged by an old run of
dt_binding_check? I totally remember running dt_binding_check on these
Documentation and I had no problem. There was a bug in the old version
and it does now correctly find these kind of errors?
> > + - dt-bindings/clock/qcom,gcc-apq8084.h
> > + - dt-bindings/reset/qcom,gcc-apq8084.h
> > + - dt-bindings/clock/qcom,gcc-ipq4019.h
> > + - dt-bindings/clock/qcom,gcc-ipq6018.h
> > + - dt-bindings/reset/qcom,gcc-ipq6018.h
> > + - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
> > + - dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
> > + - dt-bindings/clock/qcom,gcc-msm8939.h
> > + - dt-bindings/clock/qcom,gcc-msm8953.h
> > + - dt-bindings/reset/qcom,gcc-msm8939.h
> > + - dt-bindings/clock/qcom,gcc-msm8660.h
> > + - dt-bindings/reset/qcom,gcc-msm8660.h
> > + - dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
> > + - dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
> > + - dt-bindings/clock/qcom,gcc-mdm9607.h
> > + - dt-bindings/clock/qcom,gcc-mdm9615.h
> > + - dt-bindings/reset/qcom,gcc-mdm9615.h
> > + - dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
--
Ansuel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 01/15] dt-bindings: clock: split qcom,gcc.yaml to common and specific schema
2022-03-23 19:47 ` Ansuel Smith
@ 2022-03-24 13:16 ` Rob Herring
0 siblings, 0 replies; 38+ messages in thread
From: Rob Herring @ 2022-03-24 13:16 UTC (permalink / raw)
To: Ansuel Smith
Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Philipp Zabel, Taniya Das, linux-arm-msm, linux-clk, devicetree,
linux-kernel
On Wed, Mar 23, 2022 at 08:47:15PM +0100, Ansuel Smith wrote:
> On Wed, Mar 23, 2022 at 08:55:30AM -0500, Rob Herring wrote:
> > On Thu, Feb 24, 2022 at 10:48 AM Ansuel Smith <ansuelsmth@gmail.com> wrote:
> > >
> > > Split qcom,gcc.yaml to common and specific schema to use it as a
> > > template for schema that needs to use the gcc bindings and require
> > > to add additional bindings.
> > >
> > > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > > ---
> > > .../bindings/clock/qcom,gcc-other.yaml | 76 +++++++++++++++++++
> >
> > This now throws errors in linux-next:
> >
> > Traceback (most recent call last):
> > File "/usr/local/lib/python3.8/dist-packages/jsonschema/validators.py",
> > line 816, in resolve_from_url
> > document = self.resolve_remote(url)
> > File "/usr/local/lib/python3.8/dist-packages/jsonschema/validators.py",
> > line 923, in resolve_remote
> > result = json.loads(url.read().decode("utf-8"))
> > File "/usr/lib/python3.8/json/__init__.py", line 357, in loads
> > return _default_decoder.decode(s)
> > File "/usr/lib/python3.8/json/decoder.py", line 337, in decode
> > obj, end = self.raw_decode(s, idx=_w(s, 0).end())
> > File "/usr/lib/python3.8/json/decoder.py", line 355, in raw_decode
> > raise JSONDecodeError("Expecting value", s, err.value) from None
> > json.decoder.JSONDecodeError: Expecting value: line 1 column 1 (char 0)
> > During handling of the above exception, another exception occurred:
> > Traceback (most recent call last):
> > File "/usr/local/bin/dt-doc-validate", line 70, in <module>
> > ret = check_doc(f)
> > File "/usr/local/bin/dt-doc-validate", line 36, in check_doc
> > for error in
> > sorted(dtschema.DTValidator.iter_schema_errors(testtree), key=lambda
> > e: e.linecol):
> > File "/usr/local/lib/python3.8/dist-packages/dtschema/lib.py", line
> > 1016, in iter_schema_errors
> > meta_schema = cls.resolver.resolve_from_url(schema['$schema'])
> > File "/usr/local/lib/python3.8/dist-packages/jsonschema/validators.py",
> > line 818, in resolve_from_url
> > raise exceptions.RefResolutionError(exc)
> > jsonschema.exceptions.RefResolutionError: Expecting value: line 1
> > column 1 (char 0)
> > ./Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml:
> > mapping values are not allowed in this context
> > in "<unicode string>", line 17, column 11
> >
> > > .../devicetree/bindings/clock/qcom,gcc.yaml | 59 +-------------
> > > 2 files changed, 80 insertions(+), 55 deletions(-)
> > > create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> > > new file mode 100644
> > > index 000000000000..4e5903bcd70d
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> > > @@ -0,0 +1,76 @@
> > > +# SPDX-License-Identifier: GPL-2.0-only
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Qualcomm Global Clock & Reset Controller Binding
> > > +
> > > +maintainers:
> > > + - Stephen Boyd <sboyd@kernel.org>
> > > + - Taniya Das <tdas@codeaurora.org>
> > > +
> > > +description:
> > > + Qualcomm global clock control module which supports the clocks, resets and
> > > + power domains.
> > > +
> > > + See also:
> >
> > I think the problem is here. You need a '|' after 'description' to
> > preserve formatting and ignore what looks like a mapping.
> >
>
> Yes, I just sent a patch to fix this.
> Out of curiosity, any idea why this wasn't flagged by an old run of
> dt_binding_check? I totally remember running dt_binding_check on these
> Documentation and I had no problem. There was a bug in the old version
> and it does now correctly find these kind of errors?
Not sure exactly, but I don't think there was any change. v3 didn't
have the issue and the bot checks didn't run on v4 or later. Probably
because it couldn't apply them.
Rob
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v5 02/15] dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation
2022-02-24 16:48 [PATCH v5 00/15] Multiple addition and improvement to ipq8064 gcc Ansuel Smith
2022-02-24 16:48 ` [PATCH v5 01/15] dt-bindings: clock: split qcom,gcc.yaml to common and specific schema Ansuel Smith
@ 2022-02-24 16:48 ` Ansuel Smith
2022-02-24 18:46 ` Rob Herring
2022-02-24 16:48 ` [PATCH v5 03/15] dt-bindings: clock: document qcom,gcc-ipq8064 binding Ansuel Smith
` (12 subsequent siblings)
14 siblings, 1 reply; 38+ messages in thread
From: Ansuel Smith @ 2022-02-24 16:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Philipp Zabel, Taniya Das, Ansuel Smith,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Simplify qcon,gcc-apq8064 Documentation by using qcom,gcc.yaml as a
template and remove the compatible from qcom,gcc.yaml
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
.../bindings/clock/qcom,gcc-apq8064.yaml | 29 +++++--------------
.../bindings/clock/qcom,gcc-other.yaml | 3 --
2 files changed, 7 insertions(+), 25 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
index 8e2eac6cbfb9..97936411b6b4 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
@@ -6,6 +6,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for APQ8064
+allOf:
+ - $ref: qcom,gcc.yaml#
+
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
@@ -17,22 +20,12 @@ description: |
See also:
- dt-bindings/clock/qcom,gcc-msm8960.h
- dt-bindings/reset/qcom,gcc-msm8960.h
+ - dt-bindings/clock/qcom,gcc-apq8084.h
+ - dt-bindings/reset/qcom,gcc-apq8084.h
properties:
compatible:
- const: qcom,gcc-apq8064
-
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
+ const: qcom,gcc-apq8084
nvmem-cells:
minItems: 1
@@ -53,21 +46,13 @@ properties:
'#thermal-sensor-cells':
const: 1
- protected-clocks:
- description:
- Protected clock specifier list as per common clock binding.
-
required:
- compatible
- - reg
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
- nvmem-cells
- nvmem-cell-names
- '#thermal-sensor-cells'
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
index 4e5903bcd70d..47e1c5332d76 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
@@ -15,8 +15,6 @@ description:
power domains.
See also:
- - dt-bindings/clock/qcom,gcc-apq8084.h
- - dt-bindings/reset/qcom,gcc-apq8084.h
- dt-bindings/clock/qcom,gcc-ipq4019.h
- dt-bindings/clock/qcom,gcc-ipq6018.h
- dt-bindings/reset/qcom,gcc-ipq6018.h
@@ -40,7 +38,6 @@ allOf:
properties:
compatible:
enum:
- - qcom,gcc-apq8084
- qcom,gcc-ipq4019
- qcom,gcc-ipq6018
- qcom,gcc-ipq8064
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v5 02/15] dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation
2022-02-24 16:48 ` [PATCH v5 02/15] dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation Ansuel Smith
@ 2022-02-24 18:46 ` Rob Herring
2022-02-24 18:50 ` Ansuel Smith
0 siblings, 1 reply; 38+ messages in thread
From: Rob Herring @ 2022-02-24 18:46 UTC (permalink / raw)
To: Ansuel Smith
Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Philipp Zabel, Taniya Das, linux-arm-msm, linux-clk, devicetree,
linux-kernel
On Thu, Feb 24, 2022 at 05:48:18PM +0100, Ansuel Smith wrote:
> Simplify qcon,gcc-apq8064 Documentation by using qcom,gcc.yaml as a
> template and remove the compatible from qcom,gcc.yaml
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
> .../bindings/clock/qcom,gcc-apq8064.yaml | 29 +++++--------------
> .../bindings/clock/qcom,gcc-other.yaml | 3 --
> 2 files changed, 7 insertions(+), 25 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
> index 8e2eac6cbfb9..97936411b6b4 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
> @@ -6,6 +6,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> title: Qualcomm Global Clock & Reset Controller Binding for APQ8064
>
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> maintainers:
> - Stephen Boyd <sboyd@kernel.org>
> - Taniya Das <tdas@codeaurora.org>
> @@ -17,22 +20,12 @@ description: |
> See also:
> - dt-bindings/clock/qcom,gcc-msm8960.h
> - dt-bindings/reset/qcom,gcc-msm8960.h
> + - dt-bindings/clock/qcom,gcc-apq8084.h
> + - dt-bindings/reset/qcom,gcc-apq8084.h
>
> properties:
> compatible:
> - const: qcom,gcc-apq8064
I assume you didn't mean to remove this?
> -
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> + const: qcom,gcc-apq8084
>
> nvmem-cells:
> minItems: 1
> @@ -53,21 +46,13 @@ properties:
> '#thermal-sensor-cells':
> const: 1
>
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
> - nvmem-cells
> - nvmem-cell-names
> - '#thermal-sensor-cells'
>
> -additionalProperties: false
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> index 4e5903bcd70d..47e1c5332d76 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> @@ -15,8 +15,6 @@ description:
> power domains.
>
> See also:
> - - dt-bindings/clock/qcom,gcc-apq8084.h
> - - dt-bindings/reset/qcom,gcc-apq8084.h
> - dt-bindings/clock/qcom,gcc-ipq4019.h
> - dt-bindings/clock/qcom,gcc-ipq6018.h
> - dt-bindings/reset/qcom,gcc-ipq6018.h
> @@ -40,7 +38,6 @@ allOf:
> properties:
> compatible:
> enum:
> - - qcom,gcc-apq8084
> - qcom,gcc-ipq4019
> - qcom,gcc-ipq6018
> - qcom,gcc-ipq8064
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 02/15] dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation
2022-02-24 18:46 ` Rob Herring
@ 2022-02-24 18:50 ` Ansuel Smith
0 siblings, 0 replies; 38+ messages in thread
From: Ansuel Smith @ 2022-02-24 18:50 UTC (permalink / raw)
To: Rob Herring
Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Philipp Zabel, Taniya Das, linux-arm-msm, linux-clk, devicetree,
linux-kernel
On Thu, Feb 24, 2022 at 12:46:01PM -0600, Rob Herring wrote:
> On Thu, Feb 24, 2022 at 05:48:18PM +0100, Ansuel Smith wrote:
> > Simplify qcon,gcc-apq8064 Documentation by using qcom,gcc.yaml as a
> > template and remove the compatible from qcom,gcc.yaml
> >
> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > ---
> > .../bindings/clock/qcom,gcc-apq8064.yaml | 29 +++++--------------
> > .../bindings/clock/qcom,gcc-other.yaml | 3 --
> > 2 files changed, 7 insertions(+), 25 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
> > index 8e2eac6cbfb9..97936411b6b4 100644
> > --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
> > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
> > @@ -6,6 +6,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> >
> > title: Qualcomm Global Clock & Reset Controller Binding for APQ8064
> >
> > +allOf:
> > + - $ref: qcom,gcc.yaml#
> > +
> > maintainers:
> > - Stephen Boyd <sboyd@kernel.org>
> > - Taniya Das <tdas@codeaurora.org>
> > @@ -17,22 +20,12 @@ description: |
> > See also:
> > - dt-bindings/clock/qcom,gcc-msm8960.h
> > - dt-bindings/reset/qcom,gcc-msm8960.h
> > + - dt-bindings/clock/qcom,gcc-apq8084.h
> > + - dt-bindings/reset/qcom,gcc-apq8084.h
> >
> > properties:
> > compatible:
> > - const: qcom,gcc-apq8064
>
> I assume you didn't mean to remove this?
>
Think you got confused by the patch?
> > -
> > - '#clock-cells':
> > - const: 1
> > -
> > - '#reset-cells':
> > - const: 1
> > -
> > - '#power-domain-cells':
> > - const: 1
> > -
> > - reg:
> > - maxItems: 1
> > + const: qcom,gcc-apq8084
The compatible is here. Or I'm missing something?
> >
> > nvmem-cells:
> > minItems: 1
> > @@ -53,21 +46,13 @@ properties:
> > '#thermal-sensor-cells':
> > const: 1
> >
> > - protected-clocks:
> > - description:
> > - Protected clock specifier list as per common clock binding.
> > -
> > required:
> > - compatible
> > - - reg
> > - - '#clock-cells'
> > - - '#reset-cells'
> > - - '#power-domain-cells'
> > - nvmem-cells
> > - nvmem-cell-names
> > - '#thermal-sensor-cells'
> >
> > -additionalProperties: false
> > +unevaluatedProperties: false
> >
> > examples:
> > - |
> > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> > index 4e5903bcd70d..47e1c5332d76 100644
> > --- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> > @@ -15,8 +15,6 @@ description:
> > power domains.
> >
> > See also:
> > - - dt-bindings/clock/qcom,gcc-apq8084.h
> > - - dt-bindings/reset/qcom,gcc-apq8084.h
> > - dt-bindings/clock/qcom,gcc-ipq4019.h
> > - dt-bindings/clock/qcom,gcc-ipq6018.h
> > - dt-bindings/reset/qcom,gcc-ipq6018.h
> > @@ -40,7 +38,6 @@ allOf:
> > properties:
> > compatible:
> > enum:
> > - - qcom,gcc-apq8084
> > - qcom,gcc-ipq4019
> > - qcom,gcc-ipq6018
> > - qcom,gcc-ipq8064
> > --
> > 2.34.1
> >
> >
--
Ansuel
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v5 03/15] dt-bindings: clock: document qcom,gcc-ipq8064 binding
2022-02-24 16:48 [PATCH v5 00/15] Multiple addition and improvement to ipq8064 gcc Ansuel Smith
2022-02-24 16:48 ` [PATCH v5 01/15] dt-bindings: clock: split qcom,gcc.yaml to common and specific schema Ansuel Smith
2022-02-24 16:48 ` [PATCH v5 02/15] dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation Ansuel Smith
@ 2022-02-24 16:48 ` Ansuel Smith
2022-02-24 19:09 ` Rob Herring
2022-02-24 22:07 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 04/15] clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0 Ansuel Smith
` (11 subsequent siblings)
14 siblings, 2 replies; 38+ messages in thread
From: Ansuel Smith @ 2022-02-24 16:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Philipp Zabel, Taniya Das, Ansuel Smith,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source
clocks. The gcc node is also used by the tsens driver, already documented,
to get the calib nvmem cells and the base reg from gcc. Use
qcom,gcc.yaml as a template and remove the compatible from
generic qcom,gcc-other.yaml
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
.../bindings/clock/qcom,gcc-ipq8064.yaml | 76 +++++++++++++++++++
.../bindings/clock/qcom,gcc-other.yaml | 3 -
2 files changed, 76 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
new file mode 100644
index 000000000000..9eb91dd22557
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+maintainers:
+ - Ansuel Smith <ansuelsmth@gmail.com>
+
+description: |
+ Qualcomm global clock control module which supports the clocks, resets and
+ power domains on IPQ8064.
+
+ See also:
+ - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
+ - dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
+
+properties:
+ compatible:
+ items:
+ - const: qcom,gcc-ipq8064
+ - const: syscon
+
+ clocks:
+ items:
+ - description: PXO source
+ - description: CXO source
+
+ clock-names:
+ items:
+ - const: pxo
+ - const: cxo
+
+ thermal-sensor:
+ type: object
+
+ allOf:
+ - $ref: /schemas/thermal/qcom-tsens.yaml#
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ gcc: clock-controller@900000 {
+ compatible = "qcom,gcc-ipq8064", "syscon";
+ reg = <0x00900000 0x4000>;
+ clocks = <&pxo_board>, <&cxo_board>;
+ clock-names = "pxo", "cxo";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+
+ tsens: thermal-sensor {
+ compatible = "qcom,ipq8064-tsens";
+
+ nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
+ nvmem-cell-names = "calib", "calib_backup";
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
+
+ #qcom,sensors = <11>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
index 47e1c5332d76..4dc0274dbd6b 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
@@ -18,8 +18,6 @@ description:
- dt-bindings/clock/qcom,gcc-ipq4019.h
- dt-bindings/clock/qcom,gcc-ipq6018.h
- dt-bindings/reset/qcom,gcc-ipq6018.h
- - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
- - dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
- dt-bindings/clock/qcom,gcc-msm8939.h
- dt-bindings/clock/qcom,gcc-msm8953.h
- dt-bindings/reset/qcom,gcc-msm8939.h
@@ -40,7 +38,6 @@ properties:
enum:
- qcom,gcc-ipq4019
- qcom,gcc-ipq6018
- - qcom,gcc-ipq8064
- qcom,gcc-mdm9607
- qcom,gcc-msm8226
- qcom,gcc-msm8660
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v5 03/15] dt-bindings: clock: document qcom,gcc-ipq8064 binding
2022-02-24 16:48 ` [PATCH v5 03/15] dt-bindings: clock: document qcom,gcc-ipq8064 binding Ansuel Smith
@ 2022-02-24 19:09 ` Rob Herring
2022-02-24 22:07 ` Stephen Boyd
1 sibling, 0 replies; 38+ messages in thread
From: Rob Herring @ 2022-02-24 19:09 UTC (permalink / raw)
To: Ansuel Smith
Cc: Philipp Zabel, linux-arm-msm, Rob Herring, linux-kernel,
devicetree, Andy Gross, Taniya Das, Bjorn Andersson,
Stephen Boyd, linux-clk, Michael Turquette
On Thu, 24 Feb 2022 17:48:19 +0100, Ansuel Smith wrote:
> Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source
> clocks. The gcc node is also used by the tsens driver, already documented,
> to get the calib nvmem cells and the base reg from gcc. Use
> qcom,gcc.yaml as a template and remove the compatible from
> generic qcom,gcc-other.yaml
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
> .../bindings/clock/qcom,gcc-ipq8064.yaml | 76 +++++++++++++++++++
> .../bindings/clock/qcom,gcc-other.yaml | 3 -
> 2 files changed, 76 insertions(+), 3 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 03/15] dt-bindings: clock: document qcom,gcc-ipq8064 binding
2022-02-24 16:48 ` [PATCH v5 03/15] dt-bindings: clock: document qcom,gcc-ipq8064 binding Ansuel Smith
2022-02-24 19:09 ` Rob Herring
@ 2022-02-24 22:07 ` Stephen Boyd
1 sibling, 0 replies; 38+ messages in thread
From: Stephen Boyd @ 2022-02-24 22:07 UTC (permalink / raw)
To: Andy Gross, Ansuel Smith, Bjorn Andersson, Michael Turquette,
Philipp Zabel, Rob Herring, Taniya Das, devicetree,
linux-arm-msm, linux-clk, linux-kernel
Quoting Ansuel Smith (2022-02-24 08:48:19)
> Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source
> clocks. The gcc node is also used by the tsens driver, already documented,
> to get the calib nvmem cells and the base reg from gcc. Use
> qcom,gcc.yaml as a template and remove the compatible from
> generic qcom,gcc-other.yaml
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v5 04/15] clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0
2022-02-24 16:48 [PATCH v5 00/15] Multiple addition and improvement to ipq8064 gcc Ansuel Smith
` (2 preceding siblings ...)
2022-02-24 16:48 ` [PATCH v5 03/15] dt-bindings: clock: document qcom,gcc-ipq8064 binding Ansuel Smith
@ 2022-02-24 16:48 ` Ansuel Smith
2022-02-24 22:07 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 05/15] clk: qcom: gcc-ipq806x: convert parent_names to parent_data Ansuel Smith
` (10 subsequent siblings)
14 siblings, 1 reply; 38+ messages in thread
From: Ansuel Smith @ 2022-02-24 16:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Philipp Zabel, Taniya Das, Ansuel Smith,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Parent gcc_pxo_pll8_pll0 had the parent definition and parent map
swapped. Fix this naming error.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index d6b7adb4be38..34cddf461dba 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -291,13 +291,13 @@ static const char * const gcc_pxo_pll3[] = {
"pll3",
};
-static const struct parent_map gcc_pxo_pll8_pll0[] = {
+static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 3 },
{ P_PLL0, 2 }
};
-static const char * const gcc_pxo_pll8_pll0_map[] = {
+static const char * const gcc_pxo_pll8_pll0[] = {
"pxo",
"pll8_vote",
"pll0_vote",
@@ -1993,7 +1993,7 @@ static struct clk_rcg usb30_master_clk_src = {
},
.s = {
.src_sel_shift = 0,
- .parent_map = gcc_pxo_pll8_pll0,
+ .parent_map = gcc_pxo_pll8_pll0_map,
},
.freq_tbl = clk_tbl_usb30_master,
.clkr = {
@@ -2001,7 +2001,7 @@ static struct clk_rcg usb30_master_clk_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb30_master_ref_src",
- .parent_names = gcc_pxo_pll8_pll0_map,
+ .parent_names = gcc_pxo_pll8_pll0,
.num_parents = 3,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -2063,7 +2063,7 @@ static struct clk_rcg usb30_utmi_clk = {
},
.s = {
.src_sel_shift = 0,
- .parent_map = gcc_pxo_pll8_pll0,
+ .parent_map = gcc_pxo_pll8_pll0_map,
},
.freq_tbl = clk_tbl_usb30_utmi,
.clkr = {
@@ -2071,7 +2071,7 @@ static struct clk_rcg usb30_utmi_clk = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb30_utmi_clk",
- .parent_names = gcc_pxo_pll8_pll0_map,
+ .parent_names = gcc_pxo_pll8_pll0,
.num_parents = 3,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -2133,7 +2133,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = {
},
.s = {
.src_sel_shift = 0,
- .parent_map = gcc_pxo_pll8_pll0,
+ .parent_map = gcc_pxo_pll8_pll0_map,
},
.freq_tbl = clk_tbl_usb,
.clkr = {
@@ -2141,7 +2141,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_src",
- .parent_names = gcc_pxo_pll8_pll0_map,
+ .parent_names = gcc_pxo_pll8_pll0,
.num_parents = 3,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -2197,7 +2197,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = {
},
.s = {
.src_sel_shift = 0,
- .parent_map = gcc_pxo_pll8_pll0,
+ .parent_map = gcc_pxo_pll8_pll0_map,
},
.freq_tbl = clk_tbl_usb,
.clkr = {
@@ -2205,7 +2205,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_src",
- .parent_names = gcc_pxo_pll8_pll0_map,
+ .parent_names = gcc_pxo_pll8_pll0,
.num_parents = 3,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v5 04/15] clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0
2022-02-24 16:48 ` [PATCH v5 04/15] clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0 Ansuel Smith
@ 2022-02-24 22:07 ` Stephen Boyd
0 siblings, 0 replies; 38+ messages in thread
From: Stephen Boyd @ 2022-02-24 22:07 UTC (permalink / raw)
To: Andy Gross, Ansuel Smith, Bjorn Andersson, Michael Turquette,
Philipp Zabel, Rob Herring, Taniya Das, devicetree,
linux-arm-msm, linux-clk, linux-kernel
Quoting Ansuel Smith (2022-02-24 08:48:20)
> Parent gcc_pxo_pll8_pll0 had the parent definition and parent map
> swapped. Fix this naming error.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v5 05/15] clk: qcom: gcc-ipq806x: convert parent_names to parent_data
2022-02-24 16:48 [PATCH v5 00/15] Multiple addition and improvement to ipq8064 gcc Ansuel Smith
` (3 preceding siblings ...)
2022-02-24 16:48 ` [PATCH v5 04/15] clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0 Ansuel Smith
@ 2022-02-24 16:48 ` Ansuel Smith
2022-02-24 22:09 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 06/15] clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents Ansuel Smith
` (9 subsequent siblings)
14 siblings, 1 reply; 38+ messages in thread
From: Ansuel Smith @ 2022-02-24 16:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Philipp Zabel, Taniya Das, Ansuel Smith,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Convert parent_names to parent_data to modernize the driver.
Where possible use parent_hws directly.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/clk/qcom/gcc-ipq806x.c | 293 ++++++++++++++++++++-------------
1 file changed, 180 insertions(+), 113 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 34cddf461dba..f18888454b4f 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -25,6 +25,11 @@
#include "clk-hfpll.h"
#include "reset.h"
+static const struct clk_parent_data gcc_pxo[] = {
+ { .fw_name = "pxo" },
+ { .name = "pxo" },
+};
+
static struct clk_pll pll0 = {
.l_reg = 0x30c4,
.m_reg = 0x30c8,
@@ -35,7 +40,7 @@ static struct clk_pll pll0 = {
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll0",
- .parent_names = (const char *[]){ "pxo" },
+ .parent_data = gcc_pxo,
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -46,7 +51,9 @@ static struct clk_regmap pll0_vote = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "pll0_vote",
- .parent_names = (const char *[]){ "pll0" },
+ .parent_hws = (const struct clk_hw*[]){
+ &pll0.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@@ -62,7 +69,7 @@ static struct clk_pll pll3 = {
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll3",
- .parent_names = (const char *[]){ "pxo" },
+ .parent_data = gcc_pxo,
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -89,7 +96,7 @@ static struct clk_pll pll8 = {
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll8",
- .parent_names = (const char *[]){ "pxo" },
+ .parent_data = gcc_pxo,
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -100,7 +107,9 @@ static struct clk_regmap pll8_vote = {
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "pll8_vote",
- .parent_names = (const char *[]){ "pll8" },
+ .parent_hws = (const struct clk_hw*[]){
+ &pll8.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@@ -123,7 +132,7 @@ static struct hfpll_data hfpll0_data = {
static struct clk_hfpll hfpll0 = {
.d = &hfpll0_data,
.clkr.hw.init = &(struct clk_init_data){
- .parent_names = (const char *[]){ "pxo" },
+ .parent_data = gcc_pxo,
.num_parents = 1,
.name = "hfpll0",
.ops = &clk_ops_hfpll,
@@ -149,7 +158,7 @@ static struct hfpll_data hfpll1_data = {
static struct clk_hfpll hfpll1 = {
.d = &hfpll1_data,
.clkr.hw.init = &(struct clk_init_data){
- .parent_names = (const char *[]){ "pxo" },
+ .parent_data = gcc_pxo,
.num_parents = 1,
.name = "hfpll1",
.ops = &clk_ops_hfpll,
@@ -175,7 +184,7 @@ static struct hfpll_data hfpll_l2_data = {
static struct clk_hfpll hfpll_l2 = {
.d = &hfpll_l2_data,
.clkr.hw.init = &(struct clk_init_data){
- .parent_names = (const char *[]){ "pxo" },
+ .parent_data = gcc_pxo,
.num_parents = 1,
.name = "hfpll_l2",
.ops = &clk_ops_hfpll,
@@ -194,7 +203,7 @@ static struct clk_pll pll14 = {
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll14",
- .parent_names = (const char *[]){ "pxo" },
+ .parent_data = gcc_pxo,
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -205,7 +214,9 @@ static struct clk_regmap pll14_vote = {
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "pll14_vote",
- .parent_names = (const char *[]){ "pll14" },
+ .parent_hws = (const struct clk_hw*[]){
+ &pll14.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@@ -238,7 +249,7 @@ static struct clk_pll pll18 = {
.freq_tbl = pll18_freq_tbl,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll18",
- .parent_names = (const char *[]){ "pxo" },
+ .parent_data = gcc_pxo,
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -259,9 +270,10 @@ static const struct parent_map gcc_pxo_pll8_map[] = {
{ P_PLL8, 3 }
};
-static const char * const gcc_pxo_pll8[] = {
- "pxo",
- "pll8_vote",
+static const struct clk_parent_data gcc_pxo_pll8[] = {
+ { .fw_name = "pxo" },
+ { .name = "pxo" },
+ { .hw = &pll8_vote.hw },
};
static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
@@ -270,10 +282,12 @@ static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
{ P_CXO, 5 }
};
-static const char * const gcc_pxo_pll8_cxo[] = {
- "pxo",
- "pll8_vote",
- "cxo",
+static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
+ { .fw_name = "pxo" },
+ { .name = "pxo" },
+ { .hw = &pll8_vote.hw },
+ { .fw_name = "cxo" },
+ { .name = "cxo" },
};
static const struct parent_map gcc_pxo_pll3_map[] = {
@@ -286,9 +300,10 @@ static const struct parent_map gcc_pxo_pll3_sata_map[] = {
{ P_PLL3, 6 }
};
-static const char * const gcc_pxo_pll3[] = {
- "pxo",
- "pll3",
+static const struct clk_parent_data gcc_pxo_pll3[] = {
+ { .fw_name = "pxo" },
+ { .name = "pxo" },
+ { .hw = &pll3.clkr.hw },
};
static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
@@ -297,10 +312,11 @@ static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
{ P_PLL0, 2 }
};
-static const char * const gcc_pxo_pll8_pll0[] = {
- "pxo",
- "pll8_vote",
- "pll0_vote",
+static const struct clk_parent_data gcc_pxo_pll8_pll0[] = {
+ { .fw_name = "pxo" },
+ { .name = "pxo" },
+ { .hw = &pll8_vote.hw },
+ { .hw = &pll0_vote.hw },
};
static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
@@ -311,12 +327,13 @@ static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
{ P_PLL18, 1 }
};
-static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = {
- "pxo",
- "pll8_vote",
- "pll0_vote",
- "pll14",
- "pll18",
+static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = {
+ { .fw_name = "pxo" },
+ { .name = "pxo" },
+ { .hw = &pll8_vote.hw },
+ { .hw = &pll0_vote.hw },
+ { .hw = &pll14.clkr.hw },
+ { .hw = &pll18.clkr.hw },
};
static struct freq_tbl clk_tbl_gsbi_uart[] = {
@@ -362,7 +379,7 @@ static struct clk_rcg gsbi1_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -378,8 +395,8 @@ static struct clk_branch gsbi1_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_clk",
- .parent_names = (const char *[]){
- "gsbi1_uart_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi1_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -413,7 +430,7 @@ static struct clk_rcg gsbi2_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -429,8 +446,8 @@ static struct clk_branch gsbi2_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_clk",
- .parent_names = (const char *[]){
- "gsbi2_uart_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi2_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -464,7 +481,7 @@ static struct clk_rcg gsbi4_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -480,8 +497,8 @@ static struct clk_branch gsbi4_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_clk",
- .parent_names = (const char *[]){
- "gsbi4_uart_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi4_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -515,7 +532,7 @@ static struct clk_rcg gsbi5_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -531,8 +548,8 @@ static struct clk_branch gsbi5_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_clk",
- .parent_names = (const char *[]){
- "gsbi5_uart_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi5_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -566,7 +583,7 @@ static struct clk_rcg gsbi6_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_uart_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -582,8 +599,8 @@ static struct clk_branch gsbi6_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_uart_clk",
- .parent_names = (const char *[]){
- "gsbi6_uart_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi6_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -617,7 +634,7 @@ static struct clk_rcg gsbi7_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_uart_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -633,8 +650,8 @@ static struct clk_branch gsbi7_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_uart_clk",
- .parent_names = (const char *[]){
- "gsbi7_uart_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi7_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -681,7 +698,7 @@ static struct clk_rcg gsbi1_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -697,7 +714,9 @@ static struct clk_branch gsbi1_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_clk",
- .parent_names = (const char *[]){ "gsbi1_qup_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi1_qup_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -730,7 +749,7 @@ static struct clk_rcg gsbi2_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -746,7 +765,9 @@ static struct clk_branch gsbi2_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_clk",
- .parent_names = (const char *[]){ "gsbi2_qup_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi2_qup_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -779,7 +800,7 @@ static struct clk_rcg gsbi4_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -795,7 +816,9 @@ static struct clk_branch gsbi4_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_clk",
- .parent_names = (const char *[]){ "gsbi4_qup_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi4_qup_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -828,7 +851,7 @@ static struct clk_rcg gsbi5_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -844,7 +867,9 @@ static struct clk_branch gsbi5_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_clk",
- .parent_names = (const char *[]){ "gsbi5_qup_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi5_qup_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -877,7 +902,7 @@ static struct clk_rcg gsbi6_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_qup_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -893,7 +918,9 @@ static struct clk_branch gsbi6_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_qup_clk",
- .parent_names = (const char *[]){ "gsbi6_qup_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi6_qup_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -926,7 +953,7 @@ static struct clk_rcg gsbi7_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_qup_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -942,7 +969,9 @@ static struct clk_branch gsbi7_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_qup_clk",
- .parent_names = (const char *[]){ "gsbi7_qup_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi7_qup_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1076,7 +1105,7 @@ static struct clk_rcg gp0_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp0_src",
- .parent_names = gcc_pxo_pll8_cxo,
+ .parent_data = gcc_pxo_pll8_cxo,
.num_parents = 3,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -1092,7 +1121,9 @@ static struct clk_branch gp0_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp0_clk",
- .parent_names = (const char *[]){ "gp0_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gp0_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1125,7 +1156,7 @@ static struct clk_rcg gp1_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp1_src",
- .parent_names = gcc_pxo_pll8_cxo,
+ .parent_data = gcc_pxo_pll8_cxo,
.num_parents = 3,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -1141,7 +1172,9 @@ static struct clk_branch gp1_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp1_clk",
- .parent_names = (const char *[]){ "gp1_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gp1_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1174,7 +1207,7 @@ static struct clk_rcg gp2_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp2_src",
- .parent_names = gcc_pxo_pll8_cxo,
+ .parent_data = gcc_pxo_pll8_cxo,
.num_parents = 3,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -1190,7 +1223,9 @@ static struct clk_branch gp2_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp2_clk",
- .parent_names = (const char *[]){ "gp2_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gp2_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1228,7 +1263,7 @@ static struct clk_rcg prng_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "prng_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
},
@@ -1244,7 +1279,9 @@ static struct clk_branch prng_clk = {
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "prng_clk",
- .parent_names = (const char *[]){ "prng_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &prng_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
},
@@ -1290,7 +1327,7 @@ static struct clk_rcg sdc1_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc1_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
},
@@ -1305,7 +1342,9 @@ static struct clk_branch sdc1_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc1_clk",
- .parent_names = (const char *[]){ "sdc1_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &sdc1_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1338,7 +1377,7 @@ static struct clk_rcg sdc3_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc3_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
},
@@ -1353,7 +1392,9 @@ static struct clk_branch sdc3_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc3_clk",
- .parent_names = (const char *[]){ "sdc3_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &sdc3_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1421,7 +1462,7 @@ static struct clk_rcg tsif_ref_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "tsif_ref_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
},
@@ -1436,7 +1477,9 @@ static struct clk_branch tsif_ref_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "tsif_ref_clk",
- .parent_names = (const char *[]){ "tsif_ref_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &tsif_ref_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1583,7 +1626,7 @@ static struct clk_rcg pcie_ref_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "pcie_ref_src",
- .parent_names = gcc_pxo_pll3,
+ .parent_data = gcc_pxo_pll3,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -1599,7 +1642,9 @@ static struct clk_branch pcie_ref_src_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "pcie_ref_src_clk",
- .parent_names = (const char *[]){ "pcie_ref_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &pcie_ref_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1675,7 +1720,7 @@ static struct clk_rcg pcie1_ref_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "pcie1_ref_src",
- .parent_names = gcc_pxo_pll3,
+ .parent_data = gcc_pxo_pll3,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -1691,7 +1736,9 @@ static struct clk_branch pcie1_ref_src_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "pcie1_ref_src_clk",
- .parent_names = (const char *[]){ "pcie1_ref_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &pcie1_ref_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1767,7 +1814,7 @@ static struct clk_rcg pcie2_ref_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "pcie2_ref_src",
- .parent_names = gcc_pxo_pll3,
+ .parent_data = gcc_pxo_pll3,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -1783,7 +1830,9 @@ static struct clk_branch pcie2_ref_src_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "pcie2_ref_src_clk",
- .parent_names = (const char *[]){ "pcie2_ref_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &pcie2_ref_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1864,7 +1913,7 @@ static struct clk_rcg sata_ref_src = {
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "sata_ref_src",
- .parent_names = gcc_pxo_pll3,
+ .parent_data = gcc_pxo_pll3,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -1880,7 +1929,9 @@ static struct clk_branch sata_rxoob_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sata_rxoob_clk",
- .parent_names = (const char *[]){ "sata_ref_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &sata_ref_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1896,7 +1947,9 @@ static struct clk_branch sata_pmalive_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sata_pmalive_clk",
- .parent_names = (const char *[]){ "sata_ref_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &sata_ref_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1912,7 +1965,7 @@ static struct clk_branch sata_phy_ref_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sata_phy_ref_clk",
- .parent_names = (const char *[]){ "pxo" },
+ .parent_data = gcc_pxo,
.num_parents = 1,
.ops = &clk_branch_ops,
},
@@ -2001,7 +2054,7 @@ static struct clk_rcg usb30_master_clk_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb30_master_ref_src",
- .parent_names = gcc_pxo_pll8_pll0,
+ .parent_data = gcc_pxo_pll8_pll0,
.num_parents = 3,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -2017,7 +2070,9 @@ static struct clk_branch usb30_0_branch_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb30_0_branch_clk",
- .parent_names = (const char *[]){ "usb30_master_ref_src", },
+ .parent_hws = (const struct clk_hw*[]){
+ &usb30_master_clk_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -2033,7 +2088,9 @@ static struct clk_branch usb30_1_branch_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb30_1_branch_clk",
- .parent_names = (const char *[]){ "usb30_master_ref_src", },
+ .parent_hws = (const struct clk_hw*[]){
+ &usb30_master_clk_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -2071,7 +2128,7 @@ static struct clk_rcg usb30_utmi_clk = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb30_utmi_clk",
- .parent_names = gcc_pxo_pll8_pll0,
+ .parent_data = gcc_pxo_pll8_pll0,
.num_parents = 3,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -2087,7 +2144,9 @@ static struct clk_branch usb30_0_utmi_clk_ctl = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb30_0_utmi_clk_ctl",
- .parent_names = (const char *[]){ "usb30_utmi_clk", },
+ .parent_hws = (const struct clk_hw*[]){
+ &usb30_utmi_clk.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -2103,7 +2162,9 @@ static struct clk_branch usb30_1_utmi_clk_ctl = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb30_1_utmi_clk_ctl",
- .parent_names = (const char *[]){ "usb30_utmi_clk", },
+ .parent_hws = (const struct clk_hw*[]){
+ &usb30_utmi_clk.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -2141,7 +2202,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_src",
- .parent_names = gcc_pxo_pll8_pll0,
+ .parent_data = gcc_pxo_pll8_pll0,
.num_parents = 3,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -2157,7 +2218,9 @@ static struct clk_branch usb_hs1_xcvr_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_clk",
- .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &usb_hs1_xcvr_clk_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -2205,7 +2268,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_src",
- .parent_names = gcc_pxo_pll8_pll0,
+ .parent_data = gcc_pxo_pll8_pll0,
.num_parents = 3,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -2221,7 +2284,9 @@ static struct clk_branch usb_fs1_xcvr_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_clk",
- .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
+ .parent_hws = (const struct clk_hw*[]){
+ &usb_fs1_xcvr_clk_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -2237,7 +2302,9 @@ static struct clk_branch usb_fs1_sys_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_sys_clk",
- .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
+ .parent_hws = (const struct clk_hw*[]){
+ &usb_fs1_xcvr_clk_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -2337,7 +2404,7 @@ static struct clk_dyn_rcg gmac_core1_src = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gmac_core1_src",
- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = 5,
.ops = &clk_dyn_rcg_ops,
},
@@ -2354,8 +2421,8 @@ static struct clk_branch gmac_core1_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gmac_core1_clk",
- .parent_names = (const char *[]){
- "gmac_core1_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gmac_core1_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -2409,7 +2476,7 @@ static struct clk_dyn_rcg gmac_core2_src = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gmac_core2_src",
- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = 5,
.ops = &clk_dyn_rcg_ops,
},
@@ -2426,8 +2493,8 @@ static struct clk_branch gmac_core2_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gmac_core2_clk",
- .parent_names = (const char *[]){
- "gmac_core2_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gmac_core2_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -2481,7 +2548,7 @@ static struct clk_dyn_rcg gmac_core3_src = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gmac_core3_src",
- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = 5,
.ops = &clk_dyn_rcg_ops,
},
@@ -2498,8 +2565,8 @@ static struct clk_branch gmac_core3_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gmac_core3_clk",
- .parent_names = (const char *[]){
- "gmac_core3_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gmac_core3_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -2553,7 +2620,7 @@ static struct clk_dyn_rcg gmac_core4_src = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gmac_core4_src",
- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = 5,
.ops = &clk_dyn_rcg_ops,
},
@@ -2570,8 +2637,8 @@ static struct clk_branch gmac_core4_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gmac_core4_clk",
- .parent_names = (const char *[]){
- "gmac_core4_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gmac_core4_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -2613,7 +2680,7 @@ static struct clk_dyn_rcg nss_tcm_src = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "nss_tcm_src",
- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = 5,
.ops = &clk_dyn_rcg_ops,
},
@@ -2628,8 +2695,8 @@ static struct clk_branch nss_tcm_clk = {
.enable_mask = BIT(6) | BIT(4),
.hw.init = &(struct clk_init_data){
.name = "nss_tcm_clk",
- .parent_names = (const char *[]){
- "nss_tcm_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &nss_tcm_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -2691,7 +2758,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "ubi32_core1_src_clk",
- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = 5,
.ops = &clk_dyn_rcg_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
@@ -2744,7 +2811,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "ubi32_core2_src_clk",
- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = 5,
.ops = &clk_dyn_rcg_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v5 05/15] clk: qcom: gcc-ipq806x: convert parent_names to parent_data
2022-02-24 16:48 ` [PATCH v5 05/15] clk: qcom: gcc-ipq806x: convert parent_names to parent_data Ansuel Smith
@ 2022-02-24 22:09 ` Stephen Boyd
0 siblings, 0 replies; 38+ messages in thread
From: Stephen Boyd @ 2022-02-24 22:09 UTC (permalink / raw)
To: Andy Gross, Ansuel Smith, Bjorn Andersson, Michael Turquette,
Philipp Zabel, Rob Herring, Taniya Das, devicetree,
linux-arm-msm, linux-clk, linux-kernel
Quoting Ansuel Smith (2022-02-24 08:48:21)
> Convert parent_names to parent_data to modernize the driver.
> Where possible use parent_hws directly.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
> drivers/clk/qcom/gcc-ipq806x.c | 293 ++++++++++++++++++++-------------
> 1 file changed, 180 insertions(+), 113 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
> index 34cddf461dba..f18888454b4f 100644
> --- a/drivers/clk/qcom/gcc-ipq806x.c
> +++ b/drivers/clk/qcom/gcc-ipq806x.c
> @@ -25,6 +25,11 @@
> #include "clk-hfpll.h"
> #include "reset.h"
>
> +static const struct clk_parent_data gcc_pxo[] = {
> + { .fw_name = "pxo" },
> + { .name = "pxo" },
This is supposed to be one element, not two?
{ .fw_name = "pxo", .name = "pxo" }
> +};
> +
> static struct clk_pll pll0 = {
> .l_reg = 0x30c4,
> .m_reg = 0x30c8,
> @@ -259,9 +270,10 @@ static const struct parent_map gcc_pxo_pll8_map[] = {
> { P_PLL8, 3 }
> };
>
> -static const char * const gcc_pxo_pll8[] = {
> - "pxo",
> - "pll8_vote",
> +static const struct clk_parent_data gcc_pxo_pll8[] = {
> + { .fw_name = "pxo" },
> + { .name = "pxo" },
> + { .hw = &pll8_vote.hw },
> };
>
> static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
> @@ -270,10 +282,12 @@ static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
> { P_CXO, 5 }
> };
>
> -static const char * const gcc_pxo_pll8_cxo[] = {
> - "pxo",
> - "pll8_vote",
> - "cxo",
> +static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
> + { .fw_name = "pxo" },
> + { .name = "pxo" },
> + { .hw = &pll8_vote.hw },
> + { .fw_name = "cxo" },
> + { .name = "cxo" },
> };
>
> static const struct parent_map gcc_pxo_pll3_map[] = {
> @@ -286,9 +300,10 @@ static const struct parent_map gcc_pxo_pll3_sata_map[] = {
> { P_PLL3, 6 }
> };
>
> -static const char * const gcc_pxo_pll3[] = {
> - "pxo",
> - "pll3",
> +static const struct clk_parent_data gcc_pxo_pll3[] = {
> + { .fw_name = "pxo" },
> + { .name = "pxo" },
> + { .hw = &pll3.clkr.hw },
> };
>
> static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
> @@ -297,10 +312,11 @@ static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
> { P_PLL0, 2 }
> };
>
> -static const char * const gcc_pxo_pll8_pll0[] = {
> - "pxo",
> - "pll8_vote",
> - "pll0_vote",
> +static const struct clk_parent_data gcc_pxo_pll8_pll0[] = {
> + { .fw_name = "pxo" },
> + { .name = "pxo" },
Same comment for these ones
> + { .hw = &pll8_vote.hw },
> + { .hw = &pll0_vote.hw },
> };
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v5 06/15] clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents
2022-02-24 16:48 [PATCH v5 00/15] Multiple addition and improvement to ipq8064 gcc Ansuel Smith
` (4 preceding siblings ...)
2022-02-24 16:48 ` [PATCH v5 05/15] clk: qcom: gcc-ipq806x: convert parent_names to parent_data Ansuel Smith
@ 2022-02-24 16:48 ` Ansuel Smith
2022-02-24 22:09 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 07/15] clk: qcom: gcc-ipq806x: add additional freq nss cores Ansuel Smith
` (8 subsequent siblings)
14 siblings, 1 reply; 38+ messages in thread
From: Ansuel Smith @ 2022-02-24 16:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Philipp Zabel, Taniya Das, Ansuel Smith,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Use ARRAY_SIZE for num_parents instead of hardcoding the value.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
drivers/clk/qcom/gcc-ipq806x.c | 68 +++++++++++++++++-----------------
1 file changed, 34 insertions(+), 34 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index f18888454b4f..3a9001830f0c 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -380,7 +380,7 @@ static struct clk_rcg gsbi1_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -431,7 +431,7 @@ static struct clk_rcg gsbi2_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -482,7 +482,7 @@ static struct clk_rcg gsbi4_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -533,7 +533,7 @@ static struct clk_rcg gsbi5_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -584,7 +584,7 @@ static struct clk_rcg gsbi6_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi6_uart_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -635,7 +635,7 @@ static struct clk_rcg gsbi7_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi7_uart_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -699,7 +699,7 @@ static struct clk_rcg gsbi1_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -750,7 +750,7 @@ static struct clk_rcg gsbi2_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -801,7 +801,7 @@ static struct clk_rcg gsbi4_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -852,7 +852,7 @@ static struct clk_rcg gsbi5_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -903,7 +903,7 @@ static struct clk_rcg gsbi6_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi6_qup_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -954,7 +954,7 @@ static struct clk_rcg gsbi7_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi7_qup_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1106,7 +1106,7 @@ static struct clk_rcg gp0_src = {
.hw.init = &(struct clk_init_data){
.name = "gp0_src",
.parent_data = gcc_pxo_pll8_cxo,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1157,7 +1157,7 @@ static struct clk_rcg gp1_src = {
.hw.init = &(struct clk_init_data){
.name = "gp1_src",
.parent_data = gcc_pxo_pll8_cxo,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1208,7 +1208,7 @@ static struct clk_rcg gp2_src = {
.hw.init = &(struct clk_init_data){
.name = "gp2_src",
.parent_data = gcc_pxo_pll8_cxo,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1264,7 +1264,7 @@ static struct clk_rcg prng_src = {
.hw.init = &(struct clk_init_data){
.name = "prng_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
},
@@ -1328,7 +1328,7 @@ static struct clk_rcg sdc1_src = {
.hw.init = &(struct clk_init_data){
.name = "sdc1_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -1378,7 +1378,7 @@ static struct clk_rcg sdc3_src = {
.hw.init = &(struct clk_init_data){
.name = "sdc3_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -1463,7 +1463,7 @@ static struct clk_rcg tsif_ref_src = {
.hw.init = &(struct clk_init_data){
.name = "tsif_ref_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -1627,7 +1627,7 @@ static struct clk_rcg pcie_ref_src = {
.hw.init = &(struct clk_init_data){
.name = "pcie_ref_src",
.parent_data = gcc_pxo_pll3,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1721,7 +1721,7 @@ static struct clk_rcg pcie1_ref_src = {
.hw.init = &(struct clk_init_data){
.name = "pcie1_ref_src",
.parent_data = gcc_pxo_pll3,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1815,7 +1815,7 @@ static struct clk_rcg pcie2_ref_src = {
.hw.init = &(struct clk_init_data){
.name = "pcie2_ref_src",
.parent_data = gcc_pxo_pll3,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1914,7 +1914,7 @@ static struct clk_rcg sata_ref_src = {
.hw.init = &(struct clk_init_data){
.name = "sata_ref_src",
.parent_data = gcc_pxo_pll3,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2055,7 +2055,7 @@ static struct clk_rcg usb30_master_clk_src = {
.hw.init = &(struct clk_init_data){
.name = "usb30_master_ref_src",
.parent_data = gcc_pxo_pll8_pll0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2129,7 +2129,7 @@ static struct clk_rcg usb30_utmi_clk = {
.hw.init = &(struct clk_init_data){
.name = "usb30_utmi_clk",
.parent_data = gcc_pxo_pll8_pll0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2203,7 +2203,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = {
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_src",
.parent_data = gcc_pxo_pll8_pll0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2269,7 +2269,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = {
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_src",
.parent_data = gcc_pxo_pll8_pll0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2405,7 +2405,7 @@ static struct clk_dyn_rcg gmac_core1_src = {
.hw.init = &(struct clk_init_data){
.name = "gmac_core1_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
@@ -2477,7 +2477,7 @@ static struct clk_dyn_rcg gmac_core2_src = {
.hw.init = &(struct clk_init_data){
.name = "gmac_core2_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
@@ -2549,7 +2549,7 @@ static struct clk_dyn_rcg gmac_core3_src = {
.hw.init = &(struct clk_init_data){
.name = "gmac_core3_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
@@ -2621,7 +2621,7 @@ static struct clk_dyn_rcg gmac_core4_src = {
.hw.init = &(struct clk_init_data){
.name = "gmac_core4_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
@@ -2681,7 +2681,7 @@ static struct clk_dyn_rcg nss_tcm_src = {
.hw.init = &(struct clk_init_data){
.name = "nss_tcm_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
@@ -2759,7 +2759,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = {
.hw.init = &(struct clk_init_data){
.name = "ubi32_core1_src_clk",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
},
@@ -2812,7 +2812,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
.hw.init = &(struct clk_init_data){
.name = "ubi32_core2_src_clk",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
},
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v5 06/15] clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents
2022-02-24 16:48 ` [PATCH v5 06/15] clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents Ansuel Smith
@ 2022-02-24 22:09 ` Stephen Boyd
0 siblings, 0 replies; 38+ messages in thread
From: Stephen Boyd @ 2022-02-24 22:09 UTC (permalink / raw)
To: Andy Gross, Ansuel Smith, Bjorn Andersson, Michael Turquette,
Philipp Zabel, Rob Herring, Taniya Das, devicetree,
linux-arm-msm, linux-clk, linux-kernel
Quoting Ansuel Smith (2022-02-24 08:48:22)
> Use ARRAY_SIZE for num_parents instead of hardcoding the value.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v5 07/15] clk: qcom: gcc-ipq806x: add additional freq nss cores
2022-02-24 16:48 [PATCH v5 00/15] Multiple addition and improvement to ipq8064 gcc Ansuel Smith
` (5 preceding siblings ...)
2022-02-24 16:48 ` [PATCH v5 06/15] clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents Ansuel Smith
@ 2022-02-24 16:48 ` Ansuel Smith
2022-02-24 22:10 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 08/15] clk: qcom: gcc-ipq806x: add unusued flag for critical clock Ansuel Smith
` (7 subsequent siblings)
14 siblings, 1 reply; 38+ messages in thread
From: Ansuel Smith @ 2022-02-24 16:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Philipp Zabel, Taniya Das, Ansuel Smith,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be
clocked to 800MHz. Add these missing freq to the gcc driver.
Set the freq_tbl for the ubi32_cores to the correct values based on the
machine compatible.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/clk/qcom/gcc-ipq806x.c | 24 +++++++++++++++++++++---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 3a9001830f0c..0a3ba3480de8 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -233,7 +233,9 @@ static struct clk_regmap pll14_vote = {
static struct pll_freq_tbl pll18_freq_tbl[] = {
NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
+ NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
+ NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
};
static struct clk_pll pll18 = {
@@ -2705,7 +2707,7 @@ static struct clk_branch nss_tcm_clk = {
},
};
-static const struct freq_tbl clk_tbl_nss[] = {
+static const struct freq_tbl clk_tbl_nss_ipq8064[] = {
{ 110000000, P_PLL18, 1, 1, 5 },
{ 275000000, P_PLL18, 2, 0, 0 },
{ 550000000, P_PLL18, 1, 0, 0 },
@@ -2713,6 +2715,14 @@ static const struct freq_tbl clk_tbl_nss[] = {
{ }
};
+static const struct freq_tbl clk_tbl_nss_ipq8065[] = {
+ { 110000000, P_PLL18, 1, 1, 5 },
+ { 275000000, P_PLL18, 2, 0, 0 },
+ { 600000000, P_PLL18, 1, 0, 0 },
+ { 800000000, P_PLL18, 1, 0, 0 },
+ { }
+};
+
static struct clk_dyn_rcg ubi32_core1_src_clk = {
.ns_reg[0] = 0x3d2c,
.ns_reg[1] = 0x3d30,
@@ -2752,7 +2762,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = {
.pre_div_width = 2,
},
.mux_sel_bit = 0,
- .freq_tbl = clk_tbl_nss,
+ /* nss freq table is selected based on the SoC compatible */
.clkr = {
.enable_reg = 0x3d20,
.enable_mask = BIT(1),
@@ -2805,7 +2815,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
.pre_div_width = 2,
},
.mux_sel_bit = 0,
- .freq_tbl = clk_tbl_nss,
+ /* nss freq table is selected based on the SoC compatible */
.clkr = {
.enable_reg = 0x3d40,
.enable_mask = BIT(1),
@@ -3138,6 +3148,14 @@ static int gcc_ipq806x_probe(struct platform_device *pdev)
if (ret)
return ret;
+ if (of_machine_is_compatible("qcom,ipq8065")) {
+ ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
+ ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
+ } else {
+ ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8064;
+ ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8064;
+ }
+
ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc);
if (ret)
return ret;
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v5 07/15] clk: qcom: gcc-ipq806x: add additional freq nss cores
2022-02-24 16:48 ` [PATCH v5 07/15] clk: qcom: gcc-ipq806x: add additional freq nss cores Ansuel Smith
@ 2022-02-24 22:10 ` Stephen Boyd
0 siblings, 0 replies; 38+ messages in thread
From: Stephen Boyd @ 2022-02-24 22:10 UTC (permalink / raw)
To: Andy Gross, Ansuel Smith, Bjorn Andersson, Michael Turquette,
Philipp Zabel, Rob Herring, Taniya Das, devicetree,
linux-arm-msm, linux-clk, linux-kernel
Quoting Ansuel Smith (2022-02-24 08:48:23)
> Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be
> clocked to 800MHz. Add these missing freq to the gcc driver.
> Set the freq_tbl for the ubi32_cores to the correct values based on the
> machine compatible.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v5 08/15] clk: qcom: gcc-ipq806x: add unusued flag for critical clock
2022-02-24 16:48 [PATCH v5 00/15] Multiple addition and improvement to ipq8064 gcc Ansuel Smith
` (6 preceding siblings ...)
2022-02-24 16:48 ` [PATCH v5 07/15] clk: qcom: gcc-ipq806x: add additional freq nss cores Ansuel Smith
@ 2022-02-24 16:48 ` Ansuel Smith
2022-02-24 16:48 ` [PATCH v5 09/15] clk: qcom: clk-rcg: add clk_rcg_floor_ops ops Ansuel Smith
` (6 subsequent siblings)
14 siblings, 0 replies; 38+ messages in thread
From: Ansuel Smith @ 2022-02-24 16:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Philipp Zabel, Taniya Das, Ansuel Smith,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Some clocks are used by other devices present on the SoC. For example
the gsbi4_h_clk is used by RPM and is if disabled cause the RPM to
reject any regulator change command. These clock should never be
disabled.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/clk/qcom/gcc-ipq806x.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 0a3ba3480de8..49a4eae4161f 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -805,7 +805,7 @@ static struct clk_rcg gsbi4_qup_src = {
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
},
},
};
@@ -823,7 +823,7 @@ static struct clk_branch gsbi4_qup_clk = {
},
.num_parents = 1,
.ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
},
};
@@ -907,7 +907,7 @@ static struct clk_rcg gsbi6_qup_src = {
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
},
},
};
@@ -976,7 +976,7 @@ static struct clk_branch gsbi7_qup_clk = {
},
.num_parents = 1,
.ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
},
};
@@ -1022,6 +1022,7 @@ static struct clk_branch gsbi4_h_clk = {
.hw.init = &(struct clk_init_data){
.name = "gsbi4_h_clk",
.ops = &clk_branch_ops,
+ .flags = CLK_IGNORE_UNUSED,
},
},
};
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v5 09/15] clk: qcom: clk-rcg: add clk_rcg_floor_ops ops
2022-02-24 16:48 [PATCH v5 00/15] Multiple addition and improvement to ipq8064 gcc Ansuel Smith
` (7 preceding siblings ...)
2022-02-24 16:48 ` [PATCH v5 08/15] clk: qcom: gcc-ipq806x: add unusued flag for critical clock Ansuel Smith
@ 2022-02-24 16:48 ` Ansuel Smith
2022-02-24 22:11 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 10/15] clk: qcom: gcc-ipq806x: add additional freq for sdc table Ansuel Smith
` (5 subsequent siblings)
14 siblings, 1 reply; 38+ messages in thread
From: Ansuel Smith @ 2022-02-24 16:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Philipp Zabel, Taniya Das, Ansuel Smith,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Add clk_rcg_floor_ops for clock that can't provide a stable freq and
require to use a floor freq to provide the requested frequency.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
drivers/clk/qcom/clk-rcg.c | 24 ++++++++++++++++++++++++
drivers/clk/qcom/clk-rcg.h | 1 +
2 files changed, 25 insertions(+)
diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
index a9d181d6be21..88845baa7f84 100644
--- a/drivers/clk/qcom/clk-rcg.c
+++ b/drivers/clk/qcom/clk-rcg.c
@@ -526,6 +526,19 @@ static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
return __clk_rcg_set_rate(rcg, f);
}
+static int clk_rcg_set_floor_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_rcg *rcg = to_clk_rcg(hw);
+ const struct freq_tbl *f;
+
+ f = qcom_find_freq_floor(rcg->freq_tbl, rate);
+ if (!f)
+ return -EINVAL;
+
+ return __clk_rcg_set_rate(rcg, f);
+}
+
static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
@@ -816,6 +829,17 @@ const struct clk_ops clk_rcg_ops = {
};
EXPORT_SYMBOL_GPL(clk_rcg_ops);
+const struct clk_ops clk_rcg_floor_ops = {
+ .enable = clk_enable_regmap,
+ .disable = clk_disable_regmap,
+ .get_parent = clk_rcg_get_parent,
+ .set_parent = clk_rcg_set_parent,
+ .recalc_rate = clk_rcg_recalc_rate,
+ .determine_rate = clk_rcg_determine_rate,
+ .set_rate = clk_rcg_set_floor_rate,
+};
+EXPORT_SYMBOL_GPL(clk_rcg_floor_ops);
+
const struct clk_ops clk_rcg_bypass_ops = {
.enable = clk_enable_regmap,
.disable = clk_disable_regmap,
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index 99efcc7f8d88..00cea508d49e 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -86,6 +86,7 @@ struct clk_rcg {
};
extern const struct clk_ops clk_rcg_ops;
+extern const struct clk_ops clk_rcg_floor_ops;
extern const struct clk_ops clk_rcg_bypass_ops;
extern const struct clk_ops clk_rcg_bypass2_ops;
extern const struct clk_ops clk_rcg_pixel_ops;
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v5 09/15] clk: qcom: clk-rcg: add clk_rcg_floor_ops ops
2022-02-24 16:48 ` [PATCH v5 09/15] clk: qcom: clk-rcg: add clk_rcg_floor_ops ops Ansuel Smith
@ 2022-02-24 22:11 ` Stephen Boyd
0 siblings, 0 replies; 38+ messages in thread
From: Stephen Boyd @ 2022-02-24 22:11 UTC (permalink / raw)
To: Andy Gross, Ansuel Smith, Bjorn Andersson, Michael Turquette,
Philipp Zabel, Rob Herring, Taniya Das, devicetree,
linux-arm-msm, linux-clk, linux-kernel
Quoting Ansuel Smith (2022-02-24 08:48:25)
> Add clk_rcg_floor_ops for clock that can't provide a stable freq and
> require to use a floor freq to provide the requested frequency.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v5 10/15] clk: qcom: gcc-ipq806x: add additional freq for sdc table
2022-02-24 16:48 [PATCH v5 00/15] Multiple addition and improvement to ipq8064 gcc Ansuel Smith
` (8 preceding siblings ...)
2022-02-24 16:48 ` [PATCH v5 09/15] clk: qcom: clk-rcg: add clk_rcg_floor_ops ops Ansuel Smith
@ 2022-02-24 16:48 ` Ansuel Smith
2022-02-24 22:11 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 11/15] dt-bindings: clock: add ipq8064 ce5 clk define Ansuel Smith
` (4 subsequent siblings)
14 siblings, 1 reply; 38+ messages in thread
From: Ansuel Smith @ 2022-02-24 16:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Philipp Zabel, Taniya Das, Ansuel Smith,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Add additional freq supported for the sdc table. The ops are changed to
the floor_ops to handle a freq request of 52kHz where we need to provide
a freq of 51.2kHz instead for stability reason.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/clk/qcom/gcc-ipq806x.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 49a4eae4161f..6eb03b72eed4 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -1299,6 +1299,7 @@ static const struct freq_tbl clk_tbl_sdc[] = {
{ 20210000, P_PLL8, 1, 1, 19 },
{ 24000000, P_PLL8, 4, 1, 4 },
{ 48000000, P_PLL8, 4, 1, 2 },
+ { 51200000, P_PLL8, 1, 2, 15 },
{ 64000000, P_PLL8, 3, 1, 2 },
{ 96000000, P_PLL8, 4, 0, 0 },
{ 192000000, P_PLL8, 2, 0, 0 },
@@ -1332,7 +1333,7 @@ static struct clk_rcg sdc1_src = {
.name = "sdc1_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
+ .ops = &clk_rcg_floor_ops,
},
}
};
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v5 10/15] clk: qcom: gcc-ipq806x: add additional freq for sdc table
2022-02-24 16:48 ` [PATCH v5 10/15] clk: qcom: gcc-ipq806x: add additional freq for sdc table Ansuel Smith
@ 2022-02-24 22:11 ` Stephen Boyd
0 siblings, 0 replies; 38+ messages in thread
From: Stephen Boyd @ 2022-02-24 22:11 UTC (permalink / raw)
To: Andy Gross, Ansuel Smith, Bjorn Andersson, Michael Turquette,
Philipp Zabel, Rob Herring, Taniya Das, devicetree,
linux-arm-msm, linux-clk, linux-kernel
Quoting Ansuel Smith (2022-02-24 08:48:26)
> Add additional freq supported for the sdc table. The ops are changed to
> the floor_ops to handle a freq request of 52kHz where we need to provide
> a freq of 51.2kHz instead for stability reason.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v5 11/15] dt-bindings: clock: add ipq8064 ce5 clk define
2022-02-24 16:48 [PATCH v5 00/15] Multiple addition and improvement to ipq8064 gcc Ansuel Smith
` (9 preceding siblings ...)
2022-02-24 16:48 ` [PATCH v5 10/15] clk: qcom: gcc-ipq806x: add additional freq for sdc table Ansuel Smith
@ 2022-02-24 16:48 ` Ansuel Smith
2022-02-24 19:09 ` Rob Herring
2022-02-24 22:12 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 12/15] clk: qcom: gcc-ipq806x: add CryptoEngine clocks Ansuel Smith
` (3 subsequent siblings)
14 siblings, 2 replies; 38+ messages in thread
From: Ansuel Smith @ 2022-02-24 16:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Philipp Zabel, Taniya Das, Ansuel Smith,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
index 7deec14a6dee..02262d2ac899 100644
--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
@@ -240,7 +240,7 @@
#define PLL14 232
#define PLL14_VOTE 233
#define PLL18 234
-#define CE5_SRC 235
+#define CE5_A_CLK 235
#define CE5_H_CLK 236
#define CE5_CORE_CLK 237
#define CE3_SLEEP_CLK 238
@@ -283,5 +283,8 @@
#define EBI2_AON_CLK 281
#define NSSTCM_CLK_SRC 282
#define NSSTCM_CLK 283
+#define CE5_A_CLK_SRC 285
+#define CE5_H_CLK_SRC 286
+#define CE5_CORE_CLK_SRC 287
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v5 11/15] dt-bindings: clock: add ipq8064 ce5 clk define
2022-02-24 16:48 ` [PATCH v5 11/15] dt-bindings: clock: add ipq8064 ce5 clk define Ansuel Smith
@ 2022-02-24 19:09 ` Rob Herring
2022-02-24 22:12 ` Stephen Boyd
1 sibling, 0 replies; 38+ messages in thread
From: Rob Herring @ 2022-02-24 19:09 UTC (permalink / raw)
To: Ansuel Smith
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, linux-clk,
Rob Herring, linux-arm-msm, devicetree, Bjorn Andersson,
Taniya Das, linux-kernel, Andy Gross
On Thu, 24 Feb 2022 17:48:27 +0100, Ansuel Smith wrote:
> Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
> include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 11/15] dt-bindings: clock: add ipq8064 ce5 clk define
2022-02-24 16:48 ` [PATCH v5 11/15] dt-bindings: clock: add ipq8064 ce5 clk define Ansuel Smith
2022-02-24 19:09 ` Rob Herring
@ 2022-02-24 22:12 ` Stephen Boyd
1 sibling, 0 replies; 38+ messages in thread
From: Stephen Boyd @ 2022-02-24 22:12 UTC (permalink / raw)
To: Andy Gross, Ansuel Smith, Bjorn Andersson, Michael Turquette,
Philipp Zabel, Rob Herring, Taniya Das, devicetree,
linux-arm-msm, linux-clk, linux-kernel
Quoting Ansuel Smith (2022-02-24 08:48:27)
> Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver.
Would be worth noting that changing the define is OK because it isn't
used.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v5 12/15] clk: qcom: gcc-ipq806x: add CryptoEngine clocks
2022-02-24 16:48 [PATCH v5 00/15] Multiple addition and improvement to ipq8064 gcc Ansuel Smith
` (10 preceding siblings ...)
2022-02-24 16:48 ` [PATCH v5 11/15] dt-bindings: clock: add ipq8064 ce5 clk define Ansuel Smith
@ 2022-02-24 16:48 ` Ansuel Smith
2022-02-24 22:13 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 13/15] dt-bindings: reset: add ipq8064 ce5 resets Ansuel Smith
` (2 subsequent siblings)
14 siblings, 1 reply; 38+ messages in thread
From: Ansuel Smith @ 2022-02-24 16:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Philipp Zabel, Taniya Das, Ansuel Smith,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Add missing CryptoEngine clocks and pll11 required clock.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/clk/qcom/gcc-ipq806x.c | 244 +++++++++++++++++++++++++++++++++
1 file changed, 244 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 6eb03b72eed4..4c095f42eea0 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -257,6 +257,24 @@ static struct clk_pll pll18 = {
},
};
+static struct clk_pll pll11 = {
+ .l_reg = 0x3184,
+ .m_reg = 0x3188,
+ .n_reg = 0x318c,
+ .config_reg = 0x3194,
+ .mode_reg = 0x3180,
+ .status_reg = 0x3198,
+ .status_bit = 16,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pll11",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "pxo",
+ },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
enum {
P_PXO,
P_PLL8,
@@ -265,6 +283,7 @@ enum {
P_CXO,
P_PLL14,
P_PLL18,
+ P_PLL11,
};
static const struct parent_map gcc_pxo_pll8_map[] = {
@@ -338,6 +357,44 @@ static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = {
{ .hw = &pll18.clkr.hw },
};
+static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {
+ { P_PXO, 0 },
+ { P_PLL8, 4 },
+ { P_PLL0, 2 },
+ { P_PLL14, 5 },
+ { P_PLL18, 1 },
+ { P_PLL11, 3 },
+};
+
+static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {
+ { .fw_name = "pxo" },
+ { .hw = &pll8_vote.hw },
+ { .hw = &pll0_vote.hw },
+ { .hw = &pll14.clkr.hw },
+ { .hw = &pll18.clkr.hw },
+ { .hw = &pll11.clkr.hw },
+
+};
+
+static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {
+ { P_PXO, 0 },
+ { P_PLL3, 6 },
+ { P_PLL0, 2 },
+ { P_PLL14, 5 },
+ { P_PLL18, 1 },
+ { P_PLL11, 3 },
+};
+
+static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
+ { .fw_name = "pxo" },
+ { .hw = &pll3.clkr.hw },
+ { .hw = &pll0_vote.hw },
+ { .hw = &pll14.clkr.hw },
+ { .hw = &pll18.clkr.hw },
+ { .hw = &pll11.clkr.hw },
+
+};
+
static struct freq_tbl clk_tbl_gsbi_uart[] = {
{ 1843200, P_PLL8, 2, 6, 625 },
{ 3686400, P_PLL8, 2, 12, 625 },
@@ -2831,6 +2888,186 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
},
};
+static const struct freq_tbl clk_tbl_ce5_core[] = {
+ { 150000000, P_PLL3, 8, 1, 1 },
+ { 213200000, P_PLL11, 5, 1, 1 },
+ { }
+};
+
+static struct clk_dyn_rcg ce5_core_src = {
+ .ns_reg[0] = 0x36C4,
+ .ns_reg[1] = 0x36C8,
+ .bank_reg = 0x36C0,
+ .s[0] = {
+ .src_sel_shift = 0,
+ .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
+ },
+ .s[1] = {
+ .src_sel_shift = 0,
+ .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
+ },
+ .p[0] = {
+ .pre_div_shift = 3,
+ .pre_div_width = 4,
+ },
+ .p[1] = {
+ .pre_div_shift = 3,
+ .pre_div_width = 4,
+ },
+ .mux_sel_bit = 0,
+ .freq_tbl = clk_tbl_ce5_core,
+ .clkr = {
+ .enable_reg = 0x36C0,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "ce5_core_src",
+ .parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11),
+ .ops = &clk_dyn_rcg_ops,
+ },
+ },
+};
+
+static struct clk_branch ce5_core_clk = {
+ .halt_reg = 0x2FDC,
+ .halt_bit = 5,
+ .hwcg_reg = 0x36CC,
+ .hwcg_bit = 6,
+ .clkr = {
+ .enable_reg = 0x36CC,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "ce5_core_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &ce5_core_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl clk_tbl_ce5_a_clk[] = {
+ { 160000000, P_PLL0, 5, 1, 1 },
+ { 213200000, P_PLL11, 5, 1, 1 },
+ { }
+};
+
+static struct clk_dyn_rcg ce5_a_clk_src = {
+ .ns_reg[0] = 0x3d84,
+ .ns_reg[1] = 0x3d88,
+ .bank_reg = 0x3d80,
+ .s[0] = {
+ .src_sel_shift = 0,
+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
+ },
+ .s[1] = {
+ .src_sel_shift = 0,
+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
+ },
+ .p[0] = {
+ .pre_div_shift = 3,
+ .pre_div_width = 4,
+ },
+ .p[1] = {
+ .pre_div_shift = 3,
+ .pre_div_width = 4,
+ },
+ .mux_sel_bit = 0,
+ .freq_tbl = clk_tbl_ce5_a_clk,
+ .clkr = {
+ .enable_reg = 0x3d80,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "ce5_a_clk_src",
+ .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
+ .ops = &clk_dyn_rcg_ops,
+ },
+ },
+};
+
+static struct clk_branch ce5_a_clk = {
+ .halt_reg = 0x3c20,
+ .halt_bit = 12,
+ .hwcg_reg = 0x3d8c,
+ .hwcg_bit = 6,
+ .clkr = {
+ .enable_reg = 0x3d8c,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "ce5_a_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &ce5_a_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl clk_tbl_ce5_h_clk[] = {
+ { 160000000, P_PLL0, 5, 1, 1 },
+ { 213200000, P_PLL11, 5, 1, 1 },
+ { }
+};
+
+static struct clk_dyn_rcg ce5_h_clk_src = {
+ .ns_reg[0] = 0x3c64,
+ .ns_reg[1] = 0x3c68,
+ .bank_reg = 0x3c60,
+ .s[0] = {
+ .src_sel_shift = 0,
+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
+ },
+ .s[1] = {
+ .src_sel_shift = 0,
+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
+ },
+ .p[0] = {
+ .pre_div_shift = 3,
+ .pre_div_width = 4,
+ },
+ .p[1] = {
+ .pre_div_shift = 3,
+ .pre_div_width = 4,
+ },
+ .mux_sel_bit = 0,
+ .freq_tbl = clk_tbl_ce5_h_clk,
+ .clkr = {
+ .enable_reg = 0x3c60,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "ce5_h_clk_src",
+ .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
+ .ops = &clk_dyn_rcg_ops,
+ },
+ },
+};
+
+static struct clk_branch ce5_h_clk = {
+ .halt_reg = 0x3c20,
+ .halt_bit = 11,
+ .hwcg_reg = 0x3c6c,
+ .hwcg_bit = 6,
+ .clkr = {
+ .enable_reg = 0x3c6c,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "ce5_h_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &ce5_h_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
static struct clk_regmap *gcc_ipq806x_clks[] = {
[PLL0] = &pll0.clkr,
[PLL0_VOTE] = &pll0_vote,
@@ -2838,6 +3075,7 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
[PLL4_VOTE] = &pll4_vote,
[PLL8] = &pll8.clkr,
[PLL8_VOTE] = &pll8_vote,
+ [PLL11] = &pll11.clkr,
[PLL14] = &pll14.clkr,
[PLL14_VOTE] = &pll14_vote,
[PLL18] = &pll18.clkr,
@@ -2952,6 +3190,12 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
[PLL9] = &hfpll0.clkr,
[PLL10] = &hfpll1.clkr,
[PLL12] = &hfpll_l2.clkr,
+ [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,
+ [CE5_A_CLK] = &ce5_a_clk.clkr,
+ [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,
+ [CE5_H_CLK] = &ce5_h_clk.clkr,
+ [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,
+ [CE5_CORE_CLK] = &ce5_core_clk.clkr,
};
static const struct qcom_reset_map gcc_ipq806x_resets[] = {
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v5 12/15] clk: qcom: gcc-ipq806x: add CryptoEngine clocks
2022-02-24 16:48 ` [PATCH v5 12/15] clk: qcom: gcc-ipq806x: add CryptoEngine clocks Ansuel Smith
@ 2022-02-24 22:13 ` Stephen Boyd
0 siblings, 0 replies; 38+ messages in thread
From: Stephen Boyd @ 2022-02-24 22:13 UTC (permalink / raw)
To: Andy Gross, Ansuel Smith, Bjorn Andersson, Michael Turquette,
Philipp Zabel, Rob Herring, Taniya Das, devicetree,
linux-arm-msm, linux-clk, linux-kernel
Quoting Ansuel Smith (2022-02-24 08:48:28)
> Add missing CryptoEngine clocks and pll11 required clock.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v5 13/15] dt-bindings: reset: add ipq8064 ce5 resets
2022-02-24 16:48 [PATCH v5 00/15] Multiple addition and improvement to ipq8064 gcc Ansuel Smith
` (11 preceding siblings ...)
2022-02-24 16:48 ` [PATCH v5 12/15] clk: qcom: gcc-ipq806x: add CryptoEngine clocks Ansuel Smith
@ 2022-02-24 16:48 ` Ansuel Smith
2022-02-24 19:10 ` Rob Herring
2022-02-24 22:13 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 14/15] clk: qcom: gcc-ipq806x: add CryptoEngine resets Ansuel Smith
2022-02-24 16:48 ` [PATCH v5 15/15] ARM: dts: qcom: add syscon and cxo/pxo clock to gcc node for ipq8064 Ansuel Smith
14 siblings, 2 replies; 38+ messages in thread
From: Ansuel Smith @ 2022-02-24 16:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Philipp Zabel, Taniya Das, Ansuel Smith,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Add ipq8064 ce5 resets needed for CryptoEngine gcc driver.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
---
include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
index 26b6f9200620..020c9cf18751 100644
--- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h
+++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
@@ -163,5 +163,10 @@
#define NSS_CAL_PRBS_RST_N_RESET 154
#define NSS_LCKDT_RST_N_RESET 155
#define NSS_SRDS_N_RESET 156
+#define CRYPTO_ENG1_RESET 157
+#define CRYPTO_ENG2_RESET 158
+#define CRYPTO_ENG3_RESET 159
+#define CRYPTO_ENG4_RESET 160
+#define CRYPTO_AHB_RESET 161
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v5 13/15] dt-bindings: reset: add ipq8064 ce5 resets
2022-02-24 16:48 ` [PATCH v5 13/15] dt-bindings: reset: add ipq8064 ce5 resets Ansuel Smith
@ 2022-02-24 19:10 ` Rob Herring
2022-02-24 22:13 ` Stephen Boyd
1 sibling, 0 replies; 38+ messages in thread
From: Rob Herring @ 2022-02-24 19:10 UTC (permalink / raw)
To: Ansuel Smith
Cc: Rob Herring, linux-clk, linux-kernel, Bjorn Andersson,
Taniya Das, devicetree, Stephen Boyd, Andy Gross, linux-arm-msm,
Philipp Zabel, Michael Turquette
On Thu, 24 Feb 2022 17:48:29 +0100, Ansuel Smith wrote:
> Add ipq8064 ce5 resets needed for CryptoEngine gcc driver.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
> ---
> include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v5 13/15] dt-bindings: reset: add ipq8064 ce5 resets
2022-02-24 16:48 ` [PATCH v5 13/15] dt-bindings: reset: add ipq8064 ce5 resets Ansuel Smith
2022-02-24 19:10 ` Rob Herring
@ 2022-02-24 22:13 ` Stephen Boyd
1 sibling, 0 replies; 38+ messages in thread
From: Stephen Boyd @ 2022-02-24 22:13 UTC (permalink / raw)
To: Andy Gross, Ansuel Smith, Bjorn Andersson, Michael Turquette,
Philipp Zabel, Rob Herring, Taniya Das, devicetree,
linux-arm-msm, linux-clk, linux-kernel
Quoting Ansuel Smith (2022-02-24 08:48:29)
> Add ipq8064 ce5 resets needed for CryptoEngine gcc driver.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v5 14/15] clk: qcom: gcc-ipq806x: add CryptoEngine resets
2022-02-24 16:48 [PATCH v5 00/15] Multiple addition and improvement to ipq8064 gcc Ansuel Smith
` (12 preceding siblings ...)
2022-02-24 16:48 ` [PATCH v5 13/15] dt-bindings: reset: add ipq8064 ce5 resets Ansuel Smith
@ 2022-02-24 16:48 ` Ansuel Smith
2022-02-24 22:13 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 15/15] ARM: dts: qcom: add syscon and cxo/pxo clock to gcc node for ipq8064 Ansuel Smith
14 siblings, 1 reply; 38+ messages in thread
From: Ansuel Smith @ 2022-02-24 16:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Philipp Zabel, Taniya Das, Ansuel Smith,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Add missing CryptoEngine resets.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/clk/qcom/gcc-ipq806x.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 4c095f42eea0..8ec643164443 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -3327,6 +3327,11 @@ static const struct qcom_reset_map gcc_ipq806x_resets[] = {
[GMAC_CORE3_RESET] = { 0x3cfc, 0 },
[GMAC_CORE4_RESET] = { 0x3d1c, 0 },
[GMAC_AHB_RESET] = { 0x3e24, 0 },
+ [CRYPTO_ENG1_RESET] = { 0x3e00, 0},
+ [CRYPTO_ENG2_RESET] = { 0x3e04, 0},
+ [CRYPTO_ENG3_RESET] = { 0x3e08, 0},
+ [CRYPTO_ENG4_RESET] = { 0x3e0c, 0},
+ [CRYPTO_AHB_RESET] = { 0x3e10, 0},
[NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
[NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
[NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v5 14/15] clk: qcom: gcc-ipq806x: add CryptoEngine resets
2022-02-24 16:48 ` [PATCH v5 14/15] clk: qcom: gcc-ipq806x: add CryptoEngine resets Ansuel Smith
@ 2022-02-24 22:13 ` Stephen Boyd
0 siblings, 0 replies; 38+ messages in thread
From: Stephen Boyd @ 2022-02-24 22:13 UTC (permalink / raw)
To: Andy Gross, Ansuel Smith, Bjorn Andersson, Michael Turquette,
Philipp Zabel, Rob Herring, Taniya Das, devicetree,
linux-arm-msm, linux-clk, linux-kernel
Quoting Ansuel Smith (2022-02-24 08:48:30)
> Add missing CryptoEngine resets.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v5 15/15] ARM: dts: qcom: add syscon and cxo/pxo clock to gcc node for ipq8064
2022-02-24 16:48 [PATCH v5 00/15] Multiple addition and improvement to ipq8064 gcc Ansuel Smith
` (13 preceding siblings ...)
2022-02-24 16:48 ` [PATCH v5 14/15] clk: qcom: gcc-ipq806x: add CryptoEngine resets Ansuel Smith
@ 2022-02-24 16:48 ` Ansuel Smith
2022-02-24 22:14 ` Stephen Boyd
14 siblings, 1 reply; 38+ messages in thread
From: Ansuel Smith @ 2022-02-24 16:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Philipp Zabel, Taniya Das, Ansuel Smith,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Add syscon compatible required for tsens driver to correctly probe driver
and access the reg. Also add cxo and pxo tag and declare them as gcc clock
now requires them for the ipq8064 gcc driver that has now been modernized.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 11481313bdb6..5524a68cf3d1 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -298,13 +298,13 @@ smem: smem@41000000 {
};
clocks {
- cxo_board {
+ cxo_board: cxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
- pxo_board {
+ pxo_board: pxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
@@ -736,7 +736,9 @@ tsens_calib_backup: calib_backup@410 {
};
gcc: clock-controller@900000 {
- compatible = "qcom,gcc-ipq8064";
+ compatible = "qcom,gcc-ipq8064", "syscon";
+ clocks = <&pxo_board>, <&cxo_board>;
+ clock-names = "pxo", "cxo";
reg = <0x00900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
--
2.34.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v5 15/15] ARM: dts: qcom: add syscon and cxo/pxo clock to gcc node for ipq8064
2022-02-24 16:48 ` [PATCH v5 15/15] ARM: dts: qcom: add syscon and cxo/pxo clock to gcc node for ipq8064 Ansuel Smith
@ 2022-02-24 22:14 ` Stephen Boyd
0 siblings, 0 replies; 38+ messages in thread
From: Stephen Boyd @ 2022-02-24 22:14 UTC (permalink / raw)
To: Andy Gross, Ansuel Smith, Bjorn Andersson, Michael Turquette,
Philipp Zabel, Rob Herring, Taniya Das, devicetree,
linux-arm-msm, linux-clk, linux-kernel
Quoting Ansuel Smith (2022-02-24 08:48:31)
> Add syscon compatible required for tsens driver to correctly probe driver
> and access the reg. Also add cxo and pxo tag and declare them as gcc clock
> now requires them for the ipq8064 gcc driver that has now been modernized.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 38+ messages in thread