From: Andrew Lunn <andrew@lunn.ch>
To: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Cc: Chris Packham <Chris.Packham@alliedtelesis.co.nz>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"linus.walleij@linaro.org" <linus.walleij@linaro.org>,
"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
"gregory.clement@bootlin.com" <gregory.clement@bootlin.com>,
"sebastian.hesselbarth@gmail.com"
<sebastian.hesselbarth@gmail.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v2 1/8] dt-bindings: pinctrl: mvebu: Document bindings for AC5
Date: Thu, 17 Mar 2022 15:14:32 +0100 [thread overview]
Message-ID: <YjNCSENOP8EyWArw@lunn.ch> (raw)
In-Reply-To: <4b1f4772-35f9-3e21-6429-b64c7427144a@canonical.com>
> What do you mean "driver fails to load"? You control the driver, don't
> you?
It is a thin wrapper around the mvebu driver, which does all the real
work. So no, Chris does not really control what the core of the driver
does.
The existing binding documentation says:
* Marvell Armada 37xx SoC pin and gpio controller
Each Armada 37xx SoC come with two pin and gpio controller one for
the south bridge and the other for the north bridge.
Inside this set of register the gpio latch allows exposing some
configuration of the SoC and especially the clock frequency of the
xtal. Hence, this node is a represent as syscon allowing sharing
the register between multiple hardware block.
So the syscon is there to allow the clock driver to share the register
space.
Andrew
next prev parent reply other threads:[~2022-03-17 14:14 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-14 21:31 [PATCH v2 0/8] arm64: mvebu: Support for Marvell 98DX2530 (and variants) Chris Packham
2022-03-14 21:31 ` [PATCH v2 1/8] dt-bindings: pinctrl: mvebu: Document bindings for AC5 Chris Packham
2022-03-15 0:07 ` Andrew Lunn
2022-03-15 0:22 ` Chris Packham
2022-03-15 0:27 ` Andrew Lunn
2022-03-23 18:34 ` Rob Herring
2022-03-15 10:46 ` Krzysztof Kozlowski
2022-03-15 21:12 ` Chris Packham
2022-03-16 8:16 ` Krzysztof Kozlowski
2022-03-16 20:21 ` Chris Packham
2022-03-17 7:26 ` Krzysztof Kozlowski
2022-03-17 14:14 ` Andrew Lunn [this message]
2022-03-17 15:16 ` Krzysztof Kozlowski
2022-03-14 21:31 ` [PATCH v2 2/8] dt-bindings: net: mvneta: Add marvell,armada-ac5-neta Chris Packham
2022-03-15 0:10 ` Andrew Lunn
2022-03-14 21:31 ` [PATCH v2 3/8] dt-bindings: mmc: xenon: add AC5 compatible string Chris Packham
2022-03-15 0:14 ` Andrew Lunn
2022-03-14 21:31 ` [PATCH v2 4/8] pinctrl: mvebu: pinctrl driver for 98DX2530 SoC Chris Packham
2022-03-15 0:16 ` Andrew Lunn
2022-03-15 10:49 ` Krzysztof Kozlowski
2022-03-15 14:33 ` Andrew Lunn
2022-03-15 14:39 ` Krzysztof Kozlowski
2022-03-14 21:31 ` [PATCH v2 5/8] net: mvneta: Add support for 98DX2530 Ethernet port Chris Packham
2022-03-15 0:12 ` Andrew Lunn
2022-03-15 0:27 ` Chris Packham
2022-03-14 21:31 ` [PATCH v2 6/8] mmc: xenon: add AC5 compatible string Chris Packham
2022-03-15 0:14 ` Andrew Lunn
2022-03-14 21:31 ` [PATCH v2 7/8] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board Chris Packham
2022-03-15 0:24 ` Andrew Lunn
2022-03-15 2:11 ` Chris Packham
2022-03-15 14:28 ` Andrew Lunn
2022-03-16 11:49 ` Marc Zyngier
2022-03-14 21:31 ` [PATCH v2 8/8] arm64: marvell: enable the 98DX2530 pinctrl driver Chris Packham
2022-03-15 0:25 ` Andrew Lunn
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