qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Claudio Fontana <cfontana@suse.de>
To: "Richard Henderson" <richard.henderson@linaro.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>,
	"Alex Bennée" <alex.bennee@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	Roman Bolshakov <r.bolshakov@yadro.com>,
	qemu-devel@nongnu.org, Eduardo Habkost <ehabkost@redhat.com>
Subject: Re: [RFC v11 45/55] target/arm: cpu-sve: new module
Date: Thu, 25 Mar 2021 19:48:20 +0100	[thread overview]
Message-ID: <143fde2e-6c88-8fef-10ff-523c574e0db4@suse.de> (raw)
In-Reply-To: <724c86f8-2275-833b-d4e1-4729c0ca2e80@linaro.org>

On 3/25/21 7:40 PM, Richard Henderson wrote:
> On 3/23/21 9:46 AM, Claudio Fontana wrote:
>> extract the SVE-related cpu object properties and functions,
>> and move them to a separate module.
>>
>> Disentangle SVE from pauth that is a separate, TCG-only feature.
>>
>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>> ---
>>   target/arm/cpu-sve.h     |  40 +++++
>>   target/arm/cpu.h         |  22 +--
>>   target/arm/cpu-sve.c     | 360 +++++++++++++++++++++++++++++++++++++++
>>   target/arm/cpu.c         |   5 +-
>>   target/arm/cpu64.c       | 333 +-----------------------------------
>>   target/arm/kvm/kvm-cpu.c |   2 +-
>>   target/arm/meson.build   |   1 +
>>   7 files changed, 417 insertions(+), 346 deletions(-)
>>   create mode 100644 target/arm/cpu-sve.h
>>   create mode 100644 target/arm/cpu-sve.c
>>
>> diff --git a/target/arm/cpu-sve.h b/target/arm/cpu-sve.h
>> new file mode 100644
>> index 0000000000..b1be575265
>> --- /dev/null
>> +++ b/target/arm/cpu-sve.h
>> @@ -0,0 +1,40 @@
>> +/*
>> + * QEMU AArch64 CPU SVE Extensions for TARGET_AARCH64
>> + *
>> + * Copyright (c) 2013 Linaro Ltd
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License
>> + * as published by the Free Software Foundation; either version 2
>> + * of the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, see
>> + * <http://www.gnu.org/licenses/gpl-2.0.html>
>> + */
>> +
>> +#ifndef CPU_SVE_H
>> +#define CPU_SVE_H
>> +
>> +/* note: SVE is an AARCH64-only option, only include this for TARGET_AARCH64 */
>> +
>> +/* called by arm_cpu_finalize_features in realizefn */
>> +void cpu_sve_finalize_features(ARMCPU *cpu, Error **errp);
>> +
>> +/* add the CPU SVE properties */
>> +void cpu_sve_add_props(Object *obj);
>> +
>> +/* add the CPU SVE properties specific to the "MAX" CPU */
>> +void cpu_sve_add_props_max(Object *obj);
>> +
>> +/* In AArch32 mode, predicate registers do not exist at all.  */
>> +typedef struct ARMPredicateReg {
>> +    uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
>> +} ARMPredicateReg;
> 
> I don't agree with moving this out of cpu.h, next to the rest of the vector 
> definitions.
> 
> I agree that we should be using more files, but if we're going to have an 
> cpu-sve.c, why did some of the sve functions go into cpu-common.c?

maybe cpu-sve-props.c would be a better name, it really contains only cpu sve properties code.

> 
> I don't agree with moving functions and renaming them simultaneously.  I'm not 
> even sure why you're renaming them, or why you've suddenly chosen "cpu_sve_*" 
> as the prefix to use.
> 
> 
> r~
> 

I think the idea was trying to create a cpu_sve module handling everything related to sve,
and consistently using the name of the module as the prefix.

It might be too early to attempt that anyway; as you noted, there is other SVE-related functionality all over the place,
so better to revisit this.

I'd suggest renaming this to cpu_sve_props, and moving everything not props related out of it.

Thanks,

Claudio





  reply	other threads:[~2021-03-25 18:51 UTC|newest]

Thread overview: 110+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-23 15:16 [RFC v11 00/55] arm cleanup experiment for kvm-only build Claudio Fontana
2021-03-23 15:16 ` [RFC v11 01/55] target/arm: move translate modules to tcg/ Claudio Fontana
2021-03-23 15:16 ` [RFC v11 02/55] target/arm: move helpers " Claudio Fontana
2021-03-23 15:16 ` [RFC v11 03/55] arm: tcg: only build under CONFIG_TCG Claudio Fontana
2021-03-23 15:16 ` [RFC v11 04/55] target/arm: tcg: add sysemu and user subdirs Claudio Fontana
2021-03-24 18:06   ` Richard Henderson
2021-03-24 18:18   ` Richard Henderson
2021-03-24 18:21     ` Claudio Fontana
2021-03-23 15:16 ` [RFC v11 05/55] target/arm: tcg: split mte_helper user-only and sysemu code Claudio Fontana
2021-03-24 18:15   ` Richard Henderson
2021-03-23 15:17 ` [RFC v11 06/55] target/arm: tcg: move sysemu-only parts of debug_helper Claudio Fontana
2021-03-24 18:19   ` Richard Henderson
2021-03-23 15:17 ` [RFC v11 07/55] target/arm: tcg: split tlb_helper user-only and sysemu-only parts Claudio Fontana
2021-03-24 18:20   ` Richard Henderson
2021-03-23 15:45 ` [RFC v11 08/55] target/arm: tcg: split m_helper " Claudio Fontana
2021-03-24 18:21   ` Richard Henderson
2021-03-23 15:45 ` [RFC v11 09/55] target/arm: only build psci for TCG Claudio Fontana
2021-03-23 15:45 ` [RFC v11 10/55] target/arm: split off cpu-sysemu.c Claudio Fontana
2021-03-24 18:24   ` Richard Henderson
2021-03-23 15:45 ` [RFC v11 11/55] target/arm: move physical address translation to cpu-mmu Claudio Fontana
2021-03-24 18:31   ` Richard Henderson
2021-03-23 15:45 ` [RFC v11 12/55] target/arm: cpu-mmu: fix comment style Claudio Fontana
2021-03-24 18:32   ` Richard Henderson
2021-03-23 15:45 ` [RFC v11 13/55] target/arm: split cpregs from tcg/helper.c Claudio Fontana
2021-03-24 18:40   ` Richard Henderson
2021-03-23 15:45 ` [RFC v11 14/55] target/arm: cpregs: fix style (mostly just comments) Claudio Fontana
2021-03-24 18:40   ` Richard Henderson
2021-03-23 15:45 ` [RFC v11 15/55] target/arm: move cpu definitions to common cpu module Claudio Fontana
2021-03-24 18:42   ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 16/55] target/arm: only perform TCG cpu and machine inits if TCG enabled Claudio Fontana
2021-03-24 18:44   ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 17/55] target/arm: kvm: add stubs for some helpers Claudio Fontana
2021-03-24 18:46   ` Richard Henderson
2021-03-24 18:54   ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 18/55] target/arm: move cpsr_read, cpsr_write to cpu_common Claudio Fontana
2021-03-24 18:47   ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 19/55] target/arm: add temporary stub for arm_rebuild_hflags Claudio Fontana
2021-03-24 18:56   ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 20/55] target/arm: split vfp state setting from tcg helpers Claudio Fontana
2021-03-24 20:29   ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 21/55] target/arm: move arm_mmu_idx* to cpu-mmu Claudio Fontana
2021-03-24 20:31   ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 22/55] target/arm: move sve_zcr_len_for_el to common_cpu Claudio Fontana
2021-03-24 22:03   ` Richard Henderson
2021-03-25 21:44     ` Claudio Fontana
2021-03-23 15:46 ` [RFC v11 23/55] target/arm: move arm_sctlr away from tcg helpers Claudio Fontana
2021-03-24 22:07   ` Richard Henderson
2021-03-25 14:26     ` Claudio Fontana
2021-03-23 15:46 ` [RFC v11 24/55] target/arm: move arm_cpu_list to common_cpu Claudio Fontana
2021-03-23 15:46 ` [RFC v11 25/55] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code Claudio Fontana
2021-03-24 22:11   ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 26/55] target/arm: split a15 cpu model and 32bit class functions to cpu32.c Claudio Fontana
2021-03-24 22:17   ` Richard Henderson
2021-03-25 14:30     ` Claudio Fontana
2021-03-23 15:46 ` [RFC v11 27/55] target/arm: move sve_exception_el out of TCG helpers Claudio Fontana
2021-03-24 22:24   ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 28/55] target/arm: refactor exception and cpu code Claudio Fontana
2021-03-24 22:29   ` Richard Henderson
2021-03-25 11:59     ` Claudio Fontana
2021-03-25 18:43       ` Richard Henderson
2021-03-25 18:50         ` Claudio Fontana
2021-03-23 15:46 ` [RFC v11 29/55] target/arm: cpu: fix style Claudio Fontana
2021-03-24 22:29   ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 30/55] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Claudio Fontana
2021-03-23 22:50   ` Alex Bennée
2021-03-24  8:29     ` Claudio Fontana
2021-03-24 11:41       ` Alex Bennée
2021-03-24 11:48         ` Alex Bennée
2021-03-24 14:34           ` Claudio Fontana
2021-03-24 16:30             ` Alex Bennée
2021-03-24 22:30   ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 31/55] target/arm: remove kvm include file for PSCI and arm-powerctl Claudio Fontana
2021-03-24 22:30   ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 32/55] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/ Claudio Fontana
2021-03-24 22:35   ` Richard Henderson
2021-03-25 15:14     ` Claudio Fontana
2021-03-23 15:46 ` [RFC v11 33/55] target/arm: cleanup cpu includes Claudio Fontana
2021-03-23 15:46 ` [RFC v11 34/55] target/arm: remove broad "else" statements when checking accels Claudio Fontana
2021-03-24 22:37   ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 35/55] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM Claudio Fontana
2021-03-23 15:46 ` [RFC v11 36/55] tests: restrict TCG-only arm-cpu-features tests to TCG builds Claudio Fontana
2021-03-23 15:46 ` [RFC v11 37/55] tests: do not run test-hmp on all machines for ARM KVM-only Claudio Fontana
2021-03-23 15:46 ` [RFC v11 38/55] tests: device-introspect-test: cope with ARM TCG-only devices Claudio Fontana
2021-03-23 15:46 ` [RFC v11 39/55] tests: do not run qom-test on all machines for ARM KVM-only Claudio Fontana
2021-03-23 15:46 ` [RFC v11 40/55] Revert "target/arm: Restrict v8M IDAU to TCG" Claudio Fontana
2021-03-23 15:46 ` [RFC v11 41/55] target/arm: create kvm cpu accel class Claudio Fontana
2021-03-23 15:46 ` [RFC v11 42/55] target/arm: move kvm post init initialization to kvm cpu accel Claudio Fontana
2021-03-23 15:46 ` [RFC v11 43/55] target/arm: add tcg cpu accel class Claudio Fontana
2021-03-23 15:46 ` [RFC v11 44/55] target/arm: move TCG gt timer creation code in tcg/ Claudio Fontana
2021-03-23 15:46 ` [RFC v11 45/55] target/arm: cpu-sve: new module Claudio Fontana
2021-03-25 18:40   ` Richard Henderson
2021-03-25 18:48     ` Claudio Fontana [this message]
2021-03-26 13:35       ` Claudio Fontana
2021-03-23 15:46 ` [RFC v11 46/55] target/arm: cpu-sve: split TCG and KVM functionality Claudio Fontana
2021-03-25 18:44   ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 47/55] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64 Claudio Fontana
2021-03-25 19:03   ` Richard Henderson
2021-03-25 21:56     ` Claudio Fontana
2021-03-26 19:05     ` Claudio Fontana
2021-03-26 19:13       ` Claudio Fontana
2021-03-27 12:59       ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 48/55] target/arm: arch_dump: restrict ELFCLASS64 to AArch64 Claudio Fontana
2021-03-25 19:05   ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 49/55] target/arm: cpu-exceptions: new module Claudio Fontana
2021-03-23 15:46 ` [RFC v11 50/55] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64 Claudio Fontana
2021-03-23 15:46 ` [RFC v11 51/55] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication Claudio Fontana
2021-03-23 15:46 ` [RFC v11 52/55] target/arm: refactor arm_cpu_finalize_features into cpu64 Claudio Fontana
2021-03-23 15:46 ` [RFC v11 53/55] XXX target/arm: experiment refactoring cpu "max" Claudio Fontana
2021-03-23 15:46 ` [RFC v11 54/55] target/arm: tcg: remove superfluous CONFIG_TCG check Claudio Fontana
2021-03-23 15:46 ` [RFC v11 55/55] target/arm: remove v7m stub function for !CONFIG_TCG Claudio Fontana

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=143fde2e-6c88-8fef-10ff-523c574e0db4@suse.de \
    --to=cfontana@suse.de \
    --cc=alex.bennee@linaro.org \
    --cc=ehabkost@redhat.com \
    --cc=pbonzini@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=philmd@redhat.com \
    --cc=qemu-devel@nongnu.org \
    --cc=r.bolshakov@yadro.com \
    --cc=richard.henderson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).