From: Claudio Fontana <cfontana@suse.de>
To: "Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Roman Bolshakov <r.bolshakov@yadro.com>,
Claudio Fontana <cfontana@suse.de>,
Eduardo Habkost <ehabkost@redhat.com>,
qemu-devel@nongnu.org
Subject: [RFC v11 51/55] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication
Date: Tue, 23 Mar 2021 16:46:35 +0100 [thread overview]
Message-ID: <20210323154639.23477-44-cfontana@suse.de> (raw)
In-Reply-To: <20210323151749.21299-1-cfontana@suse.de>
Pointer Authentication is an AARCH64-only ARMv8.3 optional
extension, whose cpu properties can be separated out in its own module.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/arm/cpu.h | 13 +-------
target/arm/tcg/cpu-pauth.h | 38 ++++++++++++++++++++++
target/arm/cpu.c | 3 +-
target/arm/cpu64.c | 34 +-------------------
target/arm/tcg/cpu-pauth.c | 66 ++++++++++++++++++++++++++++++++++++++
target/arm/tcg/meson.build | 1 +
6 files changed, 108 insertions(+), 47 deletions(-)
create mode 100644 target/arm/tcg/cpu-pauth.h
create mode 100644 target/arm/tcg/cpu-pauth.c
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 662ac5ee62..e9cfb99ad9 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -203,6 +203,7 @@ typedef struct {
#ifdef TARGET_AARCH64
# define ARM_MAX_VQ 16
# include "cpu-sve.h"
+# include "tcg/cpu-pauth.h"
#else
# define ARM_MAX_VQ 1
#endif /* TARGET_AARCH64 */
@@ -211,18 +212,6 @@ typedef struct ARMVectorReg {
uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
} ARMVectorReg;
-/* ARMv8.3 Pointer Authentication Extension (AARCH64-only) */
-
-#ifdef TARGET_AARCH64
-void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
-/* In AArch32 mode, PAC keys do not exist at all. */
-typedef struct ARMPACKey {
- uint64_t lo, hi;
-} ARMPACKey;
-#else
-static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { }
-#endif
-
typedef struct CPUARMState {
/* Regs for current mode. */
uint32_t regs[16];
diff --git a/target/arm/tcg/cpu-pauth.h b/target/arm/tcg/cpu-pauth.h
new file mode 100644
index 0000000000..5b130cdada
--- /dev/null
+++ b/target/arm/tcg/cpu-pauth.h
@@ -0,0 +1,38 @@
+/*
+ * QEMU AArch64 Pointer Authentication Extensions
+ *
+ * Copyright (c) 2013 Linaro Ltd
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+
+#ifndef CPU_PAUTH_H
+#define CPU_PAUTH_H
+
+/* ARMv8.3 pauth is an AARCH64 option, only include this for TARGET_AARCH64 */
+
+/* called by arm_cpu_finalize_features in realizefn */
+bool cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
+
+/* add the CPU Pointer Authentication properties */
+void cpu_pauth_add_props(Object *obj);
+
+/* Pointer Authentication Code Key */
+
+typedef struct ARMPACKey {
+ uint64_t lo, hi;
+} ARMPACKey;
+
+#endif /* CPU_PAUTH_H */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 195fe49fbf..82c55b4820 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -832,8 +832,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
* is in use, so the user will not be able to set them.
*/
if (tcg_enabled()) {
- arm_cpu_pauth_finalize(cpu, &local_err);
- if (local_err != NULL) {
+ if (!cpu_pauth_finalize(cpu, &local_err)) {
error_propagate(errp, local_err);
return;
}
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 70345fbecb..9bc5ddfc09 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -245,36 +245,6 @@ static void aarch64_a72_initfn(Object *obj)
define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
}
-void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
-{
- int arch_val = 0, impdef_val = 0;
- uint64_t t;
-
- /* TODO: Handle HaveEnhancedPAC, HaveEnhancedPAC2, HaveFPAC. */
- if (cpu->prop_pauth) {
- if (cpu->prop_pauth_impdef) {
- impdef_val = 1;
- } else {
- arch_val = 1;
- }
- } else if (cpu->prop_pauth_impdef) {
- error_setg(errp, "cannot enable pauth-impdef without pauth");
- error_append_hint(errp, "Add pauth=on to the CPU property list.\n");
- }
-
- t = cpu->isar.id_aa64isar1;
- t = FIELD_DP64(t, ID_AA64ISAR1, APA, arch_val);
- t = FIELD_DP64(t, ID_AA64ISAR1, GPA, arch_val);
- t = FIELD_DP64(t, ID_AA64ISAR1, API, impdef_val);
- t = FIELD_DP64(t, ID_AA64ISAR1, GPI, impdef_val);
- cpu->isar.id_aa64isar1 = t;
-}
-
-static Property arm_cpu_pauth_property =
- DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true);
-static Property arm_cpu_pauth_impdef_property =
- DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false);
-
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
* otherwise, a CPU with as many features enabled as our emulation supports.
* The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
@@ -433,9 +403,7 @@ static void aarch64_max_initfn(Object *obj)
cpu->dcz_blocksize = 7; /* 512 bytes */
#endif
- /* Default to PAUTH on, with the architected algorithm. */
- qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property);
- qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property);
+ cpu_pauth_add_props(obj);
}
cpu_sve_add_props(obj);
diff --git a/target/arm/tcg/cpu-pauth.c b/target/arm/tcg/cpu-pauth.c
new file mode 100644
index 0000000000..4f087923ac
--- /dev/null
+++ b/target/arm/tcg/cpu-pauth.c
@@ -0,0 +1,66 @@
+/*
+ * QEMU AArch64 Pointer Authentication Extensions
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "sysemu/tcg.h"
+#include "tcg/cpu-pauth.h"
+#include "hw/qdev-properties.h"
+
+bool cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
+{
+ bool result = true;
+ int arch_val = 0, impdef_val = 0;
+ uint64_t t;
+
+ /* TODO: Handle HaveEnhancedPAC, HaveEnhancedPAC2, HaveFPAC. */
+ if (cpu->prop_pauth) {
+ if (cpu->prop_pauth_impdef) {
+ impdef_val = 1;
+ } else {
+ arch_val = 1;
+ }
+ } else if (cpu->prop_pauth_impdef) {
+ error_setg(errp, "cannot enable pauth-impdef without pauth");
+ error_append_hint(errp, "Add pauth=on to the CPU property list.\n");
+ result = false;
+ }
+
+ t = cpu->isar.id_aa64isar1;
+ t = FIELD_DP64(t, ID_AA64ISAR1, APA, arch_val);
+ t = FIELD_DP64(t, ID_AA64ISAR1, GPA, arch_val);
+ t = FIELD_DP64(t, ID_AA64ISAR1, API, impdef_val);
+ t = FIELD_DP64(t, ID_AA64ISAR1, GPI, impdef_val);
+ cpu->isar.id_aa64isar1 = t;
+ return result;
+}
+
+static Property arm_cpu_pauth_property =
+ DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true);
+static Property arm_cpu_pauth_impdef_property =
+ DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false);
+
+void cpu_pauth_add_props(Object *obj)
+{
+ /* Default to PAUTH on, with the architected algorithm. */
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property);
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property);
+}
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index d22e5efb84..47d80a06f5 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -40,6 +40,7 @@ arm_ss.add(when: ['TARGET_AARCH64', 'CONFIG_TCG'], if_true: files(
'pauth_helper.c',
'sve_helper.c',
'cpu-sve.c',
+ 'cpu-pauth.c',
))
subdir('user')
--
2.26.2
next prev parent reply other threads:[~2021-03-23 16:27 UTC|newest]
Thread overview: 110+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-23 15:16 [RFC v11 00/55] arm cleanup experiment for kvm-only build Claudio Fontana
2021-03-23 15:16 ` [RFC v11 01/55] target/arm: move translate modules to tcg/ Claudio Fontana
2021-03-23 15:16 ` [RFC v11 02/55] target/arm: move helpers " Claudio Fontana
2021-03-23 15:16 ` [RFC v11 03/55] arm: tcg: only build under CONFIG_TCG Claudio Fontana
2021-03-23 15:16 ` [RFC v11 04/55] target/arm: tcg: add sysemu and user subdirs Claudio Fontana
2021-03-24 18:06 ` Richard Henderson
2021-03-24 18:18 ` Richard Henderson
2021-03-24 18:21 ` Claudio Fontana
2021-03-23 15:16 ` [RFC v11 05/55] target/arm: tcg: split mte_helper user-only and sysemu code Claudio Fontana
2021-03-24 18:15 ` Richard Henderson
2021-03-23 15:17 ` [RFC v11 06/55] target/arm: tcg: move sysemu-only parts of debug_helper Claudio Fontana
2021-03-24 18:19 ` Richard Henderson
2021-03-23 15:17 ` [RFC v11 07/55] target/arm: tcg: split tlb_helper user-only and sysemu-only parts Claudio Fontana
2021-03-24 18:20 ` Richard Henderson
2021-03-23 15:45 ` [RFC v11 08/55] target/arm: tcg: split m_helper " Claudio Fontana
2021-03-24 18:21 ` Richard Henderson
2021-03-23 15:45 ` [RFC v11 09/55] target/arm: only build psci for TCG Claudio Fontana
2021-03-23 15:45 ` [RFC v11 10/55] target/arm: split off cpu-sysemu.c Claudio Fontana
2021-03-24 18:24 ` Richard Henderson
2021-03-23 15:45 ` [RFC v11 11/55] target/arm: move physical address translation to cpu-mmu Claudio Fontana
2021-03-24 18:31 ` Richard Henderson
2021-03-23 15:45 ` [RFC v11 12/55] target/arm: cpu-mmu: fix comment style Claudio Fontana
2021-03-24 18:32 ` Richard Henderson
2021-03-23 15:45 ` [RFC v11 13/55] target/arm: split cpregs from tcg/helper.c Claudio Fontana
2021-03-24 18:40 ` Richard Henderson
2021-03-23 15:45 ` [RFC v11 14/55] target/arm: cpregs: fix style (mostly just comments) Claudio Fontana
2021-03-24 18:40 ` Richard Henderson
2021-03-23 15:45 ` [RFC v11 15/55] target/arm: move cpu definitions to common cpu module Claudio Fontana
2021-03-24 18:42 ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 16/55] target/arm: only perform TCG cpu and machine inits if TCG enabled Claudio Fontana
2021-03-24 18:44 ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 17/55] target/arm: kvm: add stubs for some helpers Claudio Fontana
2021-03-24 18:46 ` Richard Henderson
2021-03-24 18:54 ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 18/55] target/arm: move cpsr_read, cpsr_write to cpu_common Claudio Fontana
2021-03-24 18:47 ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 19/55] target/arm: add temporary stub for arm_rebuild_hflags Claudio Fontana
2021-03-24 18:56 ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 20/55] target/arm: split vfp state setting from tcg helpers Claudio Fontana
2021-03-24 20:29 ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 21/55] target/arm: move arm_mmu_idx* to cpu-mmu Claudio Fontana
2021-03-24 20:31 ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 22/55] target/arm: move sve_zcr_len_for_el to common_cpu Claudio Fontana
2021-03-24 22:03 ` Richard Henderson
2021-03-25 21:44 ` Claudio Fontana
2021-03-23 15:46 ` [RFC v11 23/55] target/arm: move arm_sctlr away from tcg helpers Claudio Fontana
2021-03-24 22:07 ` Richard Henderson
2021-03-25 14:26 ` Claudio Fontana
2021-03-23 15:46 ` [RFC v11 24/55] target/arm: move arm_cpu_list to common_cpu Claudio Fontana
2021-03-23 15:46 ` [RFC v11 25/55] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code Claudio Fontana
2021-03-24 22:11 ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 26/55] target/arm: split a15 cpu model and 32bit class functions to cpu32.c Claudio Fontana
2021-03-24 22:17 ` Richard Henderson
2021-03-25 14:30 ` Claudio Fontana
2021-03-23 15:46 ` [RFC v11 27/55] target/arm: move sve_exception_el out of TCG helpers Claudio Fontana
2021-03-24 22:24 ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 28/55] target/arm: refactor exception and cpu code Claudio Fontana
2021-03-24 22:29 ` Richard Henderson
2021-03-25 11:59 ` Claudio Fontana
2021-03-25 18:43 ` Richard Henderson
2021-03-25 18:50 ` Claudio Fontana
2021-03-23 15:46 ` [RFC v11 29/55] target/arm: cpu: fix style Claudio Fontana
2021-03-24 22:29 ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 30/55] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Claudio Fontana
2021-03-23 22:50 ` Alex Bennée
2021-03-24 8:29 ` Claudio Fontana
2021-03-24 11:41 ` Alex Bennée
2021-03-24 11:48 ` Alex Bennée
2021-03-24 14:34 ` Claudio Fontana
2021-03-24 16:30 ` Alex Bennée
2021-03-24 22:30 ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 31/55] target/arm: remove kvm include file for PSCI and arm-powerctl Claudio Fontana
2021-03-24 22:30 ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 32/55] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/ Claudio Fontana
2021-03-24 22:35 ` Richard Henderson
2021-03-25 15:14 ` Claudio Fontana
2021-03-23 15:46 ` [RFC v11 33/55] target/arm: cleanup cpu includes Claudio Fontana
2021-03-23 15:46 ` [RFC v11 34/55] target/arm: remove broad "else" statements when checking accels Claudio Fontana
2021-03-24 22:37 ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 35/55] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM Claudio Fontana
2021-03-23 15:46 ` [RFC v11 36/55] tests: restrict TCG-only arm-cpu-features tests to TCG builds Claudio Fontana
2021-03-23 15:46 ` [RFC v11 37/55] tests: do not run test-hmp on all machines for ARM KVM-only Claudio Fontana
2021-03-23 15:46 ` [RFC v11 38/55] tests: device-introspect-test: cope with ARM TCG-only devices Claudio Fontana
2021-03-23 15:46 ` [RFC v11 39/55] tests: do not run qom-test on all machines for ARM KVM-only Claudio Fontana
2021-03-23 15:46 ` [RFC v11 40/55] Revert "target/arm: Restrict v8M IDAU to TCG" Claudio Fontana
2021-03-23 15:46 ` [RFC v11 41/55] target/arm: create kvm cpu accel class Claudio Fontana
2021-03-23 15:46 ` [RFC v11 42/55] target/arm: move kvm post init initialization to kvm cpu accel Claudio Fontana
2021-03-23 15:46 ` [RFC v11 43/55] target/arm: add tcg cpu accel class Claudio Fontana
2021-03-23 15:46 ` [RFC v11 44/55] target/arm: move TCG gt timer creation code in tcg/ Claudio Fontana
2021-03-23 15:46 ` [RFC v11 45/55] target/arm: cpu-sve: new module Claudio Fontana
2021-03-25 18:40 ` Richard Henderson
2021-03-25 18:48 ` Claudio Fontana
2021-03-26 13:35 ` Claudio Fontana
2021-03-23 15:46 ` [RFC v11 46/55] target/arm: cpu-sve: split TCG and KVM functionality Claudio Fontana
2021-03-25 18:44 ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 47/55] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64 Claudio Fontana
2021-03-25 19:03 ` Richard Henderson
2021-03-25 21:56 ` Claudio Fontana
2021-03-26 19:05 ` Claudio Fontana
2021-03-26 19:13 ` Claudio Fontana
2021-03-27 12:59 ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 48/55] target/arm: arch_dump: restrict ELFCLASS64 to AArch64 Claudio Fontana
2021-03-25 19:05 ` Richard Henderson
2021-03-23 15:46 ` [RFC v11 49/55] target/arm: cpu-exceptions: new module Claudio Fontana
2021-03-23 15:46 ` [RFC v11 50/55] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64 Claudio Fontana
2021-03-23 15:46 ` Claudio Fontana [this message]
2021-03-23 15:46 ` [RFC v11 52/55] target/arm: refactor arm_cpu_finalize_features into cpu64 Claudio Fontana
2021-03-23 15:46 ` [RFC v11 53/55] XXX target/arm: experiment refactoring cpu "max" Claudio Fontana
2021-03-23 15:46 ` [RFC v11 54/55] target/arm: tcg: remove superfluous CONFIG_TCG check Claudio Fontana
2021-03-23 15:46 ` [RFC v11 55/55] target/arm: remove v7m stub function for !CONFIG_TCG Claudio Fontana
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