From: Greg Kurz <groug@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: lvivier@redhat.com, qemu-devel@nongnu.org, paulus@samba.org,
clg@kaod.org, qemu-ppc@nongnu.org, philmd@redhat.com
Subject: Re: [PATCH v2 02/10] ppc: Remove stub of PPC970 HID4 implementation
Date: Wed, 8 Jan 2020 09:11:23 +0100 [thread overview]
Message-ID: <20200108091123.79ad7e76@bahia.lan> (raw)
In-Reply-To: <20200108010850.GJ2137@umbus.fritz.box>
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On Wed, 8 Jan 2020 12:08:50 +1100
David Gibson <david@gibson.dropbear.id.au> wrote:
> On Tue, Jan 07, 2020 at 06:36:38PM +0100, Greg Kurz wrote:
> > On Tue, 7 Jan 2020 18:32:15 +0100
> > Greg Kurz <groug@kaod.org> wrote:
> >
> > > On Tue, 7 Jan 2020 15:48:19 +1100
> > > David Gibson <david@gibson.dropbear.id.au> wrote:
> > >
> > > > The PowerPC 970 CPU was a cut-down POWER4, which had hypervisor capability.
> > > > However, it can be (and often was) strapped into "Apple mode", where the
> > > > hypervisor capabilities were disabled (essentially putting it always in
> > > > hypervisor mode).
> >
> > Isn't it supervisor mode instead of hypervisor mode ?
>
> No; hypervisor is correct. If the cpu was always in supervisor mode,
> the boot OS couldn't access the hypervisor privileged registers that
> are needed for basic setup (e.g. SDR1). "Apple mode" means the cpu
> doesn't have a supervisor mode that _isn't_ hypervisor privileged and
> hence, can't run guests.
>
Ok, thanks for the clarification.
> >
> > > >
> > > > That's actually the only mode of the 970 we support in qemu, and we're
> > > > unlikely to change that any time soon. However, we do have a partial
> > > > implementation of the 970's HID4 register which affects things only
> > > > relevant for hypervisor mode.
> > > >
> > > > That stub is also really ugly, since it attempts to duplicate the effects
> > > > of HID4 by re-encoding it into the LPCR register used in newer CPUs, but
> > > > in a really confusing way.
> > > >
> > > > Just get rid of it.
> > > >
> > > > Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> > > > ---
> > >
> > > Reviewed-by: Greg Kurz <groug@kaod.org>
> > >
> > > > target/ppc/mmu-hash64.c | 28 +---------------------------
> > > > target/ppc/translate_init.inc.c | 17 ++++++-----------
> > > > 2 files changed, 7 insertions(+), 38 deletions(-)
> > > >
> > > > diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> > > > index da8966ccf5..a881876647 100644
> > > > --- a/target/ppc/mmu-hash64.c
> > > > +++ b/target/ppc/mmu-hash64.c
> > > > @@ -1091,33 +1091,6 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
> > > >
> > > > /* Filter out bits */
> > > > switch (env->mmu_model) {
> > > > - case POWERPC_MMU_64B: /* 970 */
> > > > - if (val & 0x40) {
> > > > - lpcr |= LPCR_LPES0;
> > > > - }
> > > > - if (val & 0x8000000000000000ull) {
> > > > - lpcr |= LPCR_LPES1;
> > > > - }
> > > > - if (val & 0x20) {
> > > > - lpcr |= (0x4ull << LPCR_RMLS_SHIFT);
> > > > - }
> > > > - if (val & 0x4000000000000000ull) {
> > > > - lpcr |= (0x2ull << LPCR_RMLS_SHIFT);
> > > > - }
> > > > - if (val & 0x2000000000000000ull) {
> > > > - lpcr |= (0x1ull << LPCR_RMLS_SHIFT);
> > > > - }
> > > > - env->spr[SPR_RMOR] = ((lpcr >> 41) & 0xffffull) << 26;
> > > > -
> > > > - /*
> > > > - * XXX We could also write LPID from HID4 here
> > > > - * but since we don't tag any translation on it
> > > > - * it doesn't actually matter
> > > > - *
> > > > - * XXX For proper emulation of 970 we also need
> > > > - * to dig HRMOR out of HID5
> > > > - */
> > > > - break;
> > > > case POWERPC_MMU_2_03: /* P5p */
> > > > lpcr = val & (LPCR_RMLS | LPCR_ILE |
> > > > LPCR_LPES0 | LPCR_LPES1 |
> > > > @@ -1154,6 +1127,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
> > > > }
> > > > break;
> > > > default:
> > > > + g_assert_not_reached();
> > > > ;
> > > > }
> > > > env->spr[SPR_LPCR] = lpcr;
> > > > diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
> > > > index d33d65dff7..436d0d5a51 100644
> > > > --- a/target/ppc/translate_init.inc.c
> > > > +++ b/target/ppc/translate_init.inc.c
> > > > @@ -7884,25 +7884,20 @@ static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
> > > > {
> > > > gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
> > > > }
> > > > -
> > > > -static void spr_write_970_hid4(DisasContext *ctx, int sprn, int gprn)
> > > > -{
> > > > -#if defined(TARGET_PPC64)
> > > > - spr_write_generic(ctx, sprn, gprn);
> > > > - gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
> > > > -#endif
> > > > -}
> > > > -
> > > > #endif /* !defined(CONFIG_USER_ONLY) */
> > > >
> > > > static void gen_spr_970_lpar(CPUPPCState *env)
> > > > {
> > > > #if !defined(CONFIG_USER_ONLY)
> > > > /* Logical partitionning */
> > > > - /* PPC970: HID4 is effectively the LPCR */
> > > > + /* PPC970: HID4 covers things later controlled by the LPCR and
> > > > + * RMOR in later CPUs, but with a different encoding. We only
> > > > + * support the 970 in "Apple mode" which has all hypervisor
> > > > + * facilities disabled by strapping, so we can basically just
> > > > + * ignore it */
> > > > spr_register(env, SPR_970_HID4, "HID4",
> > > > SPR_NOACCESS, SPR_NOACCESS,
> > > > - &spr_read_generic, &spr_write_970_hid4,
> > > > + &spr_read_generic, &spr_write_generic,
> > > > 0x00000000);
> > > > #endif
> > > > }
> > >
> > >
> >
>
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next prev parent reply other threads:[~2020-01-08 8:12 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-07 4:48 [PATCH v2 00/10] target/ppc: Correct some errors with real mode handling David Gibson
2020-01-07 4:48 ` [PATCH v2 01/10] ppc: Drop PPC_EMULATE_32BITS_HYPV stub David Gibson
2020-01-07 12:52 ` Cédric Le Goater
2020-01-07 17:05 ` Greg Kurz
2020-01-07 4:48 ` [PATCH v2 02/10] ppc: Remove stub of PPC970 HID4 implementation David Gibson
2020-01-07 12:51 ` Cédric Le Goater
2020-01-07 17:32 ` Greg Kurz
2020-01-07 17:36 ` Greg Kurz
2020-01-07 18:05 ` BALATON Zoltan
2020-01-08 1:09 ` David Gibson
2020-01-08 8:29 ` Thomas Huth
2020-01-08 1:08 ` David Gibson
2020-01-08 8:11 ` Greg Kurz [this message]
2020-01-08 2:17 ` Paul Mackerras
2020-01-08 13:35 ` Greg Kurz
2020-01-07 4:48 ` [PATCH v2 03/10] target/ppc: Correct handling of real mode accesses with vhyp on hash MMU David Gibson
2020-01-14 10:22 ` Cédric Le Goater
2020-01-07 4:48 ` [PATCH v2 04/10] target/ppc: Introduce ppc_hash64_use_vrma() helper David Gibson
2020-01-07 13:24 ` Cédric Le Goater
2020-01-07 4:48 ` [PATCH v2 05/10] spapr, ppc: Remove VPM0/RMLS hacks for POWER9 David Gibson
2020-01-07 14:35 ` Cédric Le Goater
2020-01-09 7:33 ` Alexey Kardashevskiy
2020-01-13 3:38 ` David Gibson
2020-01-07 4:48 ` [PATCH v2 06/10] target/ppc: Remove RMOR register from POWER9 & POWER10 David Gibson
2020-01-07 13:39 ` Cédric Le Goater
2020-01-07 4:48 ` [PATCH v2 07/10] target/ppc: Use class fields to simplify LPCR masking David Gibson
2020-01-07 13:41 ` Cédric Le Goater
2020-01-07 4:48 ` [PATCH v2 08/10] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS] David Gibson
2020-01-07 13:43 ` Cédric Le Goater
2020-01-07 4:48 ` [PATCH v2 09/10] target/ppc: Correct RMLS table David Gibson
2020-01-07 14:21 ` Cédric Le Goater
2020-01-08 1:06 ` David Gibson
2020-01-08 8:29 ` Cédric Le Goater
2020-01-09 7:46 ` Alexey Kardashevskiy
2020-01-13 3:46 ` David Gibson
2020-01-08 8:28 ` Cédric Le Goater
2020-01-07 4:48 ` [PATCH v2 10/10] target/ppc: Only calculate RMLS derived RMA limit on demand David Gibson
2020-01-08 8:31 ` Cédric Le Goater
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