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From: "Cédric Le Goater" <clg@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>,
	qemu-devel@nongnu.org, groug@kaod.org, philmd@redhat.com
Cc: aik@ozlabs.ru, Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
	qemu-ppc@nongnu.org, lvivier@redhat.com, paulus@samba.org
Subject: Re: [PATCH v2 08/10] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS]
Date: Tue, 7 Jan 2020 14:43:15 +0100	[thread overview]
Message-ID: <a5f22049-2c99-043e-53a9-93c8947f0b02@kaod.org> (raw)
In-Reply-To: <20200107044827.471355-9-david@gibson.dropbear.id.au>

On 1/7/20 5:48 AM, David Gibson wrote:
> Currently we use a big switch statement in ppc_hash64_update_rmls() to work
> out what the right RMA limit is based on the LPCR[RMLS] field.  There's no
> formula for this - it's just an arbitrary mapping defined by the existing
> CPU implementations - but we can make it a bit more readable by using a
> lookup table rather than a switch.  In addition we can use the MiB/GiB
> symbols to make it a bit clearer.
> 
> While there we add a bit of clarity and rationale to the comment about
> what happens if the LPCR[RMLS] doesn't contain a valid value.
> 
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>

Reviewed-by: Cédric Le Goater <clg@kaod.org>


> ---
>  target/ppc/mmu-hash64.c | 71 ++++++++++++++++++++---------------------
>  1 file changed, 35 insertions(+), 36 deletions(-)
> 
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index 127b7250ae..bb9ebeaf48 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -18,6 +18,7 @@
>   * License along with this library; if not, see <http://www.gnu.org/licenses/>.
>   */
>  #include "qemu/osdep.h"
> +#include "qemu/units.h"
>  #include "cpu.h"
>  #include "exec/exec-all.h"
>  #include "exec/helper-proto.h"
> @@ -755,6 +756,39 @@ static void ppc_hash64_set_c(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1)
>      stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80);
>  }
>  
> +static target_ulong rmls_limit(PowerPCCPU *cpu)
> +{
> +    CPUPPCState *env = &cpu->env;
> +    /*
> +     * This is the full 4 bits encoding of POWER8. Previous
> +     * CPUs only support a subset of these but the filtering
> +     * is done when writing LPCR
> +     */
> +    const target_ulong rma_sizes[] = {
> +        [0] = 0,
> +        [1] = 16 * GiB,
> +        [2] = 1 * GiB,
> +        [3] = 64 * MiB,
> +        [4] = 256 * MiB,
> +        [5] = 0,
> +        [6] = 0,
> +        [7] = 128 * MiB,
> +        [8] = 32 * MiB,
> +    };
> +    target_ulong rmls = (env->spr[SPR_LPCR] & LPCR_RMLS) >> LPCR_RMLS_SHIFT;
> +
> +    if (rmls < ARRAY_SIZE(rma_sizes)) {
> +        return rma_sizes[rmls];
> +    } else {
> +        /*
> +         * Bad value, so the OS has shot itself in the foot.  Return a
> +         * 0-sized RMA which we expect to trigger an immediate DSI or
> +         * ISI
> +         */
> +        return 0;
> +    }
> +}
> +
>  int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
>                                  int rwx, int mmu_idx)
>  {
> @@ -1004,41 +1038,6 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
>      cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH;
>  }
>  
> -static void ppc_hash64_update_rmls(PowerPCCPU *cpu)
> -{
> -    CPUPPCState *env = &cpu->env;
> -    uint64_t lpcr = env->spr[SPR_LPCR];
> -
> -    /*
> -     * This is the full 4 bits encoding of POWER8. Previous
> -     * CPUs only support a subset of these but the filtering
> -     * is done when writing LPCR
> -     */
> -    switch ((lpcr & LPCR_RMLS) >> LPCR_RMLS_SHIFT) {
> -    case 0x8: /* 32MB */
> -        env->rmls = 0x2000000ull;
> -        break;
> -    case 0x3: /* 64MB */
> -        env->rmls = 0x4000000ull;
> -        break;
> -    case 0x7: /* 128MB */
> -        env->rmls = 0x8000000ull;
> -        break;
> -    case 0x4: /* 256MB */
> -        env->rmls = 0x10000000ull;
> -        break;
> -    case 0x2: /* 1GB */
> -        env->rmls = 0x40000000ull;
> -        break;
> -    case 0x1: /* 16GB */
> -        env->rmls = 0x400000000ull;
> -        break;
> -    default:
> -        /* What to do here ??? */
> -        env->rmls = 0;
> -    }
> -}
> -
>  static void ppc_hash64_update_vrma(PowerPCCPU *cpu)
>  {
>      CPUPPCState *env = &cpu->env;
> @@ -1097,7 +1096,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
>      CPUPPCState *env = &cpu->env;
>  
>      env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
> -    ppc_hash64_update_rmls(cpu);
> +    env->rmls = rmls_limit(cpu);
>      ppc_hash64_update_vrma(cpu);
>  }
>  
> 



  reply	other threads:[~2020-01-07 14:18 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-07  4:48 [PATCH v2 00/10] target/ppc: Correct some errors with real mode handling David Gibson
2020-01-07  4:48 ` [PATCH v2 01/10] ppc: Drop PPC_EMULATE_32BITS_HYPV stub David Gibson
2020-01-07 12:52   ` Cédric Le Goater
2020-01-07 17:05   ` Greg Kurz
2020-01-07  4:48 ` [PATCH v2 02/10] ppc: Remove stub of PPC970 HID4 implementation David Gibson
2020-01-07 12:51   ` Cédric Le Goater
2020-01-07 17:32   ` Greg Kurz
2020-01-07 17:36     ` Greg Kurz
2020-01-07 18:05       ` BALATON Zoltan
2020-01-08  1:09         ` David Gibson
2020-01-08  8:29         ` Thomas Huth
2020-01-08  1:08       ` David Gibson
2020-01-08  8:11         ` Greg Kurz
2020-01-08  2:17       ` Paul Mackerras
2020-01-08 13:35   ` Greg Kurz
2020-01-07  4:48 ` [PATCH v2 03/10] target/ppc: Correct handling of real mode accesses with vhyp on hash MMU David Gibson
2020-01-14 10:22   ` Cédric Le Goater
2020-01-07  4:48 ` [PATCH v2 04/10] target/ppc: Introduce ppc_hash64_use_vrma() helper David Gibson
2020-01-07 13:24   ` Cédric Le Goater
2020-01-07  4:48 ` [PATCH v2 05/10] spapr, ppc: Remove VPM0/RMLS hacks for POWER9 David Gibson
2020-01-07 14:35   ` Cédric Le Goater
2020-01-09  7:33   ` Alexey Kardashevskiy
2020-01-13  3:38     ` David Gibson
2020-01-07  4:48 ` [PATCH v2 06/10] target/ppc: Remove RMOR register from POWER9 & POWER10 David Gibson
2020-01-07 13:39   ` Cédric Le Goater
2020-01-07  4:48 ` [PATCH v2 07/10] target/ppc: Use class fields to simplify LPCR masking David Gibson
2020-01-07 13:41   ` Cédric Le Goater
2020-01-07  4:48 ` [PATCH v2 08/10] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS] David Gibson
2020-01-07 13:43   ` Cédric Le Goater [this message]
2020-01-07  4:48 ` [PATCH v2 09/10] target/ppc: Correct RMLS table David Gibson
2020-01-07 14:21   ` Cédric Le Goater
2020-01-08  1:06     ` David Gibson
2020-01-08  8:29       ` Cédric Le Goater
2020-01-09  7:46       ` Alexey Kardashevskiy
2020-01-13  3:46         ` David Gibson
2020-01-08  8:28   ` Cédric Le Goater
2020-01-07  4:48 ` [PATCH v2 10/10] target/ppc: Only calculate RMLS derived RMA limit on demand David Gibson
2020-01-08  8:31   ` Cédric Le Goater

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